Solutions to hands-on assignment #2

Three levels of memory are visible in the data we handed out, typically called L1 cache, L2 cache, and main memory. An L1 cache is usually on the same chunk of silicon as the CPU. L2 caches are usually built from separate chips, which are often fast, expensive, and not very dense. Main memory is built from separate "DRAM" chips, which are relatively slow, cheap, and dense.

1. M1 has 2 levels (L1 and main memory, the first tiny spike is noise). Both M2 and M3 have 3 levels (L1, L2 and main memory).

2. Sizes of RAM and cache are usually in multiples of powers of 2.

       L1 for M1 is 8K
       L1 for M2 is 8k
       L1 for M3 is 16K
       L2 for M2 is 256K
       L2 for M3 is 512K
   

   You may determine these numbers by observing where a huge jump in latency occurs. Such a jump implies that the data can no longer fit into the particular memory hierarchy.

3. L1 for M1, M2, M3 are 15, 20, 7 ns respectively. L2 for M2 is 30 ns. L2 for M3 is 50 ns. The latency for main memory in M1, M2, and M3 are 210, 200, 160 ns.

4. No, each generation is not entirely better than the preceding. M3 has better main memory latency, but worse L2 latency than M2. M1 has better L1 latency than M2, but worse than M3.

5. M3 has a larger L2 cache, but it's slower. This is a trade off between cache size and latency.

6. The ratios are 220/160 and 15/7. The latency of L1 cache, usually on chip, is affected by processor speed. Processors are improving at a faster rate than memory and bus technology, as can be seen from the figure 6 of the lecture notes. Therefore, when memory size is 1k, M3 performs much better.

Some other notes:

• Some people did not turn in results for their own machine. Please read the instructions carefully and turn in what is asked for.
• Please be careful to check your assignments for typos. It's especially important when it's easy to forget to change an M2 to M3.
• Some of the graphs submitted had somewhat erratic latencies. This might have been because the data were generated on a loaded machine. Since a machine only has one cache hierarchy for all of its processors, multiple active programs could have caused the memory the test program was accessing to get evicted from the cache.