|Prerequisites||Students should feel comfortable using computers. A rudimentary knowledge of electrical/computer fundamentals (6.002 or 6.08) is helpful but not required. As with all project courses the end-of-term crunch can be an issue, so it would be unwise to take another course that also has a significant design project due at the end of term.|
|Units||6.111 is a 12 unit (3-7-2) course with a substantial laboratory component (7 hours per week). The final six weeks -- 72 course hours -- of the semester are devoted to the final project.|
|Lectures||TR 2:30p - 4p in 32-141. Lectures are not held during the last six weeks of the course so that you can focus on the final project. See the course calendar for a detailed schedule.|
There is no required text for the course, but we recommend the following
book if you would like a more thorough treatment of some of the topics covered
R. H. Katz, G. Borriello
There are many good Verilog books; we strongly recommend that you have access to one. Several Verilog books are available for in-lab checkout from the staff.
D. E. Thomas, P. R. Moorby
|Handouts||On-line versions of the handouts (in PDF) can be found at this website.|
|Lecture Problems||A short problem set will be handed out during each lecture and your written solution will be due at the start of the following lecture. These should help you practice the design skills introduced by the lecture. Your solutions will be graded and returned.|
|Quizzes||There are no quizzes or final exam.|
The 6.111 lab is located on the sixth floor of Building 38 (room 38-600). During business hours you can enter via the lab doors from the Building 36 elevator lobby. After business hours the sixth floor entrance is locked and alarmed so you need to enter and leave on the fifth floor and take the internal stairs up to the 6.111 lab. The usual hours of operation are
These times are subject to change, particularly around holidays ; check the signs near the lab entrance and make your plans accordingly. The lab will be staffed by Teaching Assistants (TAs) or Lab Aides (LAs) for some, but not all, of these hours.
Each student will be issued their own lab supplies including a protoboard, a collection of components used in the assignments, a pair of scope probes and some hand tools. While wiring and some debugging can be done at home, most assignments require the use of an oscilloscope, logic analyzer and other special equipment, all of which are available in the lab. The FPGA Laboratory Kit can be found at each lab bench. Additional equipment and parts may be checked out from the course staff.
Remember to put your name on anything that you build in the laboratory and leave unattended, otherwise it may be gone when you return. There are some lockers for the safe storage of your supplies along the 6th floor entry corridor; to get one for the semester please ask the course staff.
There are five lab assignments to be completed individually. For some labs you will be asked to upload your Verilog code in addition to completing a checkoff with a member of the course staff. Checkoffs can happen anytime the lab is staffed and by appointment. There is a 20%/day late penalty for work completed 1 to 5 working days after the due date.
Note that each lab has multiple, often substantial, tasks you need to complete and it is unlikely that you'll be able to complete the work in one sitting (e.g., the day the lab is due). The lab and staff are very busy just before an assignment is due so please plan accordingly.
Note: you must complete all the labs before starting the final project. We've learned over the years that if you're struggling with the labs then it's unlikely that you'll be able to successfully complete a final project.
The Final Project is the most important assignment -- you'll get to design and implement a small digital system of your own choosing, working with one or at most two partners. The last six weeks of the term are devoted exclusively to working on the project and its accompanying report. We'll be providing lots of information about the project as the term progresses, but here's a quick list of the project milestones. See the project info page for details.
A project proposal, project presentation and a final report will be required.
The Departmental Guidelines Relating to Academic Honesty require that
we inform you of our expectations regarding permissible academic
The lecture problems and labs should be done individually. You are welcome to get help from others but the work you hand in must be your own. Copying another person's work or allowing your work to be copied by others is a serious academic offense and will be treated as such by the course staff.
The final grade is determined by your performance on the lecture problems, labs,
and final project:
Some of the factors considered in asssign the final grade are:
Traditionally, the average performance (and hence grade) has been quite high in 6.111. A large number of students do "A" level work and are indeed rewarded with a grade of "A". The corollary to this is that, since average performance levels are so high, punting any part of the subject can lead to a disappointing grade. It's very important to keep up with the work.
Incompletes will not be given.