Integrated Logic Analyzer ILA (2019-1)

A physical logic analyzer is simply a digital system that samples various probes and displays the signal. Since generally not all the gates are used in a FPGA, why not use parts of the FPGA to synthesize a logic analyzer? That's exactly an Integrated Logic Analzyer ILA.

The feature of the full feature system edition of Vivado allows you to view your actual signals in your design with a synthesized logic analyzer. To view the signals, additional signals are place and routed but used internally to display the waveforms. Obviously, to run, your design must synthesize and loaded to the FPGA.

An ILA Tutorial
Download your project file and create a create a project. In this example we will use the pong game in lab 3.

Add ILA to your design. Under Project Manager, select IP Catalog. Expand /Debug & Verification/Debug and add ILA from the catalog or search for ILA.



• For this example, add logic analyzer three probes for debugging.
  1. Select Native.
  2. Select the appropriate number of samples, 1024 in this example. Caution: the samples uses BRAM on the FPGA and reduces the amount available.
  3. Capture Control allows storing data based on user parameters.
  4. Advance Trigger allows selection of events to trigger the ILA.
  5. Do not click OK as this point. Click on Probe_Ports (green arrow) tab which will take you to the next screen.

  
  
  

• Logic analyzer probes are created and named.
  probe0 will be used to display hysnc.
  probe1 will be used to display hcount (current column on the screen), width 11.
  probe2 will be used to display rgb (the value of the current pixel), width 12.

  
  
  

• Click OK and an ila_0 Verilog module is created. The ports are defined in the module.

    module ila_0 (
              clk,
              probe0,
              probe1,
              probe2
              );
  
    input clk;
    input [0 : 0] probe0;
    input [10 : 0] probe1;  
    input [11 : 0] probe2; 
  
  

  
  
  

• In order to view the signals, the logic analyer probes must be instantiated in your design. The clock (clk) for ILA is generally the system clock, clk_65mhz in this example.
  Instantiate ila_0 in your project:

     ila_0  myila(.clk(clk_65mhz),.probe0(hsync),.probe1(hcount),.probe2(pixel));
  

  
  
  

• Synthesize, implement and generate and load the bit stream to the target.
  
  
• To display the waveforms
  • select hw_ila_1
  • click run or right click with mouse on hw_ila1
  • add Trigger Setup as needed.
  The waveform can be displayed as digital and/or analog format. Right click and select.

  In this example, the signals hsync, hcoount and rgb are displayed. hcoount is displayed as an analog waveform (ramp increasing from zero). rgb is displayed in hex format. The trigger is set to hcoount = 000. The rgb rotate through black 000, blue 00F, green 0F0, cyan 0FF, red F00, magenta F0F, yellow FF0, and white FFF.

  Important: after an ILA is added, the program device dialog will autodetect both the bit stream and a debug probes file, and only after the fpga is programmed with a debug probes file will the hardware manager show the ILA. Real signals are displayed on the ILA.