Creating ROM/RAM with Vivado

The following are instructions for creating block RAM or ROM, using Vivado. The image captures were from Windows 10 running Vivado 19.1. There are options for creating single or dual port memories. In most applications, only a single port memory is required. You may find dual port useful for your final project.

Under your project add a new source using IP Catalog and select "Block Memory Generator" [Click]. Block memory is silicon in the FPGA dedicated and optimized for creating memory. Distribured memory creates memory by using flip flops when performance is needed but consumes significant resources and area on the chip.



Create a single port ROM and and give it a filename [image_rom in this example] in your project folder.


Under Port A Options, create the 8 bit wide ROM for a 256x240 image (= 61440 depth). Select "Always Enabled". Otherwise an enable port must be created. If not, a black screen will result.


For ROMs, the memory is initialized with COE files. Under Other Options, provide a memory initization (COE) file and check "Load Init File".


The generation of the ROMs creates .veo files in the project folder. The contents of the .veo files list the ports names needed to instantiate the ROM memory. Here is an example of the port names for our image rom:


// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.

//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
image_rom YourInstanceName (
	.clka(clka),
	.addra(addra), // Bus [15 : 0] 
	.douta(douta)); // Bus [7 : 0] 

// INST_TAG_END ------ End INSTANTIATION Template ---------

The content of the COE file is a listng of the value for each address in the memory. Here is the content of a COE file:

We have MATLAB scripts that extracts the pixel values from BMP files and creates a COE file.