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XILINX EXPRESSLY DISCLAIMS ANY * * WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * * IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * * REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * * INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * * FOR A PARTICULAR PURPOSE. * * * * Xilinx products are not intended for use in life support * * appliances, devices, or systems. Use in such applications are * * expressly prohibited. * * * * (c) Copyright 1995-2004 Xilinx, Inc. * * All rights reserved. * *******************************************************************************/ /* Behavioural components instantiated: C_REG_FD_V7_0 C_GATE_BIT_V7_0 C_DIST_MEM_V7_0 C_SHIFT_FD_V7_0 C_ADDSUB_V7_0 */ `timescale 1ns/1ps module dds_8bit( DATA, WE, A, CLK, CE, RDY, SINE, COSINE ); // synthesis black_box input [20 : 0] DATA; input WE; input [4 : 0] A; input CLK; input CE; output RDY; output [7 : 0] SINE; output [7 : 0] COSINE; //synopsys translate_off wire n0 = 1'b0; wire n1 = 1'b1; wire n2; wire n3; wire n4; wire n5; wire n6; wire n7; wire n8; wire n19; wire n20; wire n21; wire n22; wire n23; wire n24; wire n25; wire n26; wire n27; wire n28; wire n29; wire n30; wire n31; wire n32; wire n33; wire n34; wire n35; wire n36; wire n37; wire n38; wire n39; wire n40; wire n41; wire n42; wire n43; wire n44; wire n45; wire n46; wire n47; wire n48; wire n49; wire n50; wire n51; wire n52; wire n53; wire n54; wire n55; wire n56; wire n82; wire n83; wire n84; wire n85; wire n86; wire n87; wire n88; wire n89; wire n90; wire n91; wire n92; wire n93; wire n94; wire n95; wire n96; wire n97; wire n98; wire n99; wire n100; wire n101; wire n102; wire n109; wire n110; wire n111; wire n112; wire n113; wire n114; wire n115; wire n116; wire n117; wire n118; wire n119; wire n120; wire n121; wire n122; wire n123; wire n124; wire n125; wire n126; wire n127; wire n173; wire n174; wire n175; wire n176; wire n177; wire n178; wire n179; wire n180; wire n181; wire n182; wire n183; wire n184; wire n185; wire n186; wire n187; wire n188; wire n189; wire n190; wire n191; wire n192; wire n193; wire n795; wire n796; wire n797; wire n798; wire n799; wire n800; wire n801; wire n802; wire n803; wire n804; wire n805; wire n806; wire n845; wire n846; wire n847; wire n848; wire n849; wire n850; wire n851; wire n852; wire n853; wire n854; wire n855; wire n896; wire n897; wire n898; wire n899; wire n900; wire n901; wire n902; wire n903; wire n904; wire n905; wire n906; wire n907; wire n908; wire n909; wire n910; wire n911; wire n912; wire n913; wire n914; wire n951; wire n952; wire n953; wire n954; wire n955; wire n956; wire n957; wire n958; wire n959; wire n960; wire n961; wire n1004; wire n1005; wire n1006; wire n1007; wire n1008; wire n1009; wire n1010; wire n1011; wire n1012; wire n1648; wire n1649; wire n1650; wire n1651; wire n1652; wire n1653; wire n1654; wire n1659; wire n1660; wire n1661; wire n1662; wire n1663; wire n1664; wire n1665; wire n1666; wire n1684; assign n82 = DATA[0]; assign n83 = DATA[1]; assign n84 = DATA[2]; assign n85 = DATA[3]; assign n86 = DATA[4]; assign n87 = DATA[5]; assign n88 = DATA[6]; assign n89 = DATA[7]; assign n90 = DATA[8]; assign n91 = DATA[9]; assign n92 = DATA[10]; assign n93 = DATA[11]; assign n94 = DATA[12]; assign n95 = DATA[13]; assign n96 = DATA[14]; assign n97 = DATA[15]; assign n98 = DATA[16]; assign n99 = DATA[17]; assign n100 = DATA[18]; assign n101 = DATA[19]; assign n102 = DATA[20]; assign n8 = WE; assign n3 = A[0]; assign n4 = A[1]; assign n5 = A[2]; assign n6 = A[3]; assign n7 = A[4]; assign n109 = CLK; assign n110 = CE; assign RDY = n111; assign SINE[0] = n112; assign SINE[1] = n113; assign SINE[2] = n114; assign SINE[3] = n115; assign SINE[4] = n116; assign SINE[5] = n117; assign SINE[6] = n118; assign SINE[7] = n119; assign COSINE[0] = n120; assign COSINE[1] = n121; assign COSINE[2] = n122; assign COSINE[3] = n123; assign COSINE[4] = n124; assign COSINE[5] = n125; assign COSINE[6] = n126; assign COSINE[7] = n127; wire [5 : 0] BU2_I; assign BU2_I[0] = n3; assign BU2_I[1] = n4; assign BU2_I[2] = n5; assign BU2_I[3] = n6; assign BU2_I[4] = n7; assign BU2_I[5] = n8; wire BU2_T; assign BU2_T = 1'b0; wire BU2_EN; assign BU2_EN = 1'b0; wire BU2_Q; wire BU2_CLK; assign BU2_CLK = 1'b0; wire BU2_CE; assign BU2_CE = 1'b0; wire BU2_ACLR; assign BU2_ACLR = 1'b0; wire BU2_ASET; assign BU2_ASET = 1'b0; wire BU2_AINIT; assign BU2_AINIT = 1'b0; wire BU2_SCLR; assign BU2_SCLR = 1'b0; wire BU2_SSET; assign BU2_SSET = 1'b0; wire BU2_SINIT; assign BU2_SINIT = 1'b0; wire BU2_O; assign n2 = BU2_O; C_GATE_BIT_V7_0 #( "0" /* c_ainit_val*/, 0 /* c_enable_rlocs*/, 0 /* c_gate_type*/, 0 /* c_has_aclr*/, 0 /* c_has_ainit*/, 0 /* c_has_aset*/, 0 /* c_has_ce*/, 1 /* c_has_o*/, 1 /* c_has_q*/, 0 /* c_has_sclr*/, 0 /* c_has_sinit*/, 0 /* c_has_sset*/, 6 /* c_inputs*/, "011111" /* c_input_inv_mask*/, 0 /* c_pipe_stages*/, "0" /* c_sinit_val*/, 0 /* c_sync_enable*/, 1 /* c_sync_priority*/ ) BU2( .I(BU2_I), .T(BU2_T), .EN(BU2_EN), .Q(BU2_Q), .CLK(BU2_CLK), .CE(BU2_CE), .ACLR(BU2_ACLR), .ASET(BU2_ASET), .AINIT(BU2_AINIT), .SCLR(BU2_SCLR), .SSET(BU2_SSET), .SINIT(BU2_SINIT), .O(BU2_O) ); wire [20 : 0] BU12_D; assign BU12_D[0] = n82; assign BU12_D[1] = n83; assign BU12_D[2] = n84; assign BU12_D[3] = n85; assign BU12_D[4] = n86; assign BU12_D[5] = n87; assign BU12_D[6] = n88; assign BU12_D[7] = n89; assign BU12_D[8] = n90; assign BU12_D[9] = n91; assign BU12_D[10] = n92; assign BU12_D[11] = n93; assign BU12_D[12] = n94; assign BU12_D[13] = n95; assign BU12_D[14] = n96; assign BU12_D[15] = n97; assign BU12_D[16] = n98; assign BU12_D[17] = n99; assign BU12_D[18] = n100; assign BU12_D[19] = n101; assign BU12_D[20] = n102; wire [20 : 0] BU12_Q; assign n173 = BU12_Q[0]; assign n174 = BU12_Q[1]; assign n175 = BU12_Q[2]; assign n176 = BU12_Q[3]; assign n177 = BU12_Q[4]; assign n178 = BU12_Q[5]; assign n179 = BU12_Q[6]; assign n180 = BU12_Q[7]; assign n181 = BU12_Q[8]; assign n182 = BU12_Q[9]; assign n183 = BU12_Q[10]; assign n184 = BU12_Q[11]; assign n185 = BU12_Q[12]; assign n186 = BU12_Q[13]; assign n187 = BU12_Q[14]; assign n188 = BU12_Q[15]; assign n189 = BU12_Q[16]; assign n190 = BU12_Q[17]; assign n191 = BU12_Q[18]; assign n192 = BU12_Q[19]; assign n193 = BU12_Q[20]; wire BU12_CLK; assign BU12_CLK = n109; wire BU12_CE; assign BU12_CE = n2; C_REG_FD_V7_0 #( "000000000000000000000" /* c_ainit_val*/, 0 /* c_enable_rlocs*/, 0 /* c_has_aclr*/, 0 /* c_has_ainit*/, 0 /* c_has_aset*/, 1 /* c_has_ce*/, 0 /* c_has_sclr*/, 0 /* c_has_sinit*/, 0 /* c_has_sset*/, "000000000000000000000" /* c_sinit_val*/, 0 /* c_sync_enable*/, 0 /* c_sync_priority*/, 21 /* c_width*/ ) BU12( .D(BU12_D), .Q(BU12_Q), .CLK(BU12_CLK), .CE(BU12_CE) ); wire [20 : 0] BU56_A; assign BU56_A[0] = n19; assign BU56_A[1] = n20; assign BU56_A[2] = n21; assign BU56_A[3] = n22; assign BU56_A[4] = n23; assign BU56_A[5] = n24; assign BU56_A[6] = n25; assign BU56_A[7] = n26; assign BU56_A[8] = n27; assign BU56_A[9] = n28; assign BU56_A[10] = n29; assign BU56_A[11] = n30; assign BU56_A[12] = n31; assign BU56_A[13] = n32; assign BU56_A[14] = n33; assign BU56_A[15] = n34; assign BU56_A[16] = n35; assign BU56_A[17] = n36; assign BU56_A[18] = n37; assign BU56_A[19] = n38; assign BU56_A[20] = n39; wire [20 : 0] BU56_B; assign BU56_B[0] = n173; assign BU56_B[1] = n174; assign BU56_B[2] = n175; assign BU56_B[3] = n176; assign BU56_B[4] = n177; assign BU56_B[5] = n178; assign BU56_B[6] = n179; assign BU56_B[7] = n180; assign BU56_B[8] = n181; assign BU56_B[9] = n182; assign BU56_B[10] = n183; assign BU56_B[11] = n184; assign BU56_B[12] = n185; assign BU56_B[13] = n186; assign BU56_B[14] = n187; assign BU56_B[15] = n188; assign BU56_B[16] = n189; assign BU56_B[17] = n190; assign BU56_B[18] = n191; assign BU56_B[19] = n192; assign BU56_B[20] = n193; wire [20 : 0] BU56_Q; assign n19 = BU56_Q[0]; assign n20 = BU56_Q[1]; assign n21 = BU56_Q[2]; assign n22 = BU56_Q[3]; assign n23 = BU56_Q[4]; assign n24 = BU56_Q[5]; assign n25 = BU56_Q[6]; assign n26 = BU56_Q[7]; assign n27 = BU56_Q[8]; assign n28 = BU56_Q[9]; assign n29 = BU56_Q[10]; assign n30 = BU56_Q[11]; assign n31 = BU56_Q[12]; assign n32 = BU56_Q[13]; assign n33 = BU56_Q[14]; assign n34 = BU56_Q[15]; assign n35 = BU56_Q[16]; assign n36 = BU56_Q[17]; assign n37 = BU56_Q[18]; assign n38 = BU56_Q[19]; assign n39 = BU56_Q[20]; wire BU56_CLK; assign BU56_CLK = n109; wire BU56_CE; assign BU56_CE = n110; C_ADDSUB_V7_0 #( 0 /* c_add_mode*/, "000000000000000000000" /* c_ainit_val*/, 1 /* c_a_type*/, 21 /* c_a_width*/, 1 /* c_bypass_enable*/, 0 /* c_bypass_low*/, 0 /* c_b_constant*/, 1 /* c_b_type*/, "000000000000000000000" /* c_b_value*/, 21 /* c_b_width*/, 0 /* c_enable_rlocs*/, 0 /* c_has_aclr*/, 0 /* c_has_add*/, 0 /* c_has_ainit*/, 0 /* c_has_aset*/, 0 /* c_has_a_signed*/, 0 /* c_has_bypass*/, 0 /* c_has_bypass_with_cin*/, 0 /* c_has_b_in*/, 0 /* c_has_b_out*/, 0 /* c_has_b_signed*/, 1 /* c_has_ce*/, 0 /* c_has_c_in*/, 0 /* c_has_c_out*/, 0 /* c_has_ovfl*/, 1 /* c_has_q*/, 0 /* c_has_q_b_out*/, 0 /* c_has_q_c_out*/, 0 /* c_has_q_ovfl*/, 1 /* c_has_s*/, 0 /* c_has_sclr*/, 0 /* c_has_sinit*/, 0 /* c_has_sset*/, 20 /* c_high_bit*/, 1 /* c_latency*/, 0 /* c_low_bit*/, 21 /* c_out_width*/, 0 /* c_pipe_stages*/, "000000000000000000000" /* c_sinit_val*/, 0 /* c_sync_enable*/, 0 /* c_sync_priority*/ ) BU56( .A(BU56_A), .B(BU56_B), .Q(BU56_Q), .CLK(BU56_CLK), .CE(BU56_CE) ); wire BU182_CLK; assign BU182_CLK = n109; wire BU182_SDOUT; assign n40 = BU182_SDOUT; wire BU182_CE; assign BU182_CE = n110; C_SHIFT_FD_V7_0 #( "0" /* c_ainit_val*/, 0 /* c_enable_rlocs*/, 1 /* c_fill_data*/, 0 /* c_has_aclr*/, 0 /* c_has_ainit*/, 0 /* c_has_aset*/, 1 /* c_has_ce*/, 0 /* c_has_d*/, 0 /* c_has_lsb_2_msb*/, 0 /* c_has_q*/, 0 /* c_has_sclr*/, 0 /* c_has_sdin*/, 1 /* c_has_sdout*/, 0 /* c_has_sinit*/, 0 /* c_has_sset*/, 1 /* c_shift_type*/, "0" /* c_sinit_val*/, 0 /* c_sync_enable*/, 1 /* c_sync_priority*/, 1 /* c_width*/ ) BU182( .CLK(BU182_CLK), .SDOUT(BU182_SDOUT), .CE(BU182_CE) ); wire [14 : 0] BU506_A; assign BU506_A[0] = n25; assign BU506_A[1] = n26; assign BU506_A[2] = n27; assign BU506_A[3] = n28; assign BU506_A[4] = n29; assign BU506_A[5] = n30; assign BU506_A[6] = n31; assign BU506_A[7] = n32; assign BU506_A[8] = n33; assign BU506_A[9] = n34; assign BU506_A[10] = n35; assign BU506_A[11] = n36; assign BU506_A[12] = n37; assign BU506_A[13] = n38; assign BU506_A[14] = n39; wire [9 : 0] BU506_B; assign BU506_B[0] = n47; assign BU506_B[1] = n48; assign BU506_B[2] = n49; assign BU506_B[3] = n50; assign BU506_B[4] = n51; assign BU506_B[5] = n52; assign BU506_B[6] = n53; assign BU506_B[7] = n54; assign BU506_B[8] = n55; assign BU506_B[9] = n56; wire [5 : 0] BU506_Q; assign n41 = BU506_Q[0]; assign n42 = BU506_Q[1]; assign n43 = BU506_Q[2]; assign n44 = BU506_Q[3]; assign n45 = BU506_Q[4]; assign n46 = BU506_Q[5]; wire BU506_CLK; assign BU506_CLK = n109; wire BU506_CE; assign BU506_CE = n110; C_ADDSUB_V7_0 #( 0 /* c_add_mode*/, "000000" /* c_ainit_val*/, 1 /* c_a_type*/, 15 /* c_a_width*/, 1 /* c_bypass_enable*/, 0 /* c_bypass_low*/, 0 /* c_b_constant*/, 0 /* c_b_type*/, "000000000000000" /* c_b_value*/, 10 /* c_b_width*/, 0 /* c_enable_rlocs*/, 0 /* c_has_aclr*/, 0 /* c_has_add*/, 0 /* c_has_ainit*/, 0 /* c_has_aset*/, 0 /* c_has_a_signed*/, 0 /* c_has_bypass*/, 0 /* c_has_bypass_with_cin*/, 0 /* c_has_b_in*/, 0 /* c_has_b_out*/, 0 /* c_has_b_signed*/, 1 /* c_has_ce*/, 0 /* c_has_c_in*/, 0 /* c_has_c_out*/, 0 /* c_has_ovfl*/, 1 /* c_has_q*/, 0 /* c_has_q_b_out*/, 0 /* c_has_q_c_out*/, 0 /* c_has_q_ovfl*/, 1 /* c_has_s*/, 0 /* c_has_sclr*/, 0 /* c_has_sinit*/, 0 /* c_has_sset*/, 14 /* c_high_bit*/, 1 /* c_latency*/, 9 /* c_low_bit*/, 6 /* c_out_width*/, 0 /* c_pipe_stages*/, "000000" /* c_sinit_val*/, 0 /* c_sync_enable*/, 0 /* c_sync_priority*/ ) BU506( .A(BU506_A), .B(BU506_B), .Q(BU506_Q), .CLK(BU506_CLK), .CE(BU506_CE) ); wire [8 : 0] BU445_A; assign BU445_A[0] = n896; assign BU445_A[1] = n897; assign BU445_A[2] = n898; assign BU445_A[3] = n899; assign BU445_A[4] = n900; assign BU445_A[5] = n901; assign BU445_A[6] = n902; assign BU445_A[7] = n903; assign BU445_A[8] = n904; wire [8 : 0] BU445_B; assign BU445_B[0] = n1004; assign BU445_B[1] = n1005; assign BU445_B[2] = n1006; assign BU445_B[3] = n1007; assign BU445_B[4] = n1008; assign BU445_B[5] = n1009; assign BU445_B[6] = n1010; assign BU445_B[7] = n1011; assign BU445_B[8] = n1012; wire [9 : 0] BU445_Q; assign n47 = BU445_Q[0]; assign n48 = BU445_Q[1]; assign n49 = BU445_Q[2]; assign n50 = BU445_Q[3]; assign n51 = BU445_Q[4]; assign n52 = BU445_Q[5]; assign n53 = BU445_Q[6]; assign n54 = BU445_Q[7]; assign n55 = BU445_Q[8]; assign n56 = BU445_Q[9]; wire BU445_CLK; assign BU445_CLK = n109; wire BU445_CE; assign BU445_CE = n110; C_ADDSUB_V7_0 #( 0 /* c_add_mode*/, "0000000000" /* c_ainit_val*/, 0 /* c_a_type*/, 9 /* c_a_width*/, 0 /* c_bypass_enable*/, 0 /* c_bypass_low*/, 0 /* c_b_constant*/, 0 /* c_b_type*/, "0000000000" /* c_b_value*/, 9 /* c_b_width*/, 0 /* c_enable_rlocs*/, 0 /* c_has_aclr*/, 0 /* c_has_add*/, 0 /* c_has_ainit*/, 0 /* c_has_aset*/, 0 /* c_has_a_signed*/, 0 /* c_has_bypass*/, 0 /* c_has_bypass_with_cin*/, 0 /* c_has_b_in*/, 0 /* c_has_b_out*/, 0 /* c_has_b_signed*/, 1 /* c_has_ce*/, 0 /* c_has_c_in*/, 0 /* c_has_c_out*/, 0 /* c_has_ovfl*/, 1 /* c_has_q*/, 0 /* c_has_q_b_out*/, 0 /* c_has_q_c_out*/, 0 /* c_has_q_ovfl*/, 1 /* c_has_s*/, 0 /* c_has_sclr*/, 0 /* c_has_sinit*/, 0 /* c_has_sset*/, 9 /* c_high_bit*/, 1 /* c_latency*/, 0 /* c_low_bit*/, 10 /* c_out_width*/, 0 /* c_pipe_stages*/, "0000000000" /* c_sinit_val*/, 0 /* c_sync_enable*/, 0 /* c_sync_priority*/ ) BU445( .A(BU445_A), .B(BU445_B), .Q(BU445_Q), .CLK(BU445_CLK), .CE(BU445_CE) ); wire [7 : 0] BU259_A; assign BU259_A[0] = n795; assign BU259_A[1] = n796; assign BU259_A[2] = n797; assign BU259_A[3] = n798; assign BU259_A[4] = n799; assign BU259_A[5] = n800; assign BU259_A[6] = n801; assign BU259_A[7] = n802; wire [7 : 0] BU259_B; assign BU259_B[0] = n845; assign BU259_B[1] = n846; assign BU259_B[2] = n847; assign BU259_B[3] = n848; assign BU259_B[4] = n849; assign BU259_B[5] = n850; assign BU259_B[6] = n851; assign BU259_B[7] = n852; wire [8 : 0] BU259_Q; assign n896 = BU259_Q[0]; assign n897 = BU259_Q[1]; assign n898 = BU259_Q[2]; assign n899 = BU259_Q[3]; assign n900 = BU259_Q[4]; assign n901 = BU259_Q[5]; assign n902 = BU259_Q[6]; assign n903 = BU259_Q[7]; assign n904 = BU259_Q[8]; wire BU259_CLK; assign BU259_CLK = n109; wire BU259_CE; assign BU259_CE = n110; C_ADDSUB_V7_0 #( 0 /* c_add_mode*/, "000000000" /* c_ainit_val*/, 0 /* c_a_type*/, 8 /* c_a_width*/, 0 /* c_bypass_enable*/, 0 /* c_bypass_low*/, 0 /* c_b_constant*/, 0 /* c_b_type*/, "000000000" /* c_b_value*/, 8 /* c_b_width*/, 0 /* c_enable_rlocs*/, 0 /* c_has_aclr*/, 0 /* c_has_add*/, 0 /* c_has_ainit*/, 0 /* c_has_aset*/, 0 /* c_has_a_signed*/, 0 /* c_has_bypass*/, 0 /* c_has_bypass_with_cin*/, 0 /* c_has_b_in*/, 0 /* c_has_b_out*/, 0 /* c_has_b_signed*/, 1 /* c_has_ce*/, 0 /* c_has_c_in*/, 0 /* c_has_c_out*/, 0 /* c_has_ovfl*/, 1 /* c_has_q*/, 0 /* c_has_q_b_out*/, 0 /* c_has_q_c_out*/, 0 /* c_has_q_ovfl*/, 1 /* c_has_s*/, 0 /* c_has_sclr*/, 0 /* c_has_sinit*/, 0 /* c_has_sset*/, 8 /* c_high_bit*/, 1 /* c_latency*/, 0 /* c_low_bit*/, 9 /* c_out_width*/, 0 /* c_pipe_stages*/, "000000000" /* c_sinit_val*/, 0 /* c_sync_enable*/, 0 /* c_sync_priority*/ ) BU259( .A(BU259_A), .B(BU259_B), .Q(BU259_Q), .CLK(BU259_CLK), .CE(BU259_CE) ); wire [3 : 0] BU190_I; assign BU190_I[0] = n804; assign BU190_I[1] = n805; assign BU190_I[2] = n806; assign BU190_I[3] = n802; wire BU190_T; assign BU190_T = 1'b0; wire BU190_EN; assign BU190_EN = 1'b0; wire BU190_Q; wire BU190_CLK; assign BU190_CLK = 1'b0; wire BU190_CE; assign BU190_CE = 1'b0; wire BU190_ACLR; assign BU190_ACLR = 1'b0; wire BU190_ASET; assign BU190_ASET = 1'b0; wire BU190_AINIT; assign BU190_AINIT = 1'b0; wire BU190_SCLR; assign BU190_SCLR = 1'b0; wire BU190_SSET; assign BU190_SSET = 1'b0; wire BU190_SINIT; assign BU190_SINIT = 1'b0; wire BU190_O; assign n803 = BU190_O; C_GATE_BIT_V7_0 #( "0" /* c_ainit_val*/, 0 /* c_enable_rlocs*/, 4 /* c_gate_type*/, 0 /* c_has_aclr*/, 0 /* c_has_ainit*/, 0 /* c_has_aset*/, 0 /* c_has_ce*/, 1 /* c_has_o*/, 1 /* c_has_q*/, 0 /* c_has_sclr*/, 0 /* c_has_sinit*/, 0 /* c_has_sset*/, 4 /* c_inputs*/, "0000" /* c_input_inv_mask*/, 0 /* c_pipe_stages*/, "0" /* c_sinit_val*/, 0 /* c_sync_enable*/, 1 /* c_sync_priority*/ ) BU190( .I(BU190_I), .T(BU190_T), .EN(BU190_EN), .Q(BU190_Q), .CLK(BU190_CLK), .CE(BU190_CE), .ACLR(BU190_ACLR), .ASET(BU190_ASET), .AINIT(BU190_AINIT), .SCLR(BU190_SCLR), .SSET(BU190_SSET), .SINIT(BU190_SINIT), .O(BU190_O) ); wire BU195_CLK; assign BU195_CLK = n109; wire BU195_SDIN; assign BU195_SDIN = n803; wire [12 : 0] BU195_Q; assign n804 = BU195_Q[0]; assign n805 = BU195_Q[2]; assign n806 = BU195_Q[3]; assign n795 = BU195_Q[5]; assign n796 = BU195_Q[6]; assign n797 = BU195_Q[7]; assign n798 = BU195_Q[8]; assign n799 = BU195_Q[9]; assign n800 = BU195_Q[10]; assign n801 = BU195_Q[11]; assign n802 = BU195_Q[12]; wire BU195_CE; assign BU195_CE = n110; C_SHIFT_FD_V7_0 #( "1000000000000" /* c_ainit_val*/, 0 /* c_enable_rlocs*/, 5 /* c_fill_data*/, 0 /* c_has_aclr*/, 0 /* c_has_ainit*/, 0 /* c_has_aset*/, 1 /* c_has_ce*/, 0 /* c_has_d*/, 0 /* c_has_lsb_2_msb*/, 1 /* c_has_q*/, 0 /* c_has_sclr*/, 1 /* c_has_sdin*/, 0 /* c_has_sdout*/, 0 /* c_has_sinit*/, 0 /* c_has_sset*/, 0 /* c_shift_type*/, "1000000000000" /* c_sinit_val*/, 0 /* c_sync_enable*/, 0 /* c_sync_priority*/, 13 /* c_width*/ ) BU195( .CLK(BU195_CLK), .SDIN(BU195_SDIN), .Q(BU195_Q), .CE(BU195_CE) ); wire [3 : 0] BU224_I; assign BU224_I[0] = n854; assign BU224_I[1] = n855; assign BU224_I[2] = n848; assign BU224_I[3] = n852; wire BU224_T; assign BU224_T = 1'b0; wire BU224_EN; assign BU224_EN = 1'b0; wire BU224_Q; wire BU224_CLK; assign BU224_CLK = 1'b0; wire BU224_CE; assign BU224_CE = 1'b0; wire BU224_ACLR; assign BU224_ACLR = 1'b0; wire BU224_ASET; assign BU224_ASET = 1'b0; wire BU224_AINIT; assign BU224_AINIT = 1'b0; wire BU224_SCLR; assign BU224_SCLR = 1'b0; wire BU224_SSET; assign BU224_SSET = 1'b0; wire BU224_SINIT; assign BU224_SINIT = 1'b0; wire BU224_O; assign n853 = BU224_O; C_GATE_BIT_V7_0 #( "0" /* c_ainit_val*/, 0 /* c_enable_rlocs*/, 4 /* c_gate_type*/, 0 /* c_has_aclr*/, 0 /* c_has_ainit*/, 0 /* c_has_aset*/, 0 /* c_has_ce*/, 1 /* c_has_o*/, 1 /* c_has_q*/, 0 /* c_has_sclr*/, 0 /* c_has_sinit*/, 0 /* c_has_sset*/, 4 /* c_inputs*/, "0000" /* c_input_inv_mask*/, 0 /* c_pipe_stages*/, "0" /* c_sinit_val*/, 0 /* c_sync_enable*/, 1 /* c_sync_priority*/ ) BU224( .I(BU224_I), .T(BU224_T), .EN(BU224_EN), .Q(BU224_Q), .CLK(BU224_CLK), .CE(BU224_CE), .ACLR(BU224_ACLR), .ASET(BU224_ASET), .AINIT(BU224_AINIT), .SCLR(BU224_SCLR), .SSET(BU224_SSET), .SINIT(BU224_SINIT), .O(BU224_O) ); wire BU229_CLK; assign BU229_CLK = n109; wire BU229_SDIN; assign BU229_SDIN = n853; wire [13 : 0] BU229_Q; assign n854 = BU229_Q[0]; assign n855 = BU229_Q[5]; assign n845 = BU229_Q[6]; assign n846 = BU229_Q[7]; assign n847 = BU229_Q[8]; assign n848 = BU229_Q[9]; assign n849 = BU229_Q[10]; assign n850 = BU229_Q[11]; assign n851 = BU229_Q[12]; assign n852 = BU229_Q[13]; wire BU229_CE; assign BU229_CE = n110; C_SHIFT_FD_V7_0 #( "10000000000000" /* c_ainit_val*/, 0 /* c_enable_rlocs*/, 5 /* c_fill_data*/, 0 /* c_has_aclr*/, 0 /* c_has_ainit*/, 0 /* c_has_aset*/, 1 /* c_has_ce*/, 0 /* c_has_d*/, 0 /* c_has_lsb_2_msb*/, 1 /* c_has_q*/, 0 /* c_has_sclr*/, 1 /* c_has_sdin*/, 0 /* c_has_sdout*/, 0 /* c_has_sinit*/, 0 /* c_has_sset*/, 0 /* c_shift_type*/, "10000000000000" /* c_sinit_val*/, 0 /* c_sync_enable*/, 0 /* c_sync_priority*/, 14 /* c_width*/ ) BU229( .CLK(BU229_CLK), .SDIN(BU229_SDIN), .Q(BU229_Q), .CE(BU229_CE) ); wire [7 : 0] BU391_A; assign BU391_A[0] = n905; assign BU391_A[1] = n906; assign BU391_A[2] = n907; assign BU391_A[3] = n908; assign BU391_A[4] = n909; assign BU391_A[5] = n910; assign BU391_A[6] = n911; assign BU391_A[7] = n912; wire [7 : 0] BU391_B; assign BU391_B[0] = n951; assign BU391_B[1] = n952; assign BU391_B[2] = n953; assign BU391_B[3] = n954; assign BU391_B[4] = n955; assign BU391_B[5] = n956; assign BU391_B[6] = n957; assign BU391_B[7] = n958; wire [8 : 0] BU391_Q; assign n1004 = BU391_Q[0]; assign n1005 = BU391_Q[1]; assign n1006 = BU391_Q[2]; assign n1007 = BU391_Q[3]; assign n1008 = BU391_Q[4]; assign n1009 = BU391_Q[5]; assign n1010 = BU391_Q[6]; assign n1011 = BU391_Q[7]; assign n1012 = BU391_Q[8]; wire BU391_CLK; assign BU391_CLK = n109; wire BU391_CE; assign BU391_CE = n110; C_ADDSUB_V7_0 #( 0 /* c_add_mode*/, "000000000" /* c_ainit_val*/, 0 /* c_a_type*/, 8 /* c_a_width*/, 0 /* c_bypass_enable*/, 0 /* c_bypass_low*/, 0 /* c_b_constant*/, 0 /* c_b_type*/, "000000000" /* c_b_value*/, 8 /* c_b_width*/, 0 /* c_enable_rlocs*/, 0 /* c_has_aclr*/, 0 /* c_has_add*/, 0 /* c_has_ainit*/, 0 /* c_has_aset*/, 0 /* c_has_a_signed*/, 0 /* c_has_bypass*/, 0 /* c_has_bypass_with_cin*/, 0 /* c_has_b_in*/, 0 /* c_has_b_out*/, 0 /* c_has_b_signed*/, 1 /* c_has_ce*/, 0 /* c_has_c_in*/, 0 /* c_has_c_out*/, 0 /* c_has_ovfl*/, 1 /* c_has_q*/, 0 /* c_has_q_b_out*/, 0 /* c_has_q_c_out*/, 0 /* c_has_q_ovfl*/, 1 /* c_has_s*/, 0 /* c_has_sclr*/, 0 /* c_has_sinit*/, 0 /* c_has_sset*/, 8 /* c_high_bit*/, 1 /* c_latency*/, 0 /* c_low_bit*/, 9 /* c_out_width*/, 0 /* c_pipe_stages*/, "000000000" /* c_sinit_val*/, 0 /* c_sync_enable*/, 0 /* c_sync_priority*/ ) BU391( .A(BU391_A), .B(BU391_B), .Q(BU391_Q), .CLK(BU391_CLK), .CE(BU391_CE) ); wire [1 : 0] BU314_I; assign BU314_I[0] = n914; assign BU314_I[1] = n912; wire BU314_T; assign BU314_T = 1'b0; wire BU314_EN; assign BU314_EN = 1'b0; wire BU314_Q; wire BU314_CLK; assign BU314_CLK = 1'b0; wire BU314_CE; assign BU314_CE = 1'b0; wire BU314_ACLR; assign BU314_ACLR = 1'b0; wire BU314_ASET; assign BU314_ASET = 1'b0; wire BU314_AINIT; assign BU314_AINIT = 1'b0; wire BU314_SCLR; assign BU314_SCLR = 1'b0; wire BU314_SSET; assign BU314_SSET = 1'b0; wire BU314_SINIT; assign BU314_SINIT = 1'b0; wire BU314_O; assign n913 = BU314_O; C_GATE_BIT_V7_0 #( "0" /* c_ainit_val*/, 0 /* c_enable_rlocs*/, 4 /* c_gate_type*/, 0 /* c_has_aclr*/, 0 /* c_has_ainit*/, 0 /* c_has_aset*/, 0 /* c_has_ce*/, 1 /* c_has_o*/, 1 /* c_has_q*/, 0 /* c_has_sclr*/, 0 /* c_has_sinit*/, 0 /* c_has_sset*/, 2 /* c_inputs*/, "00" /* c_input_inv_mask*/, 0 /* c_pipe_stages*/, "0" /* c_sinit_val*/, 0 /* c_sync_enable*/, 1 /* c_sync_priority*/ ) BU314( .I(BU314_I), .T(BU314_T), .EN(BU314_EN), .Q(BU314_Q), .CLK(BU314_CLK), .CE(BU314_CE), .ACLR(BU314_ACLR), .ASET(BU314_ASET), .AINIT(BU314_AINIT), .SCLR(BU314_SCLR), .SSET(BU314_SSET), .SINIT(BU314_SINIT), .O(BU314_O) ); wire BU319_CLK; assign BU319_CLK = n109; wire BU319_SDIN; assign BU319_SDIN = n913; wire [14 : 0] BU319_Q; assign n914 = BU319_Q[0]; assign n905 = BU319_Q[7]; assign n906 = BU319_Q[8]; assign n907 = BU319_Q[9]; assign n908 = BU319_Q[10]; assign n909 = BU319_Q[11]; assign n910 = BU319_Q[12]; assign n911 = BU319_Q[13]; assign n912 = BU319_Q[14]; wire BU319_CE; assign BU319_CE = n110; C_SHIFT_FD_V7_0 #( "100000000000000" /* c_ainit_val*/, 0 /* c_enable_rlocs*/, 5 /* c_fill_data*/, 0 /* c_has_aclr*/, 0 /* c_has_ainit*/, 0 /* c_has_aset*/, 1 /* c_has_ce*/, 0 /* c_has_d*/, 0 /* c_has_lsb_2_msb*/, 1 /* c_has_q*/, 0 /* c_has_sclr*/, 1 /* c_has_sdin*/, 0 /* c_has_sdout*/, 0 /* c_has_sinit*/, 0 /* c_has_sset*/, 0 /* c_shift_type*/, "100000000000000" /* c_sinit_val*/, 0 /* c_sync_enable*/, 0 /* c_sync_priority*/, 15 /* c_width*/ ) BU319( .CLK(BU319_CLK), .SDIN(BU319_SDIN), .Q(BU319_Q), .CE(BU319_CE) ); wire [3 : 0] BU352_I; assign BU352_I[0] = n960; assign BU352_I[1] = n961; assign BU352_I[2] = n954; assign BU352_I[3] = n958; wire BU352_T; assign BU352_T = 1'b0; wire BU352_EN; assign BU352_EN = 1'b0; wire BU352_Q; wire BU352_CLK; assign BU352_CLK = 1'b0; wire BU352_CE; assign BU352_CE = 1'b0; wire BU352_ACLR; assign BU352_ACLR = 1'b0; wire BU352_ASET; assign BU352_ASET = 1'b0; wire BU352_AINIT; assign BU352_AINIT = 1'b0; wire BU352_SCLR; assign BU352_SCLR = 1'b0; wire BU352_SSET; assign BU352_SSET = 1'b0; wire BU352_SINIT; assign BU352_SINIT = 1'b0; wire BU352_O; assign n959 = BU352_O; C_GATE_BIT_V7_0 #( "0" /* c_ainit_val*/, 0 /* c_enable_rlocs*/, 4 /* c_gate_type*/, 0 /* c_has_aclr*/, 0 /* c_has_ainit*/, 0 /* c_has_aset*/, 0 /* c_has_ce*/, 1 /* c_has_o*/, 1 /* c_has_q*/, 0 /* c_has_sclr*/, 0 /* c_has_sinit*/, 0 /* c_has_sset*/, 4 /* c_inputs*/, "0000" /* c_input_inv_mask*/, 0 /* c_pipe_stages*/, "0" /* c_sinit_val*/, 0 /* c_sync_enable*/, 1 /* c_sync_priority*/ ) BU352( .I(BU352_I), .T(BU352_T), .EN(BU352_EN), .Q(BU352_Q), .CLK(BU352_CLK), .CE(BU352_CE), .ACLR(BU352_ACLR), .ASET(BU352_ASET), .AINIT(BU352_AINIT), .SCLR(BU352_SCLR), .SSET(BU352_SSET), .SINIT(BU352_SINIT), .O(BU352_O) ); wire BU357_CLK; assign BU357_CLK = n109; wire BU357_SDIN; assign BU357_SDIN = n959; wire [15 : 0] BU357_Q; assign n960 = BU357_Q[0]; assign n961 = BU357_Q[2]; assign n951 = BU357_Q[8]; assign n952 = BU357_Q[9]; assign n953 = BU357_Q[10]; assign n954 = BU357_Q[11]; assign n955 = BU357_Q[12]; assign n956 = BU357_Q[13]; assign n957 = BU357_Q[14]; assign n958 = BU357_Q[15]; wire BU357_CE; assign BU357_CE = n110; C_SHIFT_FD_V7_0 #( "1000000000000000" /* c_ainit_val*/, 0 /* c_enable_rlocs*/, 5 /* c_fill_data*/, 0 /* c_has_aclr*/, 0 /* c_has_ainit*/, 0 /* c_has_aset*/, 1 /* c_has_ce*/, 0 /* c_has_d*/, 0 /* c_has_lsb_2_msb*/, 1 /* c_has_q*/, 0 /* c_has_sclr*/, 1 /* c_has_sdin*/, 0 /* c_has_sdout*/, 0 /* c_has_sinit*/, 0 /* c_has_sset*/, 0 /* c_shift_type*/, "1000000000000000" /* c_sinit_val*/, 0 /* c_sync_enable*/, 0 /* c_sync_priority*/, 16 /* c_width*/ ) BU357( .CLK(BU357_CLK), .SDIN(BU357_SDIN), .Q(BU357_Q), .CE(BU357_CE) ); wire [5 : 0] BU746_D; assign BU746_D[0] = n41; assign BU746_D[1] = n42; assign BU746_D[2] = n43; assign BU746_D[3] = n44; assign BU746_D[4] = n45; assign BU746_D[5] = n46; wire [5 : 0] BU746_Q; assign n1649 = BU746_Q[0]; assign n1650 = BU746_Q[1]; assign n1651 = BU746_Q[2]; assign n1652 = BU746_Q[3]; assign n1653 = BU746_Q[4]; assign n1654 = BU746_Q[5]; wire BU746_CLK; assign BU746_CLK = n109; wire BU746_CE; assign BU746_CE = n110; C_REG_FD_V7_0 #( "000000" /* c_ainit_val*/, 0 /* c_enable_rlocs*/, 0 /* c_has_aclr*/, 0 /* c_has_ainit*/, 0 /* c_has_aset*/, 1 /* c_has_ce*/, 0 /* c_has_sclr*/, 0 /* c_has_sinit*/, 0 /* c_has_sset*/, "000000" /* c_sinit_val*/, 0 /* c_sync_enable*/, 0 /* c_sync_priority*/, 6 /* c_width*/ ) BU746( .D(BU746_D), .Q(BU746_Q), .CLK(BU746_CLK), .CE(BU746_CE) ); wire [5 : 0] BU761_D; assign BU761_D[0] = n41; assign BU761_D[1] = n42; assign BU761_D[2] = n43; assign BU761_D[3] = n44; assign BU761_D[4] = n45; assign BU761_D[5] = n46; wire [5 : 0] BU761_Q; assign n1661 = BU761_Q[0]; assign n1662 = BU761_Q[1]; assign n1663 = BU761_Q[2]; assign n1664 = BU761_Q[3]; assign n1659 = BU761_Q[4]; assign n1660 = BU761_Q[5]; wire BU761_CLK; assign BU761_CLK = n109; wire BU761_CE; assign BU761_CE = n110; C_REG_FD_V7_0 #( "000000" /* c_ainit_val*/, 0 /* c_enable_rlocs*/, 0 /* c_has_aclr*/, 0 /* c_has_ainit*/, 0 /* c_has_aset*/, 1 /* c_has_ce*/, 0 /* c_has_sclr*/, 0 /* c_has_sinit*/, 0 /* c_has_sset*/, "000000" /* c_sinit_val*/, 0 /* c_sync_enable*/, 0 /* c_sync_priority*/, 6 /* c_width*/ ) BU761( .D(BU761_D), .Q(BU761_Q), .CLK(BU761_CLK), .CE(BU761_CE) ); defparam BU776.INIT = 'h5555; wire BU776_I0; assign BU776_I0 = n1659; wire BU776_I1; assign BU776_I1 = 1'b0; wire BU776_I2; assign BU776_I2 = 1'b0; wire BU776_I3; assign BU776_I3 = 1'b0; wire BU776_O; assign n1665 = BU776_O; LUT4 BU776( .I0(BU776_I0), .I1(BU776_I1), .I2(BU776_I2), .I3(BU776_I3), .O(BU776_O) ); defparam BU778.INIT = 'h6666; wire BU778_I0; assign BU778_I0 = n1660; wire BU778_I1; assign BU778_I1 = n1659; wire BU778_I2; assign BU778_I2 = 1'b0; wire BU778_I3; assign BU778_I3 = 1'b0; wire BU778_O; assign n1666 = BU778_O; LUT4 BU778( .I0(BU778_I0), .I1(BU778_I1), .I2(BU778_I2), .I3(BU778_I3), .O(BU778_O) ); wire [5 : 0] BU572_A; assign BU572_A[0] = n1649; assign BU572_A[1] = n1650; assign BU572_A[2] = n1651; assign BU572_A[3] = n1652; assign BU572_A[4] = n1653; assign BU572_A[5] = n1654; wire BU572_CLK; assign BU572_CLK = n109; wire BU572_QSPO_CE; assign BU572_QSPO_CE = n1648; wire [7 : 0] BU572_QSPO; assign n112 = BU572_QSPO[0]; assign n113 = BU572_QSPO[1]; assign n114 = BU572_QSPO[2]; assign n115 = BU572_QSPO[3]; assign n116 = BU572_QSPO[4]; assign n117 = BU572_QSPO[5]; assign n118 = BU572_QSPO[6]; assign n119 = BU572_QSPO[7]; C_DIST_MEM_V7_0 #( 6 /* c_addr_width*/, "0" /* c_default_data*/, 2 /* c_default_data_radix*/, 64 /* c_depth*/, 0 /* c_enable_rlocs*/, 0 /* c_generate_mif*/, 1 /* c_has_clk*/, 0 /* c_has_d*/, 0 /* c_has_dpo*/, 0 /* c_has_dpra*/, 0 /* c_has_i_ce*/, 0 /* c_has_qdpo*/, 0 /* c_has_qdpo_ce*/, 0 /* c_has_qdpo_clk*/, 0 /* c_has_qdpo_rst*/, 0 /* c_has_qdpo_srst*/, 1 /* c_has_qspo*/, 1 /* c_has_qspo_ce*/, 0 /* c_has_qspo_rst*/, 0 /* c_has_qspo_srst*/, 0 /* c_has_rd_en*/, 0 /* c_has_spo*/, 0 /* c_has_spra*/, 0 /* c_has_we*/, 1 /* c_latency*/, "dds_800khz_8bit_SINCOS_TABLE_TRIG_ROM.mif" /* c_mem_init_file*/, 0 /* c_mem_type*/, 0 /* c_mux_type*/, 1 /* c_qce_joined*/, 0 /* c_qualify_we*/, 1 /* c_read_mif*/, 0 /* c_reg_a_d_inputs*/, 0 /* c_reg_dpra_input*/, 0 /* c_sync_enable*/, 8 /* c_width*/ ) BU572( .A(BU572_A), .CLK(BU572_CLK), .QSPO_CE(BU572_QSPO_CE), .QSPO(BU572_QSPO) ); wire [5 : 0] BU657_A; assign BU657_A[0] = n1661; assign BU657_A[1] = n1662; assign BU657_A[2] = n1663; assign BU657_A[3] = n1664; assign BU657_A[4] = n1665; assign BU657_A[5] = n1666; wire BU657_CLK; assign BU657_CLK = n109; wire BU657_QSPO_CE; assign BU657_QSPO_CE = n1648; wire [7 : 0] BU657_QSPO; assign n120 = BU657_QSPO[0]; assign n121 = BU657_QSPO[1]; assign n122 = BU657_QSPO[2]; assign n123 = BU657_QSPO[3]; assign n124 = BU657_QSPO[4]; assign n125 = BU657_QSPO[5]; assign n126 = BU657_QSPO[6]; assign n127 = BU657_QSPO[7]; C_DIST_MEM_V7_0 #( 6 /* c_addr_width*/, "0" /* c_default_data*/, 2 /* c_default_data_radix*/, 64 /* c_depth*/, 0 /* c_enable_rlocs*/, 0 /* c_generate_mif*/, 1 /* c_has_clk*/, 0 /* c_has_d*/, 0 /* c_has_dpo*/, 0 /* c_has_dpra*/, 0 /* c_has_i_ce*/, 0 /* c_has_qdpo*/, 0 /* c_has_qdpo_ce*/, 0 /* c_has_qdpo_clk*/, 0 /* c_has_qdpo_rst*/, 0 /* c_has_qdpo_srst*/, 1 /* c_has_qspo*/, 1 /* c_has_qspo_ce*/, 0 /* c_has_qspo_rst*/, 0 /* c_has_qspo_srst*/, 0 /* c_has_rd_en*/, 0 /* c_has_spo*/, 0 /* c_has_spra*/, 0 /* c_has_we*/, 1 /* c_latency*/, "dds_800khz_8bit_SINCOS_TABLE_TRIG_ROM.mif" /* c_mem_init_file*/, 0 /* c_mem_type*/, 0 /* c_mux_type*/, 1 /* c_qce_joined*/, 0 /* c_qualify_we*/, 1 /* c_read_mif*/, 0 /* c_reg_a_d_inputs*/, 0 /* c_reg_dpra_input*/, 0 /* c_sync_enable*/, 8 /* c_width*/ ) BU657( .A(BU657_A), .CLK(BU657_CLK), .QSPO_CE(BU657_QSPO_CE), .QSPO(BU657_QSPO) ); wire BU781_CLK; assign BU781_CLK = n109; wire BU781_SDIN; assign BU781_SDIN = n40; wire [1 : 0] BU781_Q; assign n111 = BU781_Q[0]; assign n1684 = BU781_Q[1]; wire BU781_CE; assign BU781_CE = n110; C_SHIFT_FD_V7_0 #( "00" /* c_ainit_val*/, 0 /* c_enable_rlocs*/, 5 /* c_fill_data*/, 0 /* c_has_aclr*/, 0 /* c_has_ainit*/, 0 /* c_has_aset*/, 1 /* c_has_ce*/, 0 /* c_has_d*/, 0 /* c_has_lsb_2_msb*/, 1 /* c_has_q*/, 0 /* c_has_sclr*/, 1 /* c_has_sdin*/, 0 /* c_has_sdout*/, 0 /* c_has_sinit*/, 0 /* c_has_sset*/, 1 /* c_shift_type*/, "00" /* c_sinit_val*/, 0 /* c_sync_enable*/, 0 /* c_sync_priority*/, 2 /* c_width*/ ) BU781( .CLK(BU781_CLK), .SDIN(BU781_SDIN), .Q(BU781_Q), .CE(BU781_CE) ); defparam BU788.INIT = 'h8888; wire BU788_I0; assign BU788_I0 = n110; wire BU788_I1; assign BU788_I1 = n1684; wire BU788_I2; assign BU788_I2 = 1'b0; wire BU788_I3; assign BU788_I3 = 1'b0; wire BU788_O; assign n1648 = BU788_O; LUT4 BU788( .I0(BU788_I0), .I1(BU788_I1), .I2(BU788_I2), .I3(BU788_I3), .O(BU788_O) ); //synopsys translate_on endmodule