module adc_driver(clk,adc_cs_b,adc_clk,adc_data0,adc_data1,v0,v1,rdy);

   input clk;
   output adc_cs_b,adc_clk;
   input adc_data0;
   input adc_data1;
   output [11:0] v0,v1;		// ADC results - voltages
   output 	 rdy;		// high for one clk cycle on conversion finish
   
   // drive the digilent ADC board, doing continuous conversions
   // rdy goes high for one clk cycle for each new conversion
   //
   // we use a counter to clock out the bits
   // note that the ADCS7476 serial data is valid on falling edges
   // of the adc clock.  

   reg [6:0] 	count;
   wire 	adc_cs_b = count<32 ? 0 : 1;
   wire 	adc_clk = count[0];
   wire 	rdy = count==32 ? 1 : 0;
   reg [11:0] 	tmp0, tmp1;
   reg [11:0] 	v0,v1;
   reg [31:0] 	delay;
   
   always @(posedge clk)
     begin
	delay <= (delay == 2) ? 0 : delay + 1;
	if(delay==0) begin
	   count <= count==46 ? 0 : count + 1;
	   tmp0 <= (~adc_clk|adc_cs_b) ? tmp0 : {tmp0[10:0],adc_data0};
	   tmp1 <= (~adc_clk|adc_cs_b) ? tmp1 : {tmp1[10:0],adc_data1};
	   v0 <= rdy ? tmp0 : v0;
	   v1 <= rdy ? tmp1 : v1;
	end
     end

endmodule // adc_driver