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// The synopsys directives "translate_off/translate_on" specified below are
// supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).

// You must compile the wrapper file fft_256pt_8bit.v when simulating
// the core, fft_256pt_8bit. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".

`timescale 1ns/1ps

module fft_256pt_8bit(
	xn_re,
	xn_im,
	start,
	fwd_inv,
	fwd_inv_we,
	scale_sch,
	scale_sch_we,
	ce,
	clk,
	xk_re,
	xk_im,
	xn_index,
	xk_index,
	rfd,
	busy,
	dv,
	edone,
	done);


input [7 : 0] xn_re;
input [7 : 0] xn_im;
input start;
input fwd_inv;
input fwd_inv_we;
input [7 : 0] scale_sch;
input scale_sch_we;
input ce;
input clk;
output [7 : 0] xk_re;
output [7 : 0] xk_im;
output [7 : 0] xn_index;
output [7 : 0] xk_index;
output rfd;
output busy;
output dv;
output edone;
output done;

// synopsys translate_off

      XFFT_V3_1 #(
		3,	// c_arch
		1,	// c_bram_stages
		1,	// c_data_mem_type
		0,	// c_enable_rlocs
		"spartan3",	// c_family
		0,	// c_has_bfp
		1,	// c_has_bypass
		1,	// c_has_ce
		1,	// c_has_natural_output
		0,	// c_has_nfft
		0,	// c_has_ovflo
		0,	// c_has_rounding
		1,	// c_has_scaling
		0,	// c_has_sclr
		8,	// c_input_width
		8,	// c_nfft_max
		0,	// c_optimize
		8,	// c_output_width
		1,	// c_twiddle_mem_type
		8)	// c_twiddle_width
	inst (
		.XN_RE(xn_re),
		.XN_IM(xn_im),
		.START(start),
		.FWD_INV(fwd_inv),
		.FWD_INV_WE(fwd_inv_we),
		.SCALE_SCH(scale_sch),
		.SCALE_SCH_WE(scale_sch_we),
		.CE(ce),
		.CLK(clk),
		.XK_RE(xk_re),
		.XK_IM(xk_im),
		.XN_INDEX(xn_index),
		.XK_INDEX(xk_index),
		.RFD(rfd),
		.BUSY(busy),
		.DV(dv),
		.EDONE(edone),
		.DONE(done),
		.UNLOAD(),
		.NFFT(),
		.NFFT_WE(),
		.SCLR(),
		.BLK_EXP(),
		.OVFLO());


// synopsys translate_on

// FPGA Express black box declaration
// synopsys attribute fpga_dont_touch "true"
// synthesis attribute fpga_dont_touch of fft_256pt_8bit is "true"

// XST black box declaration
// box_type "black_box"
// synthesis attribute box_type of fft_256pt_8bit is "black_box"

endmodule