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Use in such applications are * * expressly prohibited. * * * * (c) Copyright 1995-2004 Xilinx, Inc. * * All rights reserved. * *******************************************************************************/ /* Behavioural components instantiated: C_SHIFT_RAM_V7_0 C_SHIFT_FD_V7_0 MULT_GEN_V7_0 C_TWOS_COMP_V7_0 C_GATE_BIT_V7_0 C_COMPARE_V7_0 C_ADDSUB_V7_0 C_REG_FD_V7_0 BLKMEMDP_V6_0 */ `timescale 1ns/1ps module dds_20bit( DATA, WE, A, CLK, CE, RDY, SINE, COSINE ); // synthesis black_box input [31 : 0] DATA; input WE; input [4 : 0] A; input CLK; input CE; output RDY; output [19 : 0] SINE; output [19 : 0] COSINE; //synopsys translate_off wire n0 = 1'b0; wire n1 = 1'b1; wire n2; wire n3; wire n4; wire n5; wire n6; wire n7; wire n8; wire n19; wire n20; wire n21; wire n22; wire n23; wire n24; wire n25; wire n26; wire n27; wire n28; wire n29; wire n30; wire n31; wire n32; wire n33; wire n34; wire n35; wire n36; wire n37; wire n38; wire n39; wire n40; wire n41; wire n42; wire n43; wire n44; wire n45; wire n46; wire n47; wire n48; wire n49; wire n50; wire n63; wire n64; wire n65; wire n66; wire n67; wire n68; wire n69; wire n70; wire n71; wire n72; wire n73; wire n74; wire n75; wire n76; wire n77; wire n78; wire n79; wire n80; wire n81; wire n82; wire n83; wire n84; wire n85; wire n86; wire n87; wire n88; wire n89; wire n90; wire n91; wire n92; wire n93; wire n94; wire n95; wire n96; wire n97; wire n98; wire n99; wire n132; wire n133; wire n134; wire n135; wire n136; wire n137; wire n138; wire n139; wire n174; wire n175; wire n176; wire n177; wire n178; wire n179; wire n180; wire n181; wire n182; wire n183; wire n184; wire n185; wire n186; wire n187; wire n188; wire n189; wire n190; wire n191; wire n192; wire n193; wire n194; wire n195; wire n196; wire n197; wire n198; wire n199; wire n200; wire n201; wire n202; wire n203; wire n204; wire n205; wire n206; wire n207; wire n208; wire n209; wire n210; wire n211; wire n212; wire n213; wire n214; wire n215; wire n216; wire n217; wire n218; wire n219; wire n220; wire n221; wire n222; wire n223; wire n224; wire n225; wire n226; wire n227; wire n228; wire n229; wire n230; wire n231; wire n232; wire n233; wire n234; wire n235; wire n236; wire n237; wire n238; wire n239; wire n240; wire n241; wire n242; wire n243; wire n244; wire n245; wire n246; wire n247; wire n248; wire n249; wire n250; wire n251; wire n252; wire n253; wire n254; wire n255; wire n256; wire n257; wire n258; wire n259; wire n260; wire n261; wire n262; wire n263; wire n264; wire n265; wire n266; wire n267; wire n268; wire n269; wire n270; wire n271; wire n272; wire n273; wire n274; wire n275; wire n276; wire n277; wire n278; wire n279; wire n280; wire n281; wire n282; wire n283; wire n284; wire n285; wire n286; wire n287; wire n288; wire n289; wire n290; wire n291; wire n292; wire n293; wire n294; wire n295; wire n296; wire n297; wire n298; wire n299; wire n300; wire n301; wire n302; wire n303; wire n304; wire n305; wire n306; wire n307; wire n308; wire n309; wire n310; wire n311; wire n312; wire n313; wire n314; wire n315; wire n316; wire n317; wire n318; wire n319; wire n320; wire n321; wire n322; wire n323; wire n324; wire n325; wire n326; wire n327; wire n328; wire n329; wire n330; wire n331; wire n385; wire n386; wire n387; wire n388; wire n389; wire n390; wire n391; wire n392; wire n393; wire n394; wire n395; wire n396; wire n397; wire n398; wire n399; wire n400; wire n401; wire n402; wire n455; wire n456; wire n457; wire n458; wire n459; wire n460; wire n461; wire n462; wire n463; wire n464; wire n465; wire n466; wire n467; wire n468; wire n469; wire n470; wire n471; wire n472; wire n508; wire n509; wire n510; wire n511; wire n512; wire n513; wire n514; wire n515; wire n516; wire n517; wire n518; wire n519; wire n520; wire n521; wire n522; wire n523; wire n524; wire n525; wire n526; wire n527; wire n528; wire n529; wire n530; wire n531; wire n532; wire n533; wire n534; wire n535; wire n536; wire n537; wire n538; wire n539; wire n540; wire n541; wire n542; wire n543; wire n544; wire n545; wire n546; wire n547; wire n548; wire n549; wire n550; wire n551; wire n552; wire n553; wire n554; wire n555; wire n556; wire n557; wire n558; wire n559; wire n560; wire n561; wire n562; wire n563; wire n564; wire n565; wire n566; wire n567; wire n568; wire n569; wire n570; wire n571; wire n572; wire n573; wire n574; wire n575; wire n576; wire n577; wire n578; wire n579; wire n580; wire n581; wire n582; wire n583; wire n584; wire n585; wire n586; wire n587; wire n588; wire n589; wire n590; wire n591; wire n592; wire n593; wire n594; wire n595; wire n596; wire n597; wire n598; wire n599; wire n600; wire n601; wire n602; wire n603; wire n604; wire n605; wire n606; wire n607; wire n608; wire n609; wire n610; wire n611; wire n612; wire n613; wire n614; wire n615; wire n616; wire n617; wire n618; wire n619; wire n620; wire n621; wire n622; wire n623; wire n624; wire n625; wire n626; wire n627; wire n628; wire n629; wire n630; wire n631; wire n632; wire n633; wire n634; wire n635; wire n636; wire n637; wire n638; wire n639; wire n640; wire n641; wire n642; wire n643; wire n644; wire n645; wire n646; wire n647; wire n648; wire n649; wire n650; wire n651; wire n652; wire n659; wire n660; wire n661; wire n662; wire n663; wire n664; wire n665; wire n666; wire n667; wire n668; wire n669; wire n670; wire n671; wire n672; wire n673; wire n674; wire n675; wire n676; wire n677; wire n678; wire n679; wire n680; wire n681; wire n682; wire n683; wire n684; wire n685; wire n686; wire n687; wire n688; wire n689; wire n690; wire n691; wire n692; wire n693; wire n694; wire n695; wire n696; wire n697; wire n698; wire n699; wire n700; wire n701; wire n758; wire n759; wire n760; wire n761; wire n762; wire n763; wire n764; wire n765; wire n766; wire n767; wire n768; wire n769; wire n770; wire n771; wire n772; wire n773; wire n774; wire n775; wire n776; wire n777; wire n778; wire n779; wire n780; wire n781; wire n782; wire n783; wire n784; wire n785; wire n786; wire n787; wire n788; wire n789; wire n1472; wire n1473; wire n1474; wire n1475; wire n1476; wire n1477; wire n1478; wire n1479; wire n1480; wire n1481; wire n1482; wire n1483; wire n1484; wire n1485; wire n1506; wire n1507; wire n1508; wire n1509; wire n1510; wire n1511; wire n1512; wire n1513; wire n1514; wire n1515; wire n1519; wire n1520; wire n1521; wire n1522; wire n1523; wire n1524; wire n1525; wire n1526; wire n1527; wire n1528; wire n1529; wire n1530; wire n1531; wire n1532; wire n1533; wire n1534; wire n1535; wire n1536; wire n1537; wire n1538; wire n1539; wire n1540; wire n1559; wire n1560; wire n1561; wire n1562; wire n1563; wire n1564; wire n1565; wire n1566; wire n1567; wire n1568; wire n1569; wire n1570; wire n1571; wire n1572; wire n1593; wire n1594; wire n1595; wire n1596; wire n1597; wire n1598; wire n1599; wire n1600; wire n1601; wire n1602; wire n1606; wire n1607; wire n1608; wire n1609; wire n1610; wire n1611; wire n1612; wire n1613; wire n1614; wire n1615; wire n1616; wire n1617; wire n1618; wire n1619; wire n1620; wire n1621; wire n1622; wire n1623; wire n1624; wire n1625; wire n1626; wire n1627; wire n1646; wire n1672; wire n1926; wire n1945; wire n1963; wire n2213; wire n2232; wire n2250; wire n6385; wire n6386; wire n6387; wire n6388; wire n6389; wire n6390; wire n6391; wire n6392; wire n6393; wire n6394; wire n6395; wire n6396; wire n6397; wire n6398; wire n6399; wire n6400; wire n6401; wire n6402; wire n6403; wire n6404; wire n6407; wire n6408; wire n6409; wire n6410; wire n6411; wire n6412; wire n6413; wire n6414; wire n6415; wire n6416; wire n6417; wire n6418; wire n6419; wire n6420; wire n6421; wire n6422; wire n6423; wire n6424; wire n6425; wire n6426; wire n6428; wire n6445; wire n6460; wire n6461; wire n6462; wire n6463; wire n6464; wire n6465; wire n6467; wire n7171; wire n7172; wire n7173; wire n7174; wire n7175; wire n7176; wire n7177; wire n7178; wire n7179; wire n7180; wire n7181; wire n7182; wire n7183; wire n7184; wire n7185; wire n7186; wire n7187; wire n7188; wire n7189; wire n7190; wire n7193; wire n7194; wire n7195; wire n7196; wire n7197; wire n7198; wire n7199; wire n7200; wire n7201; wire n7202; wire n7203; wire n7204; wire n7205; wire n7206; wire n7207; wire n7208; wire n7209; wire n7210; wire n7211; wire n7212; wire n7214; wire n7231; wire n7246; wire n7247; wire n7248; wire n7249; wire n7250; wire n7251; wire n7253; assign n621 = DATA[0]; assign n622 = DATA[1]; assign n623 = DATA[2]; assign n624 = DATA[3]; assign n625 = DATA[4]; assign n626 = DATA[5]; assign n627 = DATA[6]; assign n628 = DATA[7]; assign n629 = DATA[8]; assign n630 = DATA[9]; assign n631 = DATA[10]; assign n632 = DATA[11]; assign n633 = DATA[12]; assign n634 = DATA[13]; assign n635 = DATA[14]; assign n636 = DATA[15]; assign n637 = DATA[16]; assign n638 = DATA[17]; assign n639 = DATA[18]; assign n640 = DATA[19]; assign n641 = DATA[20]; assign n642 = DATA[21]; assign n643 = DATA[22]; assign n644 = DATA[23]; assign n645 = DATA[24]; assign n646 = DATA[25]; assign n647 = DATA[26]; assign n648 = DATA[27]; assign n649 = DATA[28]; assign n650 = DATA[29]; assign n651 = DATA[30]; assign n652 = DATA[31]; assign n8 = WE; assign n3 = A[0]; assign n4 = A[1]; assign n5 = A[2]; assign n6 = A[3]; assign n7 = A[4]; assign n659 = CLK; assign n660 = CE; assign RDY = n661; assign SINE[0] = n662; assign SINE[1] = n663; assign SINE[2] = n664; assign SINE[3] = n665; assign SINE[4] = n666; assign SINE[5] = n667; assign SINE[6] = n668; assign SINE[7] = n669; assign SINE[8] = n670; assign SINE[9] = n671; assign SINE[10] = n672; assign SINE[11] = n673; assign SINE[12] = n674; assign SINE[13] = n675; assign SINE[14] = n676; assign SINE[15] = n677; assign SINE[16] = n678; assign SINE[17] = n679; assign SINE[18] = n680; assign SINE[19] = n681; assign COSINE[0] = n682; assign COSINE[1] = n683; assign COSINE[2] = n684; assign COSINE[3] = n685; assign COSINE[4] = n686; assign COSINE[5] = n687; assign COSINE[6] = n688; assign COSINE[7] = n689; assign COSINE[8] = n690; assign COSINE[9] = n691; assign COSINE[10] = n692; assign COSINE[11] = n693; assign COSINE[12] = n694; assign COSINE[13] = n695; assign COSINE[14] = n696; assign COSINE[15] = n697; assign COSINE[16] = n698; assign COSINE[17] = n699; assign COSINE[18] = n700; assign COSINE[19] = n701; wire [5 : 0] BU2_I; assign BU2_I[0] = n3; assign BU2_I[1] = n4; assign BU2_I[2] = n5; assign BU2_I[3] = n6; assign BU2_I[4] = n7; assign BU2_I[5] = n8; wire BU2_T; assign BU2_T = 1'b0; wire BU2_EN; assign BU2_EN = 1'b0; wire BU2_Q; wire BU2_CLK; assign BU2_CLK = 1'b0; wire BU2_CE; assign BU2_CE = 1'b0; wire BU2_ACLR; assign BU2_ACLR = 1'b0; wire BU2_ASET; assign BU2_ASET = 1'b0; wire BU2_AINIT; assign BU2_AINIT = 1'b0; wire BU2_SCLR; assign BU2_SCLR = 1'b0; wire BU2_SSET; assign BU2_SSET = 1'b0; wire BU2_SINIT; assign BU2_SINIT = 1'b0; wire BU2_O; assign n2 = BU2_O; C_GATE_BIT_V7_0 #( "0" /* c_ainit_val*/, 0 /* c_enable_rlocs*/, 0 /* c_gate_type*/, 0 /* c_has_aclr*/, 0 /* c_has_ainit*/, 0 /* c_has_aset*/, 0 /* c_has_ce*/, 1 /* c_has_o*/, 1 /* c_has_q*/, 0 /* c_has_sclr*/, 0 /* c_has_sinit*/, 0 /* c_has_sset*/, 6 /* c_inputs*/, "011111" /* c_input_inv_mask*/, 0 /* c_pipe_stages*/, "0" /* c_sinit_val*/, 0 /* c_sync_enable*/, 1 /* c_sync_priority*/ ) BU2( .I(BU2_I), .T(BU2_T), .EN(BU2_EN), .Q(BU2_Q), .CLK(BU2_CLK), .CE(BU2_CE), .ACLR(BU2_ACLR), .ASET(BU2_ASET), .AINIT(BU2_AINIT), .SCLR(BU2_SCLR), .SSET(BU2_SSET), .SINIT(BU2_SINIT), .O(BU2_O) ); wire [31 : 0] BU12_D; assign BU12_D[0] = n621; assign BU12_D[1] = n622; assign BU12_D[2] = n623; assign BU12_D[3] = n624; assign BU12_D[4] = n625; assign BU12_D[5] = n626; assign BU12_D[6] = n627; assign BU12_D[7] = n628; assign BU12_D[8] = n629; assign BU12_D[9] = n630; assign BU12_D[10] = n631; assign BU12_D[11] = n632; assign BU12_D[12] = n633; assign BU12_D[13] = n634; assign BU12_D[14] = n635; assign BU12_D[15] = n636; assign BU12_D[16] = n637; assign BU12_D[17] = n638; assign BU12_D[18] = n639; assign BU12_D[19] = n640; assign BU12_D[20] = n641; assign BU12_D[21] = n642; assign BU12_D[22] = n643; assign BU12_D[23] = n644; assign BU12_D[24] = n645; assign BU12_D[25] = n646; assign BU12_D[26] = n647; assign BU12_D[27] = n648; assign BU12_D[28] = n649; assign BU12_D[29] = n650; assign BU12_D[30] = n651; assign BU12_D[31] = n652; wire [31 : 0] BU12_Q; assign n758 = BU12_Q[0]; assign n759 = BU12_Q[1]; assign n760 = BU12_Q[2]; assign n761 = BU12_Q[3]; assign n762 = BU12_Q[4]; assign n763 = BU12_Q[5]; assign n764 = BU12_Q[6]; assign n765 = BU12_Q[7]; assign n766 = BU12_Q[8]; assign n767 = BU12_Q[9]; assign n768 = BU12_Q[10]; assign n769 = BU12_Q[11]; assign n770 = BU12_Q[12]; assign n771 = BU12_Q[13]; assign n772 = BU12_Q[14]; assign n773 = BU12_Q[15]; assign n774 = BU12_Q[16]; assign n775 = BU12_Q[17]; assign n776 = BU12_Q[18]; assign n777 = BU12_Q[19]; assign n778 = BU12_Q[20]; assign n779 = BU12_Q[21]; assign n780 = BU12_Q[22]; assign n781 = BU12_Q[23]; assign n782 = BU12_Q[24]; assign n783 = BU12_Q[25]; assign n784 = BU12_Q[26]; assign n785 = BU12_Q[27]; assign n786 = BU12_Q[28]; assign n787 = BU12_Q[29]; assign n788 = BU12_Q[30]; assign n789 = BU12_Q[31]; wire BU12_CLK; assign BU12_CLK = n659; wire BU12_CE; assign BU12_CE = n2; C_REG_FD_V7_0 #( "00000000000000000000000000000000" /* c_ainit_val*/, 0 /* c_enable_rlocs*/, 0 /* c_has_aclr*/, 0 /* c_has_ainit*/, 0 /* c_has_aset*/, 1 /* c_has_ce*/, 0 /* c_has_sclr*/, 0 /* c_has_sinit*/, 0 /* c_has_sset*/, "00000000000000000000000000000000" /* c_sinit_val*/, 0 /* c_sync_enable*/, 0 /* c_sync_priority*/, 32 /* c_width*/ ) BU12( .D(BU12_D), .Q(BU12_Q), .CLK(BU12_CLK), .CE(BU12_CE) ); wire [31 : 0] BU78_A; assign BU78_A[0] = n19; assign BU78_A[1] = n20; assign BU78_A[2] = n21; assign BU78_A[3] = n22; assign BU78_A[4] = n23; assign BU78_A[5] = n24; assign BU78_A[6] = n25; assign BU78_A[7] = n26; assign BU78_A[8] = n27; assign BU78_A[9] = n28; assign BU78_A[10] = n29; assign BU78_A[11] = n30; assign BU78_A[12] = n31; assign BU78_A[13] = n32; assign BU78_A[14] = n33; assign BU78_A[15] = n34; assign BU78_A[16] = n35; assign BU78_A[17] = n36; assign BU78_A[18] = n37; assign BU78_A[19] = n38; assign BU78_A[20] = n39; assign BU78_A[21] = n40; assign BU78_A[22] = n41; assign BU78_A[23] = n42; assign BU78_A[24] = n43; assign BU78_A[25] = n44; assign BU78_A[26] = n45; assign BU78_A[27] = n46; assign BU78_A[28] = n47; assign BU78_A[29] = n48; assign BU78_A[30] = n49; assign BU78_A[31] = n50; wire [31 : 0] BU78_B; assign BU78_B[0] = n758; assign BU78_B[1] = n759; assign BU78_B[2] = n760; assign BU78_B[3] = n761; assign BU78_B[4] = n762; assign BU78_B[5] = n763; assign BU78_B[6] = n764; assign BU78_B[7] = n765; assign BU78_B[8] = n766; assign BU78_B[9] = n767; assign BU78_B[10] = n768; assign BU78_B[11] = n769; assign BU78_B[12] = n770; assign BU78_B[13] = n771; assign BU78_B[14] = n772; assign BU78_B[15] = n773; assign BU78_B[16] = n774; assign BU78_B[17] = n775; assign BU78_B[18] = n776; assign BU78_B[19] = n777; assign BU78_B[20] = n778; assign BU78_B[21] = n779; assign BU78_B[22] = n780; assign BU78_B[23] = n781; assign BU78_B[24] = n782; assign BU78_B[25] = n783; assign BU78_B[26] = n784; assign BU78_B[27] = n785; assign BU78_B[28] = n786; assign BU78_B[29] = n787; assign BU78_B[30] = n788; assign BU78_B[31] = n789; wire [31 : 0] BU78_Q; assign n19 = BU78_Q[0]; assign n20 = BU78_Q[1]; assign n21 = BU78_Q[2]; assign n22 = BU78_Q[3]; assign n23 = BU78_Q[4]; assign n24 = BU78_Q[5]; assign n25 = BU78_Q[6]; assign n26 = BU78_Q[7]; assign n27 = BU78_Q[8]; assign n28 = BU78_Q[9]; assign n29 = BU78_Q[10]; assign n30 = BU78_Q[11]; assign n31 = BU78_Q[12]; assign n32 = BU78_Q[13]; assign n33 = BU78_Q[14]; assign n34 = BU78_Q[15]; assign n35 = BU78_Q[16]; assign n36 = BU78_Q[17]; assign n37 = BU78_Q[18]; assign n38 = BU78_Q[19]; assign n39 = BU78_Q[20]; assign n40 = BU78_Q[21]; assign n41 = BU78_Q[22]; assign n42 = BU78_Q[23]; assign n43 = BU78_Q[24]; assign n44 = BU78_Q[25]; assign n45 = BU78_Q[26]; assign n46 = BU78_Q[27]; assign n47 = BU78_Q[28]; assign n48 = BU78_Q[29]; assign n49 = BU78_Q[30]; assign n50 = BU78_Q[31]; wire BU78_CLK; assign BU78_CLK = n659; wire BU78_CE; assign BU78_CE = n660; C_ADDSUB_V7_0 #( 0 /* c_add_mode*/, "00000000000000000000000000000000" /* c_ainit_val*/, 1 /* c_a_type*/, 32 /* c_a_width*/, 1 /* c_bypass_enable*/, 0 /* c_bypass_low*/, 0 /* c_b_constant*/, 1 /* c_b_type*/, "00000000000000000000000000000000" /* c_b_value*/, 32 /* c_b_width*/, 0 /* c_enable_rlocs*/, 0 /* c_has_aclr*/, 0 /* c_has_add*/, 0 /* c_has_ainit*/, 0 /* c_has_aset*/, 0 /* c_has_a_signed*/, 0 /* c_has_bypass*/, 0 /* c_has_bypass_with_cin*/, 0 /* c_has_b_in*/, 0 /* c_has_b_out*/, 0 /* c_has_b_signed*/, 1 /* c_has_ce*/, 0 /* c_has_c_in*/, 0 /* c_has_c_out*/, 0 /* c_has_ovfl*/, 1 /* c_has_q*/, 0 /* c_has_q_b_out*/, 0 /* c_has_q_c_out*/, 0 /* c_has_q_ovfl*/, 1 /* c_has_s*/, 0 /* c_has_sclr*/, 0 /* c_has_sinit*/, 0 /* c_has_sset*/, 31 /* c_high_bit*/, 1 /* c_latency*/, 0 /* c_low_bit*/, 32 /* c_out_width*/, 0 /* c_pipe_stages*/, "00000000000000000000000000000000" /* c_sinit_val*/, 0 /* c_sync_enable*/, 0 /* c_sync_priority*/ ) BU78( .A(BU78_A), .B(BU78_B), .Q(BU78_Q), .CLK(BU78_CLK), .CE(BU78_CE) ); wire [11 : 0] BU353_D; assign BU353_D[0] = n39; assign BU353_D[1] = n40; assign BU353_D[2] = n41; assign BU353_D[3] = n42; assign BU353_D[4] = n43; assign BU353_D[5] = n44; assign BU353_D[6] = n45; assign BU353_D[7] = n46; assign BU353_D[8] = n47; assign BU353_D[9] = n48; assign BU353_D[10] = n49; assign BU353_D[11] = n50; wire [11 : 0] BU353_Q; assign n1472 = BU353_Q[0]; assign n1473 = BU353_Q[1]; assign n1474 = BU353_Q[2]; assign n1475 = BU353_Q[3]; assign n1476 = BU353_Q[4]; assign n1477 = BU353_Q[5]; assign n1478 = BU353_Q[6]; assign n1479 = BU353_Q[7]; assign n1480 = BU353_Q[8]; assign n1481 = BU353_Q[9]; assign n1482 = BU353_Q[10]; assign n1483 = BU353_Q[11]; wire BU353_CLK; assign BU353_CLK = n659; wire BU353_CE; assign BU353_CE = n660; C_REG_FD_V7_0 #( "000000000000" /* c_ainit_val*/, 0 /* c_enable_rlocs*/, 0 /* c_has_aclr*/, 0 /* c_has_ainit*/, 0 /* c_has_aset*/, 1 /* c_has_ce*/, 0 /* c_has_sclr*/, 0 /* c_has_sinit*/, 0 /* c_has_sset*/, "000000000000" /* c_sinit_val*/, 0 /* c_sync_enable*/, 0 /* c_sync_priority*/, 12 /* c_width*/ ) BU353( .D(BU353_D), .Q(BU353_Q), .CLK(BU353_CLK), .CE(BU353_CE) ); wire [9 : 0] BU380_A; assign BU380_A[0] = n1472; assign BU380_A[1] = n1473; assign BU380_A[2] = n1474; assign BU380_A[3] = n1475; assign BU380_A[4] = n1476; assign BU380_A[5] = n1477; assign BU380_A[6] = n1478; assign BU380_A[7] = n1479; assign BU380_A[8] = n1480; assign BU380_A[9] = n1481; wire BU380_BYPASS; assign BU380_BYPASS = n1482; wire BU380_CLK; assign BU380_CLK = n659; wire [10 : 0] BU380_Q; assign n1506 = BU380_Q[0]; assign n1507 = BU380_Q[1]; assign n1508 = BU380_Q[2]; assign n1509 = BU380_Q[3]; assign n1510 = BU380_Q[4]; assign n1511 = BU380_Q[5]; assign n1512 = BU380_Q[6]; assign n1513 = BU380_Q[7]; assign n1514 = BU380_Q[8]; assign n1515 = BU380_Q[9]; wire BU380_CE; assign BU380_CE = n660; C_TWOS_COMP_V7_0 #( "00000000000" /* c_ainit_val*/, 1 /* c_bypass_enable*/, 1 /* c_bypass_low*/, 0 /* c_enable_rlocs*/, 0 /* c_has_aclr*/, 0 /* c_has_ainit*/, 0 /* c_has_aset*/, 1 /* c_has_bypass*/, 1 /* c_has_ce*/, 1 /* c_has_q*/, 0 /* c_has_s*/, 0 /* c_has_sclr*/, 0 /* c_has_sinit*/, 0 /* c_has_sset*/, 0 /* c_pipe_stages*/, "00000000000" /* c_sinit_val*/, 0 /* c_sync_enable*/, 0 /* c_sync_priority*/, 10 /* c_width*/ ) BU380( .A(BU380_A), .BYPASS(BU380_BYPASS), .CLK(BU380_CLK), .Q(BU380_Q), .CE(BU380_CE) ); wire BU459_CLK; assign BU459_CLK = n659; wire [0 : 0] BU459_D; assign BU459_D[0] = n1483; wire [0 : 0] BU459_Q; assign n1484 = BU459_Q[0]; wire BU459_CE; assign BU459_CE = n660; C_SHIFT_RAM_V7_0 #( 1 /* c_addr_width*/, "0" /* c_ainit_val*/, "0" /* c_default_data*/, 2 /* c_default_data_radix*/, 2 /* c_depth*/, 0 /* c_enable_rlocs*/, 0 /* c_generate_mif*/, 0 /* c_has_a*/, 0 /* c_has_aclr*/, 0 /* c_has_ainit*/, 0 /* c_has_aset*/, 1 /* c_has_ce*/, 0 /* c_has_sclr*/, 0 /* c_has_sinit*/, 0 /* c_has_sset*/, "null" /* c_mem_init_file*/, 2 /* c_mem_init_radix*/, 0 /* c_read_mif*/, 1 /* c_reg_last_bit*/, 0 /* c_shift_type*/, "0" /* c_sinit_val*/, 0 /* c_sync_enable*/, 0 /* c_sync_priority*/, 1 /* c_width*/ ) BU459( .CLK(BU459_CLK), .D(BU459_D), .Q(BU459_Q), .CE(BU459_CE) ); wire BU467_CLK; assign BU467_CLK = n659; wire [0 : 0] BU467_D; assign BU467_D[0] = n1482; wire [0 : 0] BU467_Q; assign n1485 = BU467_Q[0]; wire BU467_CE; assign BU467_CE = n660; C_SHIFT_RAM_V7_0 #( 1 /* c_addr_width*/, "0" /* c_ainit_val*/, "0" /* c_default_data*/, 2 /* c_default_data_radix*/, 2 /* c_depth*/, 0 /* c_enable_rlocs*/, 0 /* c_generate_mif*/, 0 /* c_has_a*/, 0 /* c_has_aclr*/, 0 /* c_has_ainit*/, 0 /* c_has_aset*/, 1 /* c_has_ce*/, 0 /* c_has_sclr*/, 0 /* c_has_sinit*/, 0 /* c_has_sset*/, "null" /* c_mem_init_file*/, 2 /* c_mem_init_radix*/, 0 /* c_read_mif*/, 1 /* c_reg_last_bit*/, 0 /* c_shift_type*/, "0" /* c_sinit_val*/, 0 /* c_sync_enable*/, 0 /* c_sync_priority*/, 1 /* c_width*/ ) BU467( .CLK(BU467_CLK), .D(BU467_D), .Q(BU467_Q), .CE(BU467_CE) ); defparam BU478.INIT = 'h6a6a; wire BU478_I0; assign BU478_I0 = n1484; wire BU478_I1; assign BU478_I1 = n1485; wire BU478_I2; assign BU478_I2 = n1520; wire BU478_I3; assign BU478_I3 = 1'b0; wire BU478_O; assign n1926 = BU478_O; LUT4 BU478( .I0(BU478_I0), .I1(BU478_I1), .I2(BU478_I2), .I3(BU478_I3), .O(BU478_O) ); wire BU479_D; assign BU479_D = n1926; wire BU479_C; assign BU479_C = n659; wire BU479_CE; assign BU479_CE = n660; wire BU479_PRE; assign BU479_PRE = 1'b0; wire BU479_Q; assign n1522 = BU479_Q; FDPE BU479( .D(BU479_D), .C(BU479_C), .CE(BU479_CE), .PRE(BU479_PRE), .Q(BU479_Q) ); defparam BU483.INIT = 'h0015; wire BU483_I0; assign BU483_I0 = n1484; wire BU483_I1; assign BU483_I1 = n1485; wire BU483_I2; assign BU483_I2 = n1520; wire BU483_I3; assign BU483_I3 = n1521; wire BU483_O; assign n1945 = BU483_O; LUT4 BU483( .I0(BU483_I0), .I1(BU483_I1), .I2(BU483_I2), .I3(BU483_I3), .O(BU483_O) ); wire BU484_D; assign BU484_D = n1945; wire BU484_C; assign BU484_C = n659; wire BU484_CE; assign BU484_CE = n660; wire BU484_Q; assign n1523 = BU484_Q; FDE BU484( .D(BU484_D), .C(BU484_C), .CE(BU484_CE), .Q(BU484_Q) ); defparam BU488.INIT = 'hc0c0; wire BU488_I0; assign BU488_I0 = 1'b0; wire BU488_I1; assign BU488_I1 = n1485; wire BU488_I2; assign BU488_I2 = n1520; wire BU488_I3; assign BU488_I3 = 1'b0; wire BU488_O; assign n1963 = BU488_O; LUT4 BU488( .I0(BU488_I0), .I1(BU488_I1), .I2(BU488_I2), .I3(BU488_I3), .O(BU488_O) ); wire BU489_D; assign BU489_D = n1963; wire BU489_C; assign BU489_C = n659; wire BU489_CE; assign BU489_CE = n660; wire BU489_Q; assign n1519 = BU489_Q; FDE BU489( .D(BU489_D), .C(BU489_C), .CE(BU489_CE), .Q(BU489_Q) ); wire [9 : 0] BU491_A; assign BU491_A[0] = n1506; assign BU491_A[1] = n1507; assign BU491_A[2] = n1508; assign BU491_A[3] = n1509; assign BU491_A[4] = n1510; assign BU491_A[5] = n1511; assign BU491_A[6] = n1512; assign BU491_A[7] = n1513; assign BU491_A[8] = n1514; assign BU491_A[9] = n1515; wire BU491_CLK; assign BU491_CLK = n659; wire BU491_CE; assign BU491_CE = n660; wire BU491_ACLR; assign BU491_ACLR = 1'b0; wire BU491_QA_GE_B; assign n1521 = BU491_QA_GE_B; C_COMPARE_V7_0 #( "0" /* c_ainit_val*/, 1 /* c_b_constant*/, "1111111111" /* c_b_value*/, 1 /* c_data_type*/, 0 /* c_enable_rlocs*/, 1 /* c_has_aclr*/, 0 /* c_has_aset*/, 0 /* c_has_a_eq_b*/, 0 /* c_has_a_ge_b*/, 0 /* c_has_a_gt_b*/, 0 /* c_has_a_le_b*/, 0 /* c_has_a_lt_b*/, 0 /* c_has_a_ne_b*/, 1 /* c_has_ce*/, 0 /* c_has_qa_eq_b*/, 1 /* c_has_qa_ge_b*/, 0 /* c_has_qa_gt_b*/, 0 /* c_has_qa_le_b*/, 0 /* c_has_qa_lt_b*/, 0 /* c_has_qa_ne_b*/, 0 /* c_has_sclr*/, 0 /* c_has_sset*/, 0 /* c_pipe_stages*/, 0 /* c_sync_enable*/, 0 /* c_sync_priority*/, 10 /* c_width*/ ) BU491( .A(BU491_A), .CLK(BU491_CLK), .CE(BU491_CE), .ACLR(BU491_ACLR), .QA_GE_B(BU491_QA_GE_B) ); wire [9 : 0] BU527_A; assign BU527_A[0] = n1506; assign BU527_A[1] = n1507; assign BU527_A[2] = n1508; assign BU527_A[3] = n1509; assign BU527_A[4] = n1510; assign BU527_A[5] = n1511; assign BU527_A[6] = n1512; assign BU527_A[7] = n1513; assign BU527_A[8] = n1514; assign BU527_A[9] = n1515; wire BU527_CLK; assign BU527_CLK = n659; wire BU527_CE; assign BU527_CE = n660; wire BU527_ACLR; assign BU527_ACLR = 1'b0; wire BU527_QA_EQ_B; assign n1520 = BU527_QA_EQ_B; C_COMPARE_V7_0 #( "0" /* c_ainit_val*/, 1 /* c_b_constant*/, "0000000000" /* c_b_value*/, 1 /* c_data_type*/, 0 /* c_enable_rlocs*/, 1 /* c_has_aclr*/, 0 /* c_has_aset*/, 0 /* c_has_a_eq_b*/, 0 /* c_has_a_ge_b*/, 0 /* c_has_a_gt_b*/, 0 /* c_has_a_le_b*/, 0 /* c_has_a_lt_b*/, 0 /* c_has_a_ne_b*/, 1 /* c_has_ce*/, 1 /* c_has_qa_eq_b*/, 0 /* c_has_qa_ge_b*/, 0 /* c_has_qa_gt_b*/, 0 /* c_has_qa_le_b*/, 0 /* c_has_qa_lt_b*/, 0 /* c_has_qa_ne_b*/, 0 /* c_has_sclr*/, 0 /* c_has_sset*/, 0 /* c_pipe_stages*/, 0 /* c_sync_enable*/, 0 /* c_sync_priority*/, 10 /* c_width*/ ) BU527( .A(BU527_A), .CLK(BU527_CLK), .CE(BU527_CE), .ACLR(BU527_ACLR), .QA_EQ_B(BU527_QA_EQ_B) ); wire [11 : 0] BU543_D; assign BU543_D[0] = n39; assign BU543_D[1] = n40; assign BU543_D[2] = n41; assign BU543_D[3] = n42; assign BU543_D[4] = n43; assign BU543_D[5] = n44; assign BU543_D[6] = n45; assign BU543_D[7] = n46; assign BU543_D[8] = n47; assign BU543_D[9] = n48; assign BU543_D[10] = n49; assign BU543_D[11] = n50; wire [11 : 0] BU543_Q; assign n1559 = BU543_Q[0]; assign n1560 = BU543_Q[1]; assign n1561 = BU543_Q[2]; assign n1562 = BU543_Q[3]; assign n1563 = BU543_Q[4]; assign n1564 = BU543_Q[5]; assign n1565 = BU543_Q[6]; assign n1566 = BU543_Q[7]; assign n1567 = BU543_Q[8]; assign n1568 = BU543_Q[9]; assign n1569 = BU543_Q[10]; assign n1570 = BU543_Q[11]; wire BU543_CLK; assign BU543_CLK = n659; wire BU543_CE; assign BU543_CE = n660; C_REG_FD_V7_0 #( "000000000000" /* c_ainit_val*/, 0 /* c_enable_rlocs*/, 0 /* c_has_aclr*/, 0 /* c_has_ainit*/, 0 /* c_has_aset*/, 1 /* c_has_ce*/, 0 /* c_has_sclr*/, 0 /* c_has_sinit*/, 0 /* c_has_sset*/, "000000000000" /* c_sinit_val*/, 0 /* c_sync_enable*/, 0 /* c_sync_priority*/, 12 /* c_width*/ ) BU543( .D(BU543_D), .Q(BU543_Q), .CLK(BU543_CLK), .CE(BU543_CE) ); wire [9 : 0] BU570_A; assign BU570_A[0] = n1559; assign BU570_A[1] = n1560; assign BU570_A[2] = n1561; assign BU570_A[3] = n1562; assign BU570_A[4] = n1563; assign BU570_A[5] = n1564; assign BU570_A[6] = n1565; assign BU570_A[7] = n1566; assign BU570_A[8] = n1567; assign BU570_A[9] = n1568; wire BU570_BYPASS; assign BU570_BYPASS = n1569; wire BU570_CLK; assign BU570_CLK = n659; wire [10 : 0] BU570_Q; assign n1593 = BU570_Q[0]; assign n1594 = BU570_Q[1]; assign n1595 = BU570_Q[2]; assign n1596 = BU570_Q[3]; assign n1597 = BU570_Q[4]; assign n1598 = BU570_Q[5]; assign n1599 = BU570_Q[6]; assign n1600 = BU570_Q[7]; assign n1601 = BU570_Q[8]; assign n1602 = BU570_Q[9]; wire BU570_CE; assign BU570_CE = n660; C_TWOS_COMP_V7_0 #( "00000000000" /* c_ainit_val*/, 1 /* c_bypass_enable*/, 0 /* c_bypass_low*/, 0 /* c_enable_rlocs*/, 0 /* c_has_aclr*/, 0 /* c_has_ainit*/, 0 /* c_has_aset*/, 1 /* c_has_bypass*/, 1 /* c_has_ce*/, 1 /* c_has_q*/, 0 /* c_has_s*/, 0 /* c_has_sclr*/, 0 /* c_has_sinit*/, 0 /* c_has_sset*/, 0 /* c_pipe_stages*/, "00000000000" /* c_sinit_val*/, 0 /* c_sync_enable*/, 0 /* c_sync_priority*/, 10 /* c_width*/ ) BU570( .A(BU570_A), .BYPASS(BU570_BYPASS), .CLK(BU570_CLK), .Q(BU570_Q), .CE(BU570_CE) ); wire BU651_CLK; assign BU651_CLK = n659; wire [0 : 0] BU651_D; assign BU651_D[0] = n1570; wire [0 : 0] BU651_Q; assign n1571 = BU651_Q[0]; wire BU651_CE; assign BU651_CE = n660; C_SHIFT_RAM_V7_0 #( 1 /* c_addr_width*/, "0" /* c_ainit_val*/, "0" /* c_default_data*/, 2 /* c_default_data_radix*/, 2 /* c_depth*/, 0 /* c_enable_rlocs*/, 0 /* c_generate_mif*/, 0 /* c_has_a*/, 0 /* c_has_aclr*/, 0 /* c_has_ainit*/, 0 /* c_has_aset*/, 1 /* c_has_ce*/, 0 /* c_has_sclr*/, 0 /* c_has_sinit*/, 0 /* c_has_sset*/, "null" /* c_mem_init_file*/, 2 /* c_mem_init_radix*/, 0 /* c_read_mif*/, 1 /* c_reg_last_bit*/, 0 /* c_shift_type*/, "0" /* c_sinit_val*/, 0 /* c_sync_enable*/, 0 /* c_sync_priority*/, 1 /* c_width*/ ) BU651( .CLK(BU651_CLK), .D(BU651_D), .Q(BU651_Q), .CE(BU651_CE) ); wire BU659_CLK; assign BU659_CLK = n659; wire [0 : 0] BU659_D; assign BU659_D[0] = n1569; wire [0 : 0] BU659_Q; assign n1572 = BU659_Q[0]; wire BU659_CE; assign BU659_CE = n660; C_SHIFT_RAM_V7_0 #( 1 /* c_addr_width*/, "0" /* c_ainit_val*/, "0" /* c_default_data*/, 2 /* c_default_data_radix*/, 2 /* c_depth*/, 0 /* c_enable_rlocs*/, 0 /* c_generate_mif*/, 0 /* c_has_a*/, 0 /* c_has_aclr*/, 0 /* c_has_ainit*/, 0 /* c_has_aset*/, 1 /* c_has_ce*/, 0 /* c_has_sclr*/, 0 /* c_has_sinit*/, 0 /* c_has_sset*/, "null" /* c_mem_init_file*/, 2 /* c_mem_init_radix*/, 0 /* c_read_mif*/, 1 /* c_reg_last_bit*/, 0 /* c_shift_type*/, "0" /* c_sinit_val*/, 0 /* c_sync_enable*/, 0 /* c_sync_priority*/, 1 /* c_width*/ ) BU659( .CLK(BU659_CLK), .D(BU659_D), .Q(BU659_Q), .CE(BU659_CE) ); defparam BU670.INIT = 'ha9a9; wire BU670_I0; assign BU670_I0 = n1571; wire BU670_I1; assign BU670_I1 = n1572; wire BU670_I2; assign BU670_I2 = n1607; wire BU670_I3; assign BU670_I3 = 1'b0; wire BU670_O; assign n2213 = BU670_O; LUT4 BU670( .I0(BU670_I0), .I1(BU670_I1), .I2(BU670_I2), .I3(BU670_I3), .O(BU670_O) ); wire BU671_D; assign BU671_D = n2213; wire BU671_C; assign BU671_C = n659; wire BU671_CE; assign BU671_CE = n660; wire BU671_PRE; assign BU671_PRE = 1'b0; wire BU671_Q; assign n1609 = BU671_Q; FDPE BU671( .D(BU671_D), .C(BU671_C), .CE(BU671_CE), .PRE(BU671_PRE), .Q(BU671_Q) ); defparam BU675.INIT = 'h0046; wire BU675_I0; assign BU675_I0 = n1571; wire BU675_I1; assign BU675_I1 = n1572; wire BU675_I2; assign BU675_I2 = n1607; wire BU675_I3; assign BU675_I3 = n1608; wire BU675_O; assign n2232 = BU675_O; LUT4 BU675( .I0(BU675_I0), .I1(BU675_I1), .I2(BU675_I2), .I3(BU675_I3), .O(BU675_O) ); wire BU676_D; assign BU676_D = n2232; wire BU676_C; assign BU676_C = n659; wire BU676_CE; assign BU676_CE = n660; wire BU676_Q; assign n1610 = BU676_Q; FDE BU676( .D(BU676_D), .C(BU676_C), .CE(BU676_CE), .Q(BU676_Q) ); defparam BU680.INIT = 'h3030; wire BU680_I0; assign BU680_I0 = 1'b0; wire BU680_I1; assign BU680_I1 = n1572; wire BU680_I2; assign BU680_I2 = n1607; wire BU680_I3; assign BU680_I3 = 1'b0; wire BU680_O; assign n2250 = BU680_O; LUT4 BU680( .I0(BU680_I0), .I1(BU680_I1), .I2(BU680_I2), .I3(BU680_I3), .O(BU680_O) ); wire BU681_D; assign BU681_D = n2250; wire BU681_C; assign BU681_C = n659; wire BU681_CE; assign BU681_CE = n660; wire BU681_Q; assign n1606 = BU681_Q; FDE BU681( .D(BU681_D), .C(BU681_C), .CE(BU681_CE), .Q(BU681_Q) ); wire [9 : 0] BU683_A; assign BU683_A[0] = n1593; assign BU683_A[1] = n1594; assign BU683_A[2] = n1595; assign BU683_A[3] = n1596; assign BU683_A[4] = n1597; assign BU683_A[5] = n1598; assign BU683_A[6] = n1599; assign BU683_A[7] = n1600; assign BU683_A[8] = n1601; assign BU683_A[9] = n1602; wire BU683_CLK; assign BU683_CLK = n659; wire BU683_CE; assign BU683_CE = n660; wire BU683_ACLR; assign BU683_ACLR = 1'b0; wire BU683_QA_GE_B; assign n1608 = BU683_QA_GE_B; C_COMPARE_V7_0 #( "0" /* c_ainit_val*/, 1 /* c_b_constant*/, "1111111111" /* c_b_value*/, 1 /* c_data_type*/, 0 /* c_enable_rlocs*/, 1 /* c_has_aclr*/, 0 /* c_has_aset*/, 0 /* c_has_a_eq_b*/, 0 /* c_has_a_ge_b*/, 0 /* c_has_a_gt_b*/, 0 /* c_has_a_le_b*/, 0 /* c_has_a_lt_b*/, 0 /* c_has_a_ne_b*/, 1 /* c_has_ce*/, 0 /* c_has_qa_eq_b*/, 1 /* c_has_qa_ge_b*/, 0 /* c_has_qa_gt_b*/, 0 /* c_has_qa_le_b*/, 0 /* c_has_qa_lt_b*/, 0 /* c_has_qa_ne_b*/, 0 /* c_has_sclr*/, 0 /* c_has_sset*/, 0 /* c_pipe_stages*/, 0 /* c_sync_enable*/, 0 /* c_sync_priority*/, 10 /* c_width*/ ) BU683( .A(BU683_A), .CLK(BU683_CLK), .CE(BU683_CE), .ACLR(BU683_ACLR), .QA_GE_B(BU683_QA_GE_B) ); wire [9 : 0] BU719_A; assign BU719_A[0] = n1593; assign BU719_A[1] = n1594; assign BU719_A[2] = n1595; assign BU719_A[3] = n1596; assign BU719_A[4] = n1597; assign BU719_A[5] = n1598; assign BU719_A[6] = n1599; assign BU719_A[7] = n1600; assign BU719_A[8] = n1601; assign BU719_A[9] = n1602; wire BU719_CLK; assign BU719_CLK = n659; wire BU719_CE; assign BU719_CE = n660; wire BU719_ACLR; assign BU719_ACLR = 1'b0; wire BU719_QA_EQ_B; assign n1607 = BU719_QA_EQ_B; C_COMPARE_V7_0 #( "0" /* c_ainit_val*/, 1 /* c_b_constant*/, "0000000000" /* c_b_value*/, 1 /* c_data_type*/, 0 /* c_enable_rlocs*/, 1 /* c_has_aclr*/, 0 /* c_has_aset*/, 0 /* c_has_a_eq_b*/, 0 /* c_has_a_ge_b*/, 0 /* c_has_a_gt_b*/, 0 /* c_has_a_le_b*/, 0 /* c_has_a_lt_b*/, 0 /* c_has_a_ne_b*/, 1 /* c_has_ce*/, 1 /* c_has_qa_eq_b*/, 0 /* c_has_qa_ge_b*/, 0 /* c_has_qa_gt_b*/, 0 /* c_has_qa_le_b*/, 0 /* c_has_qa_lt_b*/, 0 /* c_has_qa_ne_b*/, 0 /* c_has_sclr*/, 0 /* c_has_sset*/, 0 /* c_pipe_stages*/, 0 /* c_sync_enable*/, 0 /* c_sync_priority*/, 10 /* c_width*/ ) BU719( .A(BU719_A), .CLK(BU719_CLK), .CE(BU719_CE), .ACLR(BU719_ACLR), .QA_EQ_B(BU719_QA_EQ_B) ); wire [9 : 0] BU273_addra; assign BU273_addra[9] = n1515; assign BU273_addra[8] = n1514; assign BU273_addra[7] = n1513; assign BU273_addra[6] = n1512; assign BU273_addra[5] = n1511; assign BU273_addra[4] = n1510; assign BU273_addra[3] = n1509; assign BU273_addra[2] = n1508; assign BU273_addra[1] = n1507; assign BU273_addra[0] = n1506; wire [9 : 0] BU273_addrb; assign BU273_addrb[9] = n1602; assign BU273_addrb[8] = n1601; assign BU273_addrb[7] = n1600; assign BU273_addrb[6] = n1599; assign BU273_addrb[5] = n1598; assign BU273_addrb[4] = n1597; assign BU273_addrb[3] = n1596; assign BU273_addrb[2] = n1595; assign BU273_addrb[1] = n1594; assign BU273_addrb[0] = n1593; wire BU273_clka; assign BU273_clka = n659; wire BU273_clkb; assign BU273_clkb = n659; wire [16 : 0] BU273_dina; assign BU273_dina[16] = 1'b0; assign BU273_dina[15] = 1'b0; assign BU273_dina[14] = 1'b0; assign BU273_dina[13] = 1'b0; assign BU273_dina[12] = 1'b0; assign BU273_dina[11] = 1'b0; assign BU273_dina[10] = 1'b0; assign BU273_dina[9] = 1'b0; assign BU273_dina[8] = 1'b0; assign BU273_dina[7] = 1'b0; assign BU273_dina[6] = 1'b0; assign BU273_dina[5] = 1'b0; assign BU273_dina[4] = 1'b0; assign BU273_dina[3] = 1'b0; assign BU273_dina[2] = 1'b0; assign BU273_dina[1] = 1'b0; assign BU273_dina[0] = 1'b0; wire [16 : 0] BU273_dinb; assign BU273_dinb[16] = 1'b0; assign BU273_dinb[15] = 1'b0; assign BU273_dinb[14] = 1'b0; assign BU273_dinb[13] = 1'b0; assign BU273_dinb[12] = 1'b0; assign BU273_dinb[11] = 1'b0; assign BU273_dinb[10] = 1'b0; assign BU273_dinb[9] = 1'b0; assign BU273_dinb[8] = 1'b0; assign BU273_dinb[7] = 1'b0; assign BU273_dinb[6] = 1'b0; assign BU273_dinb[5] = 1'b0; assign BU273_dinb[4] = 1'b0; assign BU273_dinb[3] = 1'b0; assign BU273_dinb[2] = 1'b0; assign BU273_dinb[1] = 1'b0; assign BU273_dinb[0] = 1'b0; wire [16 : 0] BU273_douta; assign n1540 = BU273_douta[16]; assign n1539 = BU273_douta[15]; assign n1538 = BU273_douta[14]; assign n1537 = BU273_douta[13]; assign n1536 = BU273_douta[12]; assign n1535 = BU273_douta[11]; assign n1534 = BU273_douta[10]; assign n1533 = BU273_douta[9]; assign n1532 = BU273_douta[8]; assign n1531 = BU273_douta[7]; assign n1530 = BU273_douta[6]; assign n1529 = BU273_douta[5]; assign n1528 = BU273_douta[4]; assign n1527 = BU273_douta[3]; assign n1526 = BU273_douta[2]; assign n1525 = BU273_douta[1]; assign n1524 = BU273_douta[0]; wire [16 : 0] BU273_doutb; assign n1627 = BU273_doutb[16]; assign n1626 = BU273_doutb[15]; assign n1625 = BU273_doutb[14]; assign n1624 = BU273_doutb[13]; assign n1623 = BU273_doutb[12]; assign n1622 = BU273_doutb[11]; assign n1621 = BU273_doutb[10]; assign n1620 = BU273_doutb[9]; assign n1619 = BU273_doutb[8]; assign n1618 = BU273_doutb[7]; assign n1617 = BU273_doutb[6]; assign n1616 = BU273_doutb[5]; assign n1615 = BU273_doutb[4]; assign n1614 = BU273_doutb[3]; assign n1613 = BU273_doutb[2]; assign n1612 = BU273_doutb[1]; assign n1611 = BU273_doutb[0]; wire BU273_ena; assign BU273_ena = n660; wire BU273_enb; assign BU273_enb = n660; wire BU273_nda; assign BU273_nda = 1'b0; wire BU273_ndb; assign BU273_ndb = 1'b0; wire BU273_rfda; wire BU273_rfdb; wire BU273_rdya; wire BU273_rdyb; wire BU273_sinita; assign BU273_sinita = 1'b0; wire BU273_sinitb; assign BU273_sinitb = 1'b0; wire BU273_wea; assign BU273_wea = 1'b0; wire BU273_web; assign BU273_web = 1'b0; BLKMEMDP_V6_0 #( 10 /* c_addra_width*/, 10 /* c_addrb_width*/, "0000" /* c_default_data*/, 1024 /* c_depth_a*/, 1024 /* c_depth_b*/, 0 /* c_enable_rlocs*/, 0 /* c_has_default_data*/, 0 /* c_has_dina*/, 0 /* c_has_dinb*/, 1 /* c_has_douta*/, 1 /* c_has_doutb*/, 1 /* c_has_ena*/, 1 /* c_has_enb*/, 0 /* c_has_limit_data_pitch*/, 0 /* c_has_nda*/, 0 /* c_has_ndb*/, 0 /* c_has_rdya*/, 0 /* c_has_rdyb*/, 0 /* c_has_rfda*/, 0 /* c_has_rfdb*/, 0 /* c_has_sinita*/, 0 /* c_has_sinitb*/, 0 /* c_has_wea*/, 0 /* c_has_web*/, 18 /* c_limit_data_pitch*/, "dds_20bit_SINCOS_TABLE_TRIG_ROM.mif" /* c_mem_init_file*/, 1 /* c_pipe_stages_a*/, 1 /* c_pipe_stages_b*/, 0 /* c_reg_inputsa*/, 0 /* c_reg_inputsb*/, "0000" /* c_sinita_value*/, "0000" /* c_sinitb_value*/, 17 /* c_width_a*/, 17 /* c_width_b*/, 0 /* c_write_modea*/, 0 /* c_write_modeb*/, "0" /* c_ybottom_addr*/, 1 /* c_yclka_is_rising*/, 1 /* c_yclkb_is_rising*/, 1 /* c_yena_is_high*/, 1 /* c_yenb_is_high*/, "hierarchy1" /* c_yhierarchy*/, 0 /* c_ymake_bmm*/, "4kx4" /* c_yprimitive_type*/, 1 /* c_ysinita_is_high*/, 1 /* c_ysinitb_is_high*/, "1024" /* c_ytop_addr*/, 0 /* c_yuse_single_primitive*/, 1 /* c_ywea_is_high*/, 1 /* c_yweb_is_high*/, 1 /* c_yydisable_warnings*/ ) BU273( .ADDRA(BU273_addra), .ADDRB(BU273_addrb), .CLKA(BU273_clka), .CLKB(BU273_clkb), .DINA(BU273_dina), .DINB(BU273_dinb), .DOUTA(BU273_douta), .DOUTB(BU273_doutb), .ENA(BU273_ena), .ENB(BU273_enb), .NDA(BU273_nda), .NDB(BU273_ndb), .RFDA(BU273_rfda), .RFDB(BU273_rfdb), .RDYA(BU273_rdya), .RDYB(BU273_rdyb), .SINITA(BU273_sinita), .SINITB(BU273_sinitb), .WEA(BU273_wea), .WEB(BU273_web) ); wire [17 : 0] BU735_A; assign BU735_A[0] = 1'b0; assign BU735_A[1] = 1'b0; assign BU735_A[2] = 1'b0; assign BU735_A[3] = 1'b0; assign BU735_A[4] = 1'b0; assign BU735_A[5] = 1'b0; assign BU735_A[6] = 1'b0; assign BU735_A[7] = 1'b0; assign BU735_A[8] = 1'b0; assign BU735_A[9] = 1'b0; assign BU735_A[10] = 1'b0; assign BU735_A[11] = 1'b0; assign BU735_A[12] = 1'b0; assign BU735_A[13] = 1'b0; assign BU735_A[14] = 1'b0; assign BU735_A[15] = 1'b0; assign BU735_A[16] = 1'b0; assign BU735_A[17] = 1'b0; wire [17 : 0] BU735_B; assign BU735_B[0] = n1524; assign BU735_B[1] = n1525; assign BU735_B[2] = n1526; assign BU735_B[3] = n1527; assign BU735_B[4] = n1528; assign BU735_B[5] = n1529; assign BU735_B[6] = n1530; assign BU735_B[7] = n1531; assign BU735_B[8] = n1532; assign BU735_B[9] = n1533; assign BU735_B[10] = n1534; assign BU735_B[11] = n1535; assign BU735_B[12] = n1536; assign BU735_B[13] = n1537; assign BU735_B[14] = n1538; assign BU735_B[15] = n1539; assign BU735_B[16] = n1540; assign BU735_B[17] = n1519; wire BU735_C_IN; assign BU735_C_IN = n1523; wire BU735_ADD; assign BU735_ADD = n1522; wire [17 : 0] BU735_Q; assign n81 = BU735_Q[0]; assign n82 = BU735_Q[1]; assign n83 = BU735_Q[2]; assign n84 = BU735_Q[3]; assign n85 = BU735_Q[4]; assign n86 = BU735_Q[5]; assign n87 = BU735_Q[6]; assign n88 = BU735_Q[7]; assign n89 = BU735_Q[8]; assign n90 = BU735_Q[9]; assign n91 = BU735_Q[10]; assign n92 = BU735_Q[11]; assign n93 = BU735_Q[12]; assign n94 = BU735_Q[13]; assign n95 = BU735_Q[14]; assign n96 = BU735_Q[15]; assign n97 = BU735_Q[16]; assign n98 = BU735_Q[17]; wire BU735_CLK; assign BU735_CLK = n659; wire BU735_CE; assign BU735_CE = n1646; C_ADDSUB_V7_0 #( 2 /* c_add_mode*/, "000000000000000000" /* c_ainit_val*/, 1 /* c_a_type*/, 18 /* c_a_width*/, 1 /* c_bypass_enable*/, 0 /* c_bypass_low*/, 0 /* c_b_constant*/, 1 /* c_b_type*/, "000000000000000000" /* c_b_value*/, 18 /* c_b_width*/, 0 /* c_enable_rlocs*/, 0 /* c_has_aclr*/, 1 /* c_has_add*/, 0 /* c_has_ainit*/, 0 /* c_has_aset*/, 0 /* c_has_a_signed*/, 0 /* c_has_bypass*/, 0 /* c_has_bypass_with_cin*/, 0 /* c_has_b_in*/, 0 /* c_has_b_out*/, 0 /* c_has_b_signed*/, 1 /* c_has_ce*/, 1 /* c_has_c_in*/, 0 /* c_has_c_out*/, 0 /* c_has_ovfl*/, 1 /* c_has_q*/, 0 /* c_has_q_b_out*/, 0 /* c_has_q_c_out*/, 0 /* c_has_q_ovfl*/, 1 /* c_has_s*/, 0 /* c_has_sclr*/, 0 /* c_has_sinit*/, 0 /* c_has_sset*/, 17 /* c_high_bit*/, 1 /* c_latency*/, 0 /* c_low_bit*/, 18 /* c_out_width*/, 0 /* c_pipe_stages*/, "000000000000000000" /* c_sinit_val*/, 0 /* c_sync_enable*/, 0 /* c_sync_priority*/ ) BU735( .A(BU735_A), .B(BU735_B), .C_IN(BU735_C_IN), .ADD(BU735_ADD), .Q(BU735_Q), .CLK(BU735_CLK), .CE(BU735_CE) ); wire BU844_CLK; assign BU844_CLK = n659; wire [4 : 0] BU844_Q; assign n99 = BU844_Q[0]; assign n1672 = BU844_Q[1]; wire BU844_CE; assign BU844_CE = n660; C_SHIFT_FD_V7_0 #( "00000" /* c_ainit_val*/, 0 /* c_enable_rlocs*/, 1 /* c_fill_data*/, 0 /* c_has_aclr*/, 0 /* c_has_ainit*/, 0 /* c_has_aset*/, 1 /* c_has_ce*/, 0 /* c_has_d*/, 0 /* c_has_lsb_2_msb*/, 1 /* c_has_q*/, 0 /* c_has_sclr*/, 0 /* c_has_sdin*/, 0 /* c_has_sdout*/, 0 /* c_has_sinit*/, 0 /* c_has_sset*/, 1 /* c_shift_type*/, "00000" /* c_sinit_val*/, 0 /* c_sync_enable*/, 0 /* c_sync_priority*/, 5 /* c_width*/ ) BU844( .CLK(BU844_CLK), .Q(BU844_Q), .CE(BU844_CE) ); defparam BU857.INIT = 'h8888; wire BU857_I0; assign BU857_I0 = n660; wire BU857_I1; assign BU857_I1 = n1672; wire BU857_I2; assign BU857_I2 = 1'b0; wire BU857_I3; assign BU857_I3 = 1'b0; wire BU857_O; assign n1646 = BU857_O; LUT4 BU857( .I0(BU857_I0), .I1(BU857_I1), .I2(BU857_I2), .I3(BU857_I3), .O(BU857_O) ); wire [17 : 0] BU860_A; assign BU860_A[0] = 1'b0; assign BU860_A[1] = 1'b0; assign BU860_A[2] = 1'b0; assign BU860_A[3] = 1'b0; assign BU860_A[4] = 1'b0; assign BU860_A[5] = 1'b0; assign BU860_A[6] = 1'b0; assign BU860_A[7] = 1'b0; assign BU860_A[8] = 1'b0; assign BU860_A[9] = 1'b0; assign BU860_A[10] = 1'b0; assign BU860_A[11] = 1'b0; assign BU860_A[12] = 1'b0; assign BU860_A[13] = 1'b0; assign BU860_A[14] = 1'b0; assign BU860_A[15] = 1'b0; assign BU860_A[16] = 1'b0; assign BU860_A[17] = 1'b0; wire [17 : 0] BU860_B; assign BU860_B[0] = n1611; assign BU860_B[1] = n1612; assign BU860_B[2] = n1613; assign BU860_B[3] = n1614; assign BU860_B[4] = n1615; assign BU860_B[5] = n1616; assign BU860_B[6] = n1617; assign BU860_B[7] = n1618; assign BU860_B[8] = n1619; assign BU860_B[9] = n1620; assign BU860_B[10] = n1621; assign BU860_B[11] = n1622; assign BU860_B[12] = n1623; assign BU860_B[13] = n1624; assign BU860_B[14] = n1625; assign BU860_B[15] = n1626; assign BU860_B[16] = n1627; assign BU860_B[17] = n1606; wire BU860_C_IN; assign BU860_C_IN = n1610; wire BU860_ADD; assign BU860_ADD = n1609; wire [17 : 0] BU860_Q; assign n63 = BU860_Q[0]; assign n64 = BU860_Q[1]; assign n65 = BU860_Q[2]; assign n66 = BU860_Q[3]; assign n67 = BU860_Q[4]; assign n68 = BU860_Q[5]; assign n69 = BU860_Q[6]; assign n70 = BU860_Q[7]; assign n71 = BU860_Q[8]; assign n72 = BU860_Q[9]; assign n73 = BU860_Q[10]; assign n74 = BU860_Q[11]; assign n75 = BU860_Q[12]; assign n76 = BU860_Q[13]; assign n77 = BU860_Q[14]; assign n78 = BU860_Q[15]; assign n79 = BU860_Q[16]; assign n80 = BU860_Q[17]; wire BU860_CLK; assign BU860_CLK = n659; wire BU860_CE; assign BU860_CE = n1646; C_ADDSUB_V7_0 #( 2 /* c_add_mode*/, "000000000000000000" /* c_ainit_val*/, 1 /* c_a_type*/, 18 /* c_a_width*/, 1 /* c_bypass_enable*/, 0 /* c_bypass_low*/, 0 /* c_b_constant*/, 1 /* c_b_type*/, "000000000000000000" /* c_b_value*/, 18 /* c_b_width*/, 0 /* c_enable_rlocs*/, 0 /* c_has_aclr*/, 1 /* c_has_add*/, 0 /* c_has_ainit*/, 0 /* c_has_aset*/, 0 /* c_has_a_signed*/, 0 /* c_has_bypass*/, 0 /* c_has_bypass_with_cin*/, 0 /* c_has_b_in*/, 0 /* c_has_b_out*/, 0 /* c_has_b_signed*/, 1 /* c_has_ce*/, 1 /* c_has_c_in*/, 0 /* c_has_c_out*/, 0 /* c_has_ovfl*/, 1 /* c_has_q*/, 0 /* c_has_q_b_out*/, 0 /* c_has_q_c_out*/, 0 /* c_has_q_ovfl*/, 1 /* c_has_s*/, 0 /* c_has_sclr*/, 0 /* c_has_sinit*/, 0 /* c_has_sset*/, 17 /* c_high_bit*/, 1 /* c_latency*/, 0 /* c_low_bit*/, 18 /* c_out_width*/, 0 /* c_pipe_stages*/, "000000000000000000" /* c_sinit_val*/, 0 /* c_sync_enable*/, 0 /* c_sync_priority*/ ) BU860( .A(BU860_A), .B(BU860_B), .C_IN(BU860_C_IN), .ADD(BU860_ADD), .Q(BU860_Q), .CLK(BU860_CLK), .CE(BU860_CE) ); wire [17 : 0] BU1527_D; assign BU1527_D[0] = n63; assign BU1527_D[1] = n64; assign BU1527_D[2] = n65; assign BU1527_D[3] = n66; assign BU1527_D[4] = n67; assign BU1527_D[5] = n68; assign BU1527_D[6] = n69; assign BU1527_D[7] = n70; assign BU1527_D[8] = n71; assign BU1527_D[9] = n72; assign BU1527_D[10] = n73; assign BU1527_D[11] = n74; assign BU1527_D[12] = n75; assign BU1527_D[13] = n76; assign BU1527_D[14] = n77; assign BU1527_D[15] = n78; assign BU1527_D[16] = n79; assign BU1527_D[17] = n80; wire [17 : 0] BU1527_Q; assign n226 = BU1527_Q[0]; assign n227 = BU1527_Q[1]; assign n228 = BU1527_Q[2]; assign n229 = BU1527_Q[3]; assign n230 = BU1527_Q[4]; assign n231 = BU1527_Q[5]; assign n232 = BU1527_Q[6]; assign n233 = BU1527_Q[7]; assign n234 = BU1527_Q[8]; assign n235 = BU1527_Q[9]; assign n236 = BU1527_Q[10]; assign n237 = BU1527_Q[11]; assign n238 = BU1527_Q[12]; assign n239 = BU1527_Q[13]; assign n240 = BU1527_Q[14]; assign n241 = BU1527_Q[15]; assign n242 = BU1527_Q[16]; assign n243 = BU1527_Q[17]; wire BU1527_CLK; assign BU1527_CLK = n659; wire BU1527_CE; assign BU1527_CE = n660; C_REG_FD_V7_0 #( "000000000000000000" /* c_ainit_val*/, 0 /* c_enable_rlocs*/, 0 /* c_has_aclr*/, 0 /* c_has_ainit*/, 0 /* c_has_aset*/, 1 /* c_has_ce*/, 0 /* c_has_sclr*/, 0 /* c_has_sinit*/, 0 /* c_has_sset*/, "000000000000000000" /* c_sinit_val*/, 0 /* c_sync_enable*/, 0 /* c_sync_priority*/, 18 /* c_width*/ ) BU1527( .D(BU1527_D), .Q(BU1527_Q), .CLK(BU1527_CLK), .CE(BU1527_CE) ); wire [16 : 0] BU1565_D; assign BU1565_D[0] = n174; assign BU1565_D[1] = n175; assign BU1565_D[2] = n176; assign BU1565_D[3] = n177; assign BU1565_D[4] = n178; assign BU1565_D[5] = n179; assign BU1565_D[6] = n180; assign BU1565_D[7] = n181; assign BU1565_D[8] = n182; assign BU1565_D[9] = n183; assign BU1565_D[10] = n184; assign BU1565_D[11] = n185; assign BU1565_D[12] = n186; assign BU1565_D[13] = n187; assign BU1565_D[14] = n188; assign BU1565_D[15] = n189; assign BU1565_D[16] = n190; wire [16 : 0] BU1565_Q; assign n244 = BU1565_Q[0]; assign n245 = BU1565_Q[1]; assign n246 = BU1565_Q[2]; assign n247 = BU1565_Q[3]; assign n248 = BU1565_Q[4]; assign n249 = BU1565_Q[5]; assign n250 = BU1565_Q[6]; assign n251 = BU1565_Q[7]; assign n252 = BU1565_Q[8]; assign n253 = BU1565_Q[9]; assign n254 = BU1565_Q[10]; assign n255 = BU1565_Q[11]; assign n256 = BU1565_Q[12]; assign n257 = BU1565_Q[13]; assign n258 = BU1565_Q[14]; assign n259 = BU1565_Q[15]; assign n260 = BU1565_Q[16]; wire BU1565_CLK; assign BU1565_CLK = n659; wire BU1565_CE; assign BU1565_CE = n660; C_REG_FD_V7_0 #( "00000000000000000" /* c_ainit_val*/, 0 /* c_enable_rlocs*/, 0 /* c_has_aclr*/, 0 /* c_has_ainit*/, 0 /* c_has_aset*/, 1 /* c_has_ce*/, 0 /* c_has_sclr*/, 0 /* c_has_sinit*/, 0 /* c_has_sset*/, "00000000000000000" /* c_sinit_val*/, 0 /* c_sync_enable*/, 0 /* c_sync_priority*/, 17 /* c_width*/ ) BU1565( .D(BU1565_D), .Q(BU1565_Q), .CLK(BU1565_CLK), .CE(BU1565_CE) ); wire [17 : 0] BU1728_D; assign BU1728_D[0] = n81; assign BU1728_D[1] = n82; assign BU1728_D[2] = n83; assign BU1728_D[3] = n84; assign BU1728_D[4] = n85; assign BU1728_D[5] = n86; assign BU1728_D[6] = n87; assign BU1728_D[7] = n88; assign BU1728_D[8] = n89; assign BU1728_D[9] = n90; assign BU1728_D[10] = n91; assign BU1728_D[11] = n92; assign BU1728_D[12] = n93; assign BU1728_D[13] = n94; assign BU1728_D[14] = n95; assign BU1728_D[15] = n96; assign BU1728_D[16] = n97; assign BU1728_D[17] = n98; wire [17 : 0] BU1728_Q; assign n296 = BU1728_Q[0]; assign n297 = BU1728_Q[1]; assign n298 = BU1728_Q[2]; assign n299 = BU1728_Q[3]; assign n300 = BU1728_Q[4]; assign n301 = BU1728_Q[5]; assign n302 = BU1728_Q[6]; assign n303 = BU1728_Q[7]; assign n304 = BU1728_Q[8]; assign n305 = BU1728_Q[9]; assign n306 = BU1728_Q[10]; assign n307 = BU1728_Q[11]; assign n308 = BU1728_Q[12]; assign n309 = BU1728_Q[13]; assign n310 = BU1728_Q[14]; assign n311 = BU1728_Q[15]; assign n312 = BU1728_Q[16]; assign n313 = BU1728_Q[17]; wire BU1728_CLK; assign BU1728_CLK = n659; wire BU1728_CE; assign BU1728_CE = n660; C_REG_FD_V7_0 #( "000000000000000000" /* c_ainit_val*/, 0 /* c_enable_rlocs*/, 0 /* c_has_aclr*/, 0 /* c_has_ainit*/, 0 /* c_has_aset*/, 1 /* c_has_ce*/, 0 /* c_has_sclr*/, 0 /* c_has_sinit*/, 0 /* c_has_sset*/, "000000000000000000" /* c_sinit_val*/, 0 /* c_sync_enable*/, 0 /* c_sync_priority*/, 18 /* c_width*/ ) BU1728( .D(BU1728_D), .Q(BU1728_Q), .CLK(BU1728_CLK), .CE(BU1728_CE) ); wire [16 : 0] BU1766_D; assign BU1766_D[0] = n174; assign BU1766_D[1] = n175; assign BU1766_D[2] = n176; assign BU1766_D[3] = n177; assign BU1766_D[4] = n178; assign BU1766_D[5] = n179; assign BU1766_D[6] = n180; assign BU1766_D[7] = n181; assign BU1766_D[8] = n182; assign BU1766_D[9] = n183; assign BU1766_D[10] = n184; assign BU1766_D[11] = n185; assign BU1766_D[12] = n186; assign BU1766_D[13] = n187; assign BU1766_D[14] = n188; assign BU1766_D[15] = n189; assign BU1766_D[16] = n190; wire [16 : 0] BU1766_Q; assign n314 = BU1766_Q[0]; assign n315 = BU1766_Q[1]; assign n316 = BU1766_Q[2]; assign n317 = BU1766_Q[3]; assign n318 = BU1766_Q[4]; assign n319 = BU1766_Q[5]; assign n320 = BU1766_Q[6]; assign n321 = BU1766_Q[7]; assign n322 = BU1766_Q[8]; assign n323 = BU1766_Q[9]; assign n324 = BU1766_Q[10]; assign n325 = BU1766_Q[11]; assign n326 = BU1766_Q[12]; assign n327 = BU1766_Q[13]; assign n328 = BU1766_Q[14]; assign n329 = BU1766_Q[15]; assign n330 = BU1766_Q[16]; wire BU1766_CLK; assign BU1766_CLK = n659; wire BU1766_CE; assign BU1766_CE = n660; C_REG_FD_V7_0 #( "00000000000000000" /* c_ainit_val*/, 0 /* c_enable_rlocs*/, 0 /* c_has_aclr*/, 0 /* c_has_ainit*/, 0 /* c_has_aset*/, 1 /* c_has_ce*/, 0 /* c_has_sclr*/, 0 /* c_has_sinit*/, 0 /* c_has_sset*/, "00000000000000000" /* c_sinit_val*/, 0 /* c_sync_enable*/, 0 /* c_sync_priority*/, 17 /* c_width*/ ) BU1766( .D(BU1766_D), .Q(BU1766_Q), .CLK(BU1766_CLK), .CE(BU1766_CE) ); wire BU3184_CLK; assign BU3184_CLK = n659; wire BU3184_SDIN; assign BU3184_SDIN = n99; wire BU3184_SDOUT; assign n620 = BU3184_SDOUT; wire BU3184_CE; assign BU3184_CE = n660; C_SHIFT_FD_V7_0 #( "0000000" /* c_ainit_val*/, 0 /* c_enable_rlocs*/, 5 /* c_fill_data*/, 0 /* c_has_aclr*/, 0 /* c_has_ainit*/, 0 /* c_has_aset*/, 1 /* c_has_ce*/, 0 /* c_has_d*/, 0 /* c_has_lsb_2_msb*/, 0 /* c_has_q*/, 0 /* c_has_sclr*/, 1 /* c_has_sdin*/, 1 /* c_has_sdout*/, 0 /* c_has_sinit*/, 0 /* c_has_sset*/, 0 /* c_shift_type*/, "0000000" /* c_sinit_val*/, 0 /* c_sync_enable*/, 0 /* c_sync_priority*/, 7 /* c_width*/ ) BU3184( .CLK(BU3184_CLK), .SDIN(BU3184_SDIN), .SDOUT(BU3184_SDOUT), .CE(BU3184_CE) ); defparam BU3204.INIT = 'h8888; wire BU3204_I0; assign BU3204_I0 = n660; wire BU3204_I1; assign BU3204_I1 = n620; wire BU3204_I2; assign BU3204_I2 = 1'b0; wire BU3204_I3; assign BU3204_I3 = 1'b0; wire BU3204_O; assign n331 = BU3204_O; LUT4 BU3204( .I0(BU3204_I0), .I1(BU3204_I1), .I2(BU3204_I2), .I3(BU3204_I3), .O(BU3204_O) ); wire BU3205_D; assign BU3205_D = n331; wire BU3205_C; assign BU3205_C = n659; wire BU3205_CE; assign BU3205_CE = n660; wire BU3205_Q; assign n661 = BU3205_Q; FDE BU3205( .D(BU3205_D), .C(BU3205_C), .CE(BU3205_CE), .Q(BU3205_Q) ); wire BU970_clk; assign BU970_clk = n659; wire [15 : 0] BU970_a; assign BU970_a[15] = n38; assign BU970_a[14] = n37; assign BU970_a[13] = n36; assign BU970_a[12] = n35; assign BU970_a[11] = n34; assign BU970_a[10] = n33; assign BU970_a[9] = n32; assign BU970_a[8] = n31; assign BU970_a[7] = n30; assign BU970_a[6] = n29; assign BU970_a[5] = n28; assign BU970_a[4] = n27; assign BU970_a[3] = n26; assign BU970_a[2] = n25; assign BU970_a[1] = n24; assign BU970_a[0] = n23; wire [6 : 0] BU970_b; assign BU970_b[6] = 1'b0; assign BU970_b[5] = 1'b0; assign BU970_b[4] = 1'b0; assign BU970_b[3] = 1'b0; assign BU970_b[2] = 1'b0; assign BU970_b[1] = 1'b0; assign BU970_b[0] = 1'b0; wire [22 : 0] BU970_o; wire [22 : 0] BU970_q; assign n139 = BU970_q[22]; assign n138 = BU970_q[21]; assign n137 = BU970_q[20]; assign n136 = BU970_q[19]; assign n135 = BU970_q[18]; assign n134 = BU970_q[17]; assign n133 = BU970_q[16]; assign n132 = BU970_q[15]; wire BU970_a_signed; assign BU970_a_signed = 1'b0; wire BU970_loadb; assign BU970_loadb = 1'b0; wire BU970_load_done; wire BU970_swapb; assign BU970_swapb = 1'b0; wire BU970_ce; assign BU970_ce = n660; wire BU970_aclr; assign BU970_aclr = 1'b0; wire BU970_sclr; assign BU970_sclr = 1'b0; wire BU970_rfd; wire BU970_nd; assign BU970_nd = 1'b0; wire BU970_rdy; MULT_GEN_V7_0 #( 8 /* bram_addr_width*/, 1 /* c_a_type*/, 16 /* c_a_width*/, 16 /* c_baat*/, 1 /* c_b_constant*/, 1 /* c_b_type*/, "1100101" /* c_b_value*/, 7 /* c_b_width*/, 0 /* c_enable_rlocs*/, 0 /* c_has_aclr*/, 0 /* c_has_a_signed*/, 1 /* c_has_b*/, 1 /* c_has_ce*/, 0 /* c_has_loadb*/, 0 /* c_has_load_done*/, 0 /* c_has_nd*/, 0 /* c_has_o*/, 1 /* c_has_q*/, 0 /* c_has_rdy*/, 0 /* c_has_rfd*/, 0 /* c_has_sclr*/, 0 /* c_has_swapb*/, "mem" /* c_mem_init_prefix*/, 0 /* c_mem_type*/, 2 /* c_mult_type*/, 0 /* c_output_hold*/, 23 /* c_out_width*/, 1 /* c_pipeline*/, 0 /* c_reg_a_b_inputs*/, 0 /* c_sqm_type*/, 0 /* c_stack_adders*/, 0 /* c_standalone*/, 1 /* c_sync_enable*/, 1 /* c_use_luts*/, 0 /* c_v2_speed*/ ) BU970( .CLK(BU970_clk), .A(BU970_a), .B(BU970_b), .O(BU970_o), .Q(BU970_q), .A_SIGNED(BU970_a_signed), .LOADB(BU970_loadb), .LOAD_DONE(BU970_load_done), .SWAPB(BU970_swapb), .CE(BU970_ce), .ACLR(BU970_aclr), .SCLR(BU970_sclr), .RFD(BU970_rfd), .ND(BU970_nd), .RDY(BU970_rdy) ); wire BU1471_CLK; assign BU1471_CLK = n659; wire [16 : 0] BU1471_D; assign BU1471_D[0] = n132; assign BU1471_D[1] = n133; assign BU1471_D[2] = n134; assign BU1471_D[3] = n135; assign BU1471_D[4] = n136; assign BU1471_D[5] = n137; assign BU1471_D[6] = n138; assign BU1471_D[7] = n139; assign BU1471_D[8] = 1'b0; assign BU1471_D[9] = 1'b0; assign BU1471_D[10] = 1'b0; assign BU1471_D[11] = 1'b0; assign BU1471_D[12] = 1'b0; assign BU1471_D[13] = 1'b0; assign BU1471_D[14] = 1'b0; assign BU1471_D[15] = 1'b0; assign BU1471_D[16] = 1'b0; wire [16 : 0] BU1471_Q; assign n174 = BU1471_Q[0]; assign n175 = BU1471_Q[1]; assign n176 = BU1471_Q[2]; assign n177 = BU1471_Q[3]; assign n178 = BU1471_Q[4]; assign n179 = BU1471_Q[5]; assign n180 = BU1471_Q[6]; assign n181 = BU1471_Q[7]; assign n182 = BU1471_Q[8]; assign n183 = BU1471_Q[9]; assign n184 = BU1471_Q[10]; assign n185 = BU1471_Q[11]; assign n186 = BU1471_Q[12]; assign n187 = BU1471_Q[13]; assign n188 = BU1471_Q[14]; assign n189 = BU1471_Q[15]; assign n190 = BU1471_Q[16]; wire BU1471_CE; assign BU1471_CE = n660; C_SHIFT_RAM_V7_0 #( 1 /* c_addr_width*/, "00000000000000000" /* c_ainit_val*/, "0" /* c_default_data*/, 2 /* c_default_data_radix*/, 2 /* c_depth*/, 0 /* c_enable_rlocs*/, 0 /* c_generate_mif*/, 0 /* c_has_a*/, 0 /* c_has_aclr*/, 0 /* c_has_ainit*/, 0 /* c_has_aset*/, 1 /* c_has_ce*/, 0 /* c_has_sclr*/, 0 /* c_has_sinit*/, 0 /* c_has_sset*/, "null" /* c_mem_init_file*/, 2 /* c_mem_init_radix*/, 0 /* c_read_mif*/, 1 /* c_reg_last_bit*/, 0 /* c_shift_type*/, "00000000000000000" /* c_sinit_val*/, 0 /* c_sync_enable*/, 0 /* c_sync_priority*/, 17 /* c_width*/ ) BU1471( .CLK(BU1471_CLK), .D(BU1471_D), .Q(BU1471_Q), .CE(BU1471_CE) ); wire BU1601_clk; assign BU1601_clk = n659; wire [17 : 0] BU1601_a; assign BU1601_a[17] = n243; assign BU1601_a[16] = n242; assign BU1601_a[15] = n241; assign BU1601_a[14] = n240; assign BU1601_a[13] = n239; assign BU1601_a[12] = n238; assign BU1601_a[11] = n237; assign BU1601_a[10] = n236; assign BU1601_a[9] = n235; assign BU1601_a[8] = n234; assign BU1601_a[7] = n233; assign BU1601_a[6] = n232; assign BU1601_a[5] = n231; assign BU1601_a[4] = n230; assign BU1601_a[3] = n229; assign BU1601_a[2] = n228; assign BU1601_a[1] = n227; assign BU1601_a[0] = n226; wire [16 : 0] BU1601_b; assign BU1601_b[16] = n260; assign BU1601_b[15] = n259; assign BU1601_b[14] = n258; assign BU1601_b[13] = n257; assign BU1601_b[12] = n256; assign BU1601_b[11] = n255; assign BU1601_b[10] = n254; assign BU1601_b[9] = n253; assign BU1601_b[8] = n252; assign BU1601_b[7] = n251; assign BU1601_b[6] = n250; assign BU1601_b[5] = n249; assign BU1601_b[4] = n248; assign BU1601_b[3] = n247; assign BU1601_b[2] = n246; assign BU1601_b[1] = n245; assign BU1601_b[0] = n244; wire [34 : 0] BU1601_o; wire [34 : 0] BU1601_q; assign n225 = BU1601_q[34]; assign n224 = BU1601_q[33]; assign n223 = BU1601_q[32]; assign n222 = BU1601_q[31]; assign n221 = BU1601_q[30]; assign n220 = BU1601_q[29]; assign n219 = BU1601_q[28]; assign n218 = BU1601_q[27]; assign n217 = BU1601_q[26]; assign n216 = BU1601_q[25]; assign n215 = BU1601_q[24]; assign n214 = BU1601_q[23]; assign n213 = BU1601_q[22]; assign n212 = BU1601_q[21]; assign n211 = BU1601_q[20]; assign n210 = BU1601_q[19]; assign n209 = BU1601_q[18]; assign n208 = BU1601_q[17]; assign n207 = BU1601_q[16]; assign n206 = BU1601_q[15]; assign n205 = BU1601_q[14]; assign n204 = BU1601_q[13]; assign n203 = BU1601_q[12]; assign n202 = BU1601_q[11]; assign n201 = BU1601_q[10]; assign n200 = BU1601_q[9]; assign n199 = BU1601_q[8]; assign n198 = BU1601_q[7]; assign n197 = BU1601_q[6]; assign n196 = BU1601_q[5]; assign n195 = BU1601_q[4]; assign n194 = BU1601_q[3]; assign n193 = BU1601_q[2]; assign n192 = BU1601_q[1]; assign n191 = BU1601_q[0]; wire BU1601_a_signed; assign BU1601_a_signed = 1'b0; wire BU1601_loadb; assign BU1601_loadb = 1'b0; wire BU1601_load_done; wire BU1601_swapb; assign BU1601_swapb = 1'b0; wire BU1601_ce; assign BU1601_ce = n660; wire BU1601_aclr; assign BU1601_aclr = 1'b0; wire BU1601_sclr; assign BU1601_sclr = 1'b0; wire BU1601_rfd; wire BU1601_nd; assign BU1601_nd = 1'b0; wire BU1601_rdy; MULT_GEN_V7_0 #( 8 /* bram_addr_width*/, 0 /* c_a_type*/, 18 /* c_a_width*/, 18 /* c_baat*/, 0 /* c_b_constant*/, 1 /* c_b_type*/, "0000000000000001" /* c_b_value*/, 17 /* c_b_width*/, 0 /* c_enable_rlocs*/, 0 /* c_has_aclr*/, 0 /* c_has_a_signed*/, 1 /* c_has_b*/, 1 /* c_has_ce*/, 0 /* c_has_loadb*/, 0 /* c_has_load_done*/, 0 /* c_has_nd*/, 0 /* c_has_o*/, 1 /* c_has_q*/, 0 /* c_has_rdy*/, 0 /* c_has_rfd*/, 0 /* c_has_sclr*/, 0 /* c_has_swapb*/, "mem" /* c_mem_init_prefix*/, 0 /* c_mem_type*/, 1 /* c_mult_type*/, 0 /* c_output_hold*/, 35 /* c_out_width*/, 1 /* c_pipeline*/, 0 /* c_reg_a_b_inputs*/, 0 /* c_sqm_type*/, 0 /* c_stack_adders*/, 0 /* c_standalone*/, 1 /* c_sync_enable*/, 1 /* c_use_luts*/, 0 /* c_v2_speed*/ ) BU1601( .CLK(BU1601_clk), .A(BU1601_a), .B(BU1601_b), .O(BU1601_o), .Q(BU1601_q), .A_SIGNED(BU1601_a_signed), .LOADB(BU1601_loadb), .LOAD_DONE(BU1601_load_done), .SWAPB(BU1601_swapb), .CE(BU1601_ce), .ACLR(BU1601_aclr), .SCLR(BU1601_sclr), .RFD(BU1601_rfd), .ND(BU1601_nd), .RDY(BU1601_rdy) ); wire [34 : 0] BU2047_A; assign BU2047_A[0] = 1'b0; assign BU2047_A[1] = 1'b0; assign BU2047_A[2] = 1'b0; assign BU2047_A[3] = 1'b0; assign BU2047_A[4] = 1'b0; assign BU2047_A[5] = 1'b0; assign BU2047_A[6] = 1'b0; assign BU2047_A[7] = 1'b0; assign BU2047_A[8] = 1'b0; assign BU2047_A[9] = 1'b0; assign BU2047_A[10] = 1'b0; assign BU2047_A[11] = 1'b0; assign BU2047_A[12] = 1'b0; assign BU2047_A[13] = 1'b0; assign BU2047_A[14] = 1'b0; assign BU2047_A[15] = 1'b0; assign BU2047_A[16] = 1'b0; assign BU2047_A[17] = n385; assign BU2047_A[18] = n386; assign BU2047_A[19] = n387; assign BU2047_A[20] = n388; assign BU2047_A[21] = n389; assign BU2047_A[22] = n390; assign BU2047_A[23] = n391; assign BU2047_A[24] = n392; assign BU2047_A[25] = n393; assign BU2047_A[26] = n394; assign BU2047_A[27] = n395; assign BU2047_A[28] = n396; assign BU2047_A[29] = n397; assign BU2047_A[30] = n398; assign BU2047_A[31] = n399; assign BU2047_A[32] = n400; assign BU2047_A[33] = n401; assign BU2047_A[34] = n402; wire [34 : 0] BU2047_B; assign BU2047_B[0] = n191; assign BU2047_B[1] = n192; assign BU2047_B[2] = n193; assign BU2047_B[3] = n194; assign BU2047_B[4] = n195; assign BU2047_B[5] = n196; assign BU2047_B[6] = n197; assign BU2047_B[7] = n198; assign BU2047_B[8] = n199; assign BU2047_B[9] = n200; assign BU2047_B[10] = n201; assign BU2047_B[11] = n202; assign BU2047_B[12] = n203; assign BU2047_B[13] = n204; assign BU2047_B[14] = n205; assign BU2047_B[15] = n206; assign BU2047_B[16] = n207; assign BU2047_B[17] = n208; assign BU2047_B[18] = n209; assign BU2047_B[19] = n210; assign BU2047_B[20] = n211; assign BU2047_B[21] = n212; assign BU2047_B[22] = n213; assign BU2047_B[23] = n214; assign BU2047_B[24] = n215; assign BU2047_B[25] = n216; assign BU2047_B[26] = n217; assign BU2047_B[27] = n218; assign BU2047_B[28] = n219; assign BU2047_B[29] = n220; assign BU2047_B[30] = n221; assign BU2047_B[31] = n222; assign BU2047_B[32] = n223; assign BU2047_B[33] = n224; assign BU2047_B[34] = n225; wire BU2047_Q_OVFL; assign n578 = BU2047_Q_OVFL; wire [34 : 0] BU2047_Q; assign n508 = BU2047_Q[0]; assign n509 = BU2047_Q[1]; assign n510 = BU2047_Q[2]; assign n511 = BU2047_Q[3]; assign n512 = BU2047_Q[4]; assign n513 = BU2047_Q[5]; assign n514 = BU2047_Q[6]; assign n515 = BU2047_Q[7]; assign n516 = BU2047_Q[8]; assign n517 = BU2047_Q[9]; assign n518 = BU2047_Q[10]; assign n519 = BU2047_Q[11]; assign n520 = BU2047_Q[12]; assign n521 = BU2047_Q[13]; assign n522 = BU2047_Q[14]; assign n523 = BU2047_Q[15]; assign n524 = BU2047_Q[16]; assign n525 = BU2047_Q[17]; assign n526 = BU2047_Q[18]; assign n527 = BU2047_Q[19]; assign n528 = BU2047_Q[20]; assign n529 = BU2047_Q[21]; assign n530 = BU2047_Q[22]; assign n531 = BU2047_Q[23]; assign n532 = BU2047_Q[24]; assign n533 = BU2047_Q[25]; assign n534 = BU2047_Q[26]; assign n535 = BU2047_Q[27]; assign n536 = BU2047_Q[28]; assign n537 = BU2047_Q[29]; assign n538 = BU2047_Q[30]; assign n539 = BU2047_Q[31]; assign n540 = BU2047_Q[32]; assign n541 = BU2047_Q[33]; assign n542 = BU2047_Q[34]; wire BU2047_CLK; assign BU2047_CLK = n659; wire BU2047_CE; assign BU2047_CE = n660; C_ADDSUB_V7_0 #( 1 /* c_add_mode*/, "0" /* c_ainit_val*/, 0 /* c_a_type*/, 35 /* c_a_width*/, 0 /* c_bypass_enable*/, 0 /* c_bypass_low*/, 0 /* c_b_constant*/, 0 /* c_b_type*/, "00000000000000000000000000000000000" /* c_b_value*/, 35 /* c_b_width*/, 0 /* c_enable_rlocs*/, 0 /* c_has_aclr*/, 0 /* c_has_add*/, 0 /* c_has_ainit*/, 0 /* c_has_aset*/, 0 /* c_has_a_signed*/, 0 /* c_has_bypass*/, 0 /* c_has_bypass_with_cin*/, 0 /* c_has_b_in*/, 0 /* c_has_b_out*/, 0 /* c_has_b_signed*/, 1 /* c_has_ce*/, 0 /* c_has_c_in*/, 0 /* c_has_c_out*/, 0 /* c_has_ovfl*/, 1 /* c_has_q*/, 0 /* c_has_q_b_out*/, 0 /* c_has_q_c_out*/, 1 /* c_has_q_ovfl*/, 1 /* c_has_s*/, 0 /* c_has_sclr*/, 0 /* c_has_sinit*/, 0 /* c_has_sset*/, 34 /* c_high_bit*/, 1 /* c_latency*/, 0 /* c_low_bit*/, 35 /* c_out_width*/, 0 /* c_pipe_stages*/, "0" /* c_sinit_val*/, 0 /* c_sync_enable*/, 0 /* c_sync_priority*/ ) BU2047( .A(BU2047_A), .B(BU2047_B), .Q_OVFL(BU2047_Q_OVFL), .Q(BU2047_Q), .CLK(BU2047_CLK), .CE(BU2047_CE) ); wire BU1929_CLK; assign BU1929_CLK = n659; wire [17 : 0] BU1929_D; assign BU1929_D[0] = n81; assign BU1929_D[1] = n82; assign BU1929_D[2] = n83; assign BU1929_D[3] = n84; assign BU1929_D[4] = n85; assign BU1929_D[5] = n86; assign BU1929_D[6] = n87; assign BU1929_D[7] = n88; assign BU1929_D[8] = n89; assign BU1929_D[9] = n90; assign BU1929_D[10] = n91; assign BU1929_D[11] = n92; assign BU1929_D[12] = n93; assign BU1929_D[13] = n94; assign BU1929_D[14] = n95; assign BU1929_D[15] = n96; assign BU1929_D[16] = n97; assign BU1929_D[17] = n98; wire [17 : 0] BU1929_Q; assign n385 = BU1929_Q[0]; assign n386 = BU1929_Q[1]; assign n387 = BU1929_Q[2]; assign n388 = BU1929_Q[3]; assign n389 = BU1929_Q[4]; assign n390 = BU1929_Q[5]; assign n391 = BU1929_Q[6]; assign n392 = BU1929_Q[7]; assign n393 = BU1929_Q[8]; assign n394 = BU1929_Q[9]; assign n395 = BU1929_Q[10]; assign n396 = BU1929_Q[11]; assign n397 = BU1929_Q[12]; assign n398 = BU1929_Q[13]; assign n399 = BU1929_Q[14]; assign n400 = BU1929_Q[15]; assign n401 = BU1929_Q[16]; assign n402 = BU1929_Q[17]; wire BU1929_CE; assign BU1929_CE = n660; C_SHIFT_RAM_V7_0 #( 1 /* c_addr_width*/, "000000000000000000" /* c_ainit_val*/, "0" /* c_default_data*/, 2 /* c_default_data_radix*/, 3 /* c_depth*/, 0 /* c_enable_rlocs*/, 0 /* c_generate_mif*/, 0 /* c_has_a*/, 0 /* c_has_aclr*/, 0 /* c_has_ainit*/, 0 /* c_has_aset*/, 1 /* c_has_ce*/, 0 /* c_has_sclr*/, 0 /* c_has_sinit*/, 0 /* c_has_sset*/, "null" /* c_mem_init_file*/, 2 /* c_mem_init_radix*/, 0 /* c_read_mif*/, 1 /* c_reg_last_bit*/, 0 /* c_shift_type*/, "000000000000000000" /* c_sinit_val*/, 0 /* c_sync_enable*/, 0 /* c_sync_priority*/, 18 /* c_width*/ ) BU1929( .CLK(BU1929_CLK), .D(BU1929_D), .Q(BU1929_Q), .CE(BU1929_CE) ); wire BU1802_clk; assign BU1802_clk = n659; wire [17 : 0] BU1802_a; assign BU1802_a[17] = n313; assign BU1802_a[16] = n312; assign BU1802_a[15] = n311; assign BU1802_a[14] = n310; assign BU1802_a[13] = n309; assign BU1802_a[12] = n308; assign BU1802_a[11] = n307; assign BU1802_a[10] = n306; assign BU1802_a[9] = n305; assign BU1802_a[8] = n304; assign BU1802_a[7] = n303; assign BU1802_a[6] = n302; assign BU1802_a[5] = n301; assign BU1802_a[4] = n300; assign BU1802_a[3] = n299; assign BU1802_a[2] = n298; assign BU1802_a[1] = n297; assign BU1802_a[0] = n296; wire [16 : 0] BU1802_b; assign BU1802_b[16] = n330; assign BU1802_b[15] = n329; assign BU1802_b[14] = n328; assign BU1802_b[13] = n327; assign BU1802_b[12] = n326; assign BU1802_b[11] = n325; assign BU1802_b[10] = n324; assign BU1802_b[9] = n323; assign BU1802_b[8] = n322; assign BU1802_b[7] = n321; assign BU1802_b[6] = n320; assign BU1802_b[5] = n319; assign BU1802_b[4] = n318; assign BU1802_b[3] = n317; assign BU1802_b[2] = n316; assign BU1802_b[1] = n315; assign BU1802_b[0] = n314; wire [34 : 0] BU1802_o; wire [34 : 0] BU1802_q; assign n295 = BU1802_q[34]; assign n294 = BU1802_q[33]; assign n293 = BU1802_q[32]; assign n292 = BU1802_q[31]; assign n291 = BU1802_q[30]; assign n290 = BU1802_q[29]; assign n289 = BU1802_q[28]; assign n288 = BU1802_q[27]; assign n287 = BU1802_q[26]; assign n286 = BU1802_q[25]; assign n285 = BU1802_q[24]; assign n284 = BU1802_q[23]; assign n283 = BU1802_q[22]; assign n282 = BU1802_q[21]; assign n281 = BU1802_q[20]; assign n280 = BU1802_q[19]; assign n279 = BU1802_q[18]; assign n278 = BU1802_q[17]; assign n277 = BU1802_q[16]; assign n276 = BU1802_q[15]; assign n275 = BU1802_q[14]; assign n274 = BU1802_q[13]; assign n273 = BU1802_q[12]; assign n272 = BU1802_q[11]; assign n271 = BU1802_q[10]; assign n270 = BU1802_q[9]; assign n269 = BU1802_q[8]; assign n268 = BU1802_q[7]; assign n267 = BU1802_q[6]; assign n266 = BU1802_q[5]; assign n265 = BU1802_q[4]; assign n264 = BU1802_q[3]; assign n263 = BU1802_q[2]; assign n262 = BU1802_q[1]; assign n261 = BU1802_q[0]; wire BU1802_a_signed; assign BU1802_a_signed = 1'b0; wire BU1802_loadb; assign BU1802_loadb = 1'b0; wire BU1802_load_done; wire BU1802_swapb; assign BU1802_swapb = 1'b0; wire BU1802_ce; assign BU1802_ce = n660; wire BU1802_aclr; assign BU1802_aclr = 1'b0; wire BU1802_sclr; assign BU1802_sclr = 1'b0; wire BU1802_rfd; wire BU1802_nd; assign BU1802_nd = 1'b0; wire BU1802_rdy; MULT_GEN_V7_0 #( 8 /* bram_addr_width*/, 0 /* c_a_type*/, 18 /* c_a_width*/, 18 /* c_baat*/, 0 /* c_b_constant*/, 1 /* c_b_type*/, "0000000000000001" /* c_b_value*/, 17 /* c_b_width*/, 0 /* c_enable_rlocs*/, 0 /* c_has_aclr*/, 0 /* c_has_a_signed*/, 1 /* c_has_b*/, 1 /* c_has_ce*/, 0 /* c_has_loadb*/, 0 /* c_has_load_done*/, 0 /* c_has_nd*/, 0 /* c_has_o*/, 1 /* c_has_q*/, 0 /* c_has_rdy*/, 0 /* c_has_rfd*/, 0 /* c_has_sclr*/, 0 /* c_has_swapb*/, "mem" /* c_mem_init_prefix*/, 0 /* c_mem_type*/, 1 /* c_mult_type*/, 0 /* c_output_hold*/, 35 /* c_out_width*/, 1 /* c_pipeline*/, 0 /* c_reg_a_b_inputs*/, 0 /* c_sqm_type*/, 0 /* c_stack_adders*/, 0 /* c_standalone*/, 1 /* c_sync_enable*/, 1 /* c_use_luts*/, 0 /* c_v2_speed*/ ) BU1802( .CLK(BU1802_clk), .A(BU1802_a), .B(BU1802_b), .O(BU1802_o), .Q(BU1802_q), .A_SIGNED(BU1802_a_signed), .LOADB(BU1802_loadb), .LOAD_DONE(BU1802_load_done), .SWAPB(BU1802_swapb), .CE(BU1802_ce), .ACLR(BU1802_aclr), .SCLR(BU1802_sclr), .RFD(BU1802_rfd), .ND(BU1802_nd), .RDY(BU1802_rdy) ); wire [34 : 0] BU2615_A; assign BU2615_A[0] = 1'b0; assign BU2615_A[1] = 1'b0; assign BU2615_A[2] = 1'b0; assign BU2615_A[3] = 1'b0; assign BU2615_A[4] = 1'b0; assign BU2615_A[5] = 1'b0; assign BU2615_A[6] = 1'b0; assign BU2615_A[7] = 1'b0; assign BU2615_A[8] = 1'b0; assign BU2615_A[9] = 1'b0; assign BU2615_A[10] = 1'b0; assign BU2615_A[11] = 1'b0; assign BU2615_A[12] = 1'b0; assign BU2615_A[13] = 1'b0; assign BU2615_A[14] = 1'b0; assign BU2615_A[15] = 1'b0; assign BU2615_A[16] = 1'b0; assign BU2615_A[17] = n455; assign BU2615_A[18] = n456; assign BU2615_A[19] = n457; assign BU2615_A[20] = n458; assign BU2615_A[21] = n459; assign BU2615_A[22] = n460; assign BU2615_A[23] = n461; assign BU2615_A[24] = n462; assign BU2615_A[25] = n463; assign BU2615_A[26] = n464; assign BU2615_A[27] = n465; assign BU2615_A[28] = n466; assign BU2615_A[29] = n467; assign BU2615_A[30] = n468; assign BU2615_A[31] = n469; assign BU2615_A[32] = n470; assign BU2615_A[33] = n471; assign BU2615_A[34] = n472; wire [34 : 0] BU2615_B; assign BU2615_B[0] = n261; assign BU2615_B[1] = n262; assign BU2615_B[2] = n263; assign BU2615_B[3] = n264; assign BU2615_B[4] = n265; assign BU2615_B[5] = n266; assign BU2615_B[6] = n267; assign BU2615_B[7] = n268; assign BU2615_B[8] = n269; assign BU2615_B[9] = n270; assign BU2615_B[10] = n271; assign BU2615_B[11] = n272; assign BU2615_B[12] = n273; assign BU2615_B[13] = n274; assign BU2615_B[14] = n275; assign BU2615_B[15] = n276; assign BU2615_B[16] = n277; assign BU2615_B[17] = n278; assign BU2615_B[18] = n279; assign BU2615_B[19] = n280; assign BU2615_B[20] = n281; assign BU2615_B[21] = n282; assign BU2615_B[22] = n283; assign BU2615_B[23] = n284; assign BU2615_B[24] = n285; assign BU2615_B[25] = n286; assign BU2615_B[26] = n287; assign BU2615_B[27] = n288; assign BU2615_B[28] = n289; assign BU2615_B[29] = n290; assign BU2615_B[30] = n291; assign BU2615_B[31] = n292; assign BU2615_B[32] = n293; assign BU2615_B[33] = n294; assign BU2615_B[34] = n295; wire BU2615_Q_OVFL; assign n579 = BU2615_Q_OVFL; wire [34 : 0] BU2615_Q; assign n543 = BU2615_Q[0]; assign n544 = BU2615_Q[1]; assign n545 = BU2615_Q[2]; assign n546 = BU2615_Q[3]; assign n547 = BU2615_Q[4]; assign n548 = BU2615_Q[5]; assign n549 = BU2615_Q[6]; assign n550 = BU2615_Q[7]; assign n551 = BU2615_Q[8]; assign n552 = BU2615_Q[9]; assign n553 = BU2615_Q[10]; assign n554 = BU2615_Q[11]; assign n555 = BU2615_Q[12]; assign n556 = BU2615_Q[13]; assign n557 = BU2615_Q[14]; assign n558 = BU2615_Q[15]; assign n559 = BU2615_Q[16]; assign n560 = BU2615_Q[17]; assign n561 = BU2615_Q[18]; assign n562 = BU2615_Q[19]; assign n563 = BU2615_Q[20]; assign n564 = BU2615_Q[21]; assign n565 = BU2615_Q[22]; assign n566 = BU2615_Q[23]; assign n567 = BU2615_Q[24]; assign n568 = BU2615_Q[25]; assign n569 = BU2615_Q[26]; assign n570 = BU2615_Q[27]; assign n571 = BU2615_Q[28]; assign n572 = BU2615_Q[29]; assign n573 = BU2615_Q[30]; assign n574 = BU2615_Q[31]; assign n575 = BU2615_Q[32]; assign n576 = BU2615_Q[33]; assign n577 = BU2615_Q[34]; wire BU2615_CLK; assign BU2615_CLK = n659; wire BU2615_CE; assign BU2615_CE = n660; C_ADDSUB_V7_0 #( 0 /* c_add_mode*/, "0" /* c_ainit_val*/, 0 /* c_a_type*/, 35 /* c_a_width*/, 0 /* c_bypass_enable*/, 0 /* c_bypass_low*/, 0 /* c_b_constant*/, 0 /* c_b_type*/, "00000000000000000000000000000000000" /* c_b_value*/, 35 /* c_b_width*/, 0 /* c_enable_rlocs*/, 0 /* c_has_aclr*/, 0 /* c_has_add*/, 0 /* c_has_ainit*/, 0 /* c_has_aset*/, 0 /* c_has_a_signed*/, 0 /* c_has_bypass*/, 0 /* c_has_bypass_with_cin*/, 0 /* c_has_b_in*/, 0 /* c_has_b_out*/, 0 /* c_has_b_signed*/, 1 /* c_has_ce*/, 0 /* c_has_c_in*/, 0 /* c_has_c_out*/, 0 /* c_has_ovfl*/, 1 /* c_has_q*/, 0 /* c_has_q_b_out*/, 0 /* c_has_q_c_out*/, 1 /* c_has_q_ovfl*/, 1 /* c_has_s*/, 0 /* c_has_sclr*/, 0 /* c_has_sinit*/, 0 /* c_has_sset*/, 34 /* c_high_bit*/, 1 /* c_latency*/, 0 /* c_low_bit*/, 35 /* c_out_width*/, 0 /* c_pipe_stages*/, "0" /* c_sinit_val*/, 0 /* c_sync_enable*/, 0 /* c_sync_priority*/ ) BU2615( .A(BU2615_A), .B(BU2615_B), .Q_OVFL(BU2615_Q_OVFL), .Q(BU2615_Q), .CLK(BU2615_CLK), .CE(BU2615_CE) ); wire BU1988_CLK; assign BU1988_CLK = n659; wire [17 : 0] BU1988_D; assign BU1988_D[0] = n63; assign BU1988_D[1] = n64; assign BU1988_D[2] = n65; assign BU1988_D[3] = n66; assign BU1988_D[4] = n67; assign BU1988_D[5] = n68; assign BU1988_D[6] = n69; assign BU1988_D[7] = n70; assign BU1988_D[8] = n71; assign BU1988_D[9] = n72; assign BU1988_D[10] = n73; assign BU1988_D[11] = n74; assign BU1988_D[12] = n75; assign BU1988_D[13] = n76; assign BU1988_D[14] = n77; assign BU1988_D[15] = n78; assign BU1988_D[16] = n79; assign BU1988_D[17] = n80; wire [17 : 0] BU1988_Q; assign n455 = BU1988_Q[0]; assign n456 = BU1988_Q[1]; assign n457 = BU1988_Q[2]; assign n458 = BU1988_Q[3]; assign n459 = BU1988_Q[4]; assign n460 = BU1988_Q[5]; assign n461 = BU1988_Q[6]; assign n462 = BU1988_Q[7]; assign n463 = BU1988_Q[8]; assign n464 = BU1988_Q[9]; assign n465 = BU1988_Q[10]; assign n466 = BU1988_Q[11]; assign n467 = BU1988_Q[12]; assign n468 = BU1988_Q[13]; assign n469 = BU1988_Q[14]; assign n470 = BU1988_Q[15]; assign n471 = BU1988_Q[16]; assign n472 = BU1988_Q[17]; wire BU1988_CE; assign BU1988_CE = n660; C_SHIFT_RAM_V7_0 #( 1 /* c_addr_width*/, "000000000000000000" /* c_ainit_val*/, "0" /* c_default_data*/, 2 /* c_default_data_radix*/, 3 /* c_depth*/, 0 /* c_enable_rlocs*/, 0 /* c_generate_mif*/, 0 /* c_has_a*/, 0 /* c_has_aclr*/, 0 /* c_has_ainit*/, 0 /* c_has_aset*/, 1 /* c_has_ce*/, 0 /* c_has_sclr*/, 0 /* c_has_sinit*/, 0 /* c_has_sset*/, "null" /* c_mem_init_file*/, 2 /* c_mem_init_radix*/, 0 /* c_read_mif*/, 1 /* c_reg_last_bit*/, 0 /* c_shift_type*/, "000000000000000000" /* c_sinit_val*/, 0 /* c_sync_enable*/, 0 /* c_sync_priority*/, 18 /* c_width*/ ) BU1988( .CLK(BU1988_CLK), .D(BU1988_D), .Q(BU1988_Q), .CE(BU1988_CE) ); wire [0 : 0] BU2326_D; assign BU2326_D[0] = n6460; wire [0 : 0] BU2326_Q; assign n6428 = BU2326_Q[0]; wire BU2326_CLK; assign BU2326_CLK = n659; wire BU2326_CE; assign BU2326_CE = n660; C_REG_FD_V7_0 #( "0" /* c_ainit_val*/, 0 /* c_enable_rlocs*/, 0 /* c_has_aclr*/, 0 /* c_has_ainit*/, 0 /* c_has_aset*/, 1 /* c_has_ce*/, 0 /* c_has_sclr*/, 0 /* c_has_sinit*/, 0 /* c_has_sset*/, "0" /* c_sinit_val*/, 0 /* c_sync_enable*/, 0 /* c_sync_priority*/, 1 /* c_width*/ ) BU2326( .D(BU2326_D), .Q(BU2326_Q), .CLK(BU2326_CLK), .CE(BU2326_CE) ); defparam BU2330.INIT = 'hc4c4; wire BU2330_I0; assign BU2330_I0 = n6404; wire BU2330_I1; assign BU2330_I1 = n522; wire BU2330_I2; assign BU2330_I2 = n6445; wire BU2330_I3; assign BU2330_I3 = 1'b0; wire BU2330_O; assign n6460 = BU2330_O; LUT4 BU2330( .I0(BU2330_I0), .I1(BU2330_I1), .I2(BU2330_I2), .I3(BU2330_I3), .O(BU2330_O) ); wire [13 : 0] BU2307_I; assign BU2307_I[0] = n508; assign BU2307_I[1] = n509; assign BU2307_I[2] = n510; assign BU2307_I[3] = n511; assign BU2307_I[4] = n512; assign BU2307_I[5] = n513; assign BU2307_I[6] = n514; assign BU2307_I[7] = n515; assign BU2307_I[8] = n516; assign BU2307_I[9] = n517; assign BU2307_I[10] = n518; assign BU2307_I[11] = n519; assign BU2307_I[12] = n520; assign BU2307_I[13] = n521; wire BU2307_T; assign BU2307_T = 1'b0; wire BU2307_EN; assign BU2307_EN = 1'b0; wire BU2307_Q; wire BU2307_CLK; assign BU2307_CLK = 1'b0; wire BU2307_CE; assign BU2307_CE = 1'b0; wire BU2307_ACLR; assign BU2307_ACLR = 1'b0; wire BU2307_ASET; assign BU2307_ASET = 1'b0; wire BU2307_AINIT; assign BU2307_AINIT = 1'b0; wire BU2307_SCLR; assign BU2307_SCLR = 1'b0; wire BU2307_SSET; assign BU2307_SSET = 1'b0; wire BU2307_SINIT; assign BU2307_SINIT = 1'b0; wire BU2307_O; assign n6445 = BU2307_O; C_GATE_BIT_V7_0 #( "0" /* c_ainit_val*/, 0 /* c_enable_rlocs*/, 2 /* c_gate_type*/, 0 /* c_has_aclr*/, 0 /* c_has_ainit*/, 0 /* c_has_aset*/, 0 /* c_has_ce*/, 1 /* c_has_o*/, 1 /* c_has_q*/, 0 /* c_has_sclr*/, 0 /* c_has_sinit*/, 0 /* c_has_sset*/, 14 /* c_inputs*/, "000000000000000" /* c_input_inv_mask*/, 0 /* c_pipe_stages*/, "0" /* c_sinit_val*/, 0 /* c_sync_enable*/, 1 /* c_sync_priority*/ ) BU2307( .I(BU2307_I), .T(BU2307_T), .EN(BU2307_EN), .Q(BU2307_Q), .CLK(BU2307_CLK), .CE(BU2307_CE), .ACLR(BU2307_ACLR), .ASET(BU2307_ASET), .AINIT(BU2307_AINIT), .SCLR(BU2307_SCLR), .SSET(BU2307_SSET), .SINIT(BU2307_SINIT), .O(BU2307_O) ); wire [19 : 0] BU2266_D; assign BU2266_D[0] = n523; assign BU2266_D[1] = n524; assign BU2266_D[2] = n525; assign BU2266_D[3] = n526; assign BU2266_D[4] = n527; assign BU2266_D[5] = n528; assign BU2266_D[6] = n529; assign BU2266_D[7] = n530; assign BU2266_D[8] = n531; assign BU2266_D[9] = n532; assign BU2266_D[10] = n533; assign BU2266_D[11] = n534; assign BU2266_D[12] = n535; assign BU2266_D[13] = n536; assign BU2266_D[14] = n537; assign BU2266_D[15] = n538; assign BU2266_D[16] = n539; assign BU2266_D[17] = n540; assign BU2266_D[18] = n541; assign BU2266_D[19] = n542; wire [19 : 0] BU2266_Q; assign n6385 = BU2266_Q[0]; assign n6386 = BU2266_Q[1]; assign n6387 = BU2266_Q[2]; assign n6388 = BU2266_Q[3]; assign n6389 = BU2266_Q[4]; assign n6390 = BU2266_Q[5]; assign n6391 = BU2266_Q[6]; assign n6392 = BU2266_Q[7]; assign n6393 = BU2266_Q[8]; assign n6394 = BU2266_Q[9]; assign n6395 = BU2266_Q[10]; assign n6396 = BU2266_Q[11]; assign n6397 = BU2266_Q[12]; assign n6398 = BU2266_Q[13]; assign n6399 = BU2266_Q[14]; assign n6400 = BU2266_Q[15]; assign n6401 = BU2266_Q[16]; assign n6402 = BU2266_Q[17]; assign n6403 = BU2266_Q[18]; assign n6404 = BU2266_Q[19]; wire BU2266_CLK; assign BU2266_CLK = n659; wire BU2266_CE; assign BU2266_CE = n660; C_REG_FD_V7_0 #( "00000000000000000000" /* c_ainit_val*/, 0 /* c_enable_rlocs*/, 0 /* c_has_aclr*/, 0 /* c_has_ainit*/, 0 /* c_has_aset*/, 1 /* c_has_ce*/, 0 /* c_has_sclr*/, 0 /* c_has_sinit*/, 0 /* c_has_sset*/, "00000000000000000000" /* c_sinit_val*/, 0 /* c_sync_enable*/, 0 /* c_sync_priority*/, 20 /* c_width*/ ) BU2266( .D(BU2266_D), .Q(BU2266_Q), .CLK(BU2266_CLK), .CE(BU2266_CE) ); wire BU2461_CLK; assign BU2461_CLK = n659; wire [0 : 0] BU2461_D; assign BU2461_D[0] = n578; wire [0 : 0] BU2461_Q; assign n6461 = BU2461_Q[0]; wire BU2461_CE; assign BU2461_CE = n660; C_SHIFT_RAM_V7_0 #( 1 /* c_addr_width*/, "0" /* c_ainit_val*/, "0" /* c_default_data*/, 2 /* c_default_data_radix*/, 2 /* c_depth*/, 0 /* c_enable_rlocs*/, 0 /* c_generate_mif*/, 0 /* c_has_a*/, 0 /* c_has_aclr*/, 0 /* c_has_ainit*/, 0 /* c_has_aset*/, 1 /* c_has_ce*/, 0 /* c_has_sclr*/, 0 /* c_has_sinit*/, 0 /* c_has_sset*/, "null" /* c_mem_init_file*/, 2 /* c_mem_init_radix*/, 0 /* c_read_mif*/, 1 /* c_reg_last_bit*/, 0 /* c_shift_type*/, "0" /* c_sinit_val*/, 0 /* c_sync_enable*/, 0 /* c_sync_priority*/, 1 /* c_width*/ ) BU2461( .CLK(BU2461_CLK), .D(BU2461_D), .Q(BU2461_Q), .CE(BU2461_CE) ); wire [0 : 0] BU2469_D; assign BU2469_D[0] = n6404; wire [0 : 0] BU2469_Q; assign n6462 = BU2469_Q[0]; wire BU2469_CLK; assign BU2469_CLK = n659; wire BU2469_CE; assign BU2469_CE = n660; C_REG_FD_V7_0 #( "0" /* c_ainit_val*/, 0 /* c_enable_rlocs*/, 0 /* c_has_aclr*/, 0 /* c_has_ainit*/, 0 /* c_has_aset*/, 1 /* c_has_ce*/, 0 /* c_has_sclr*/, 0 /* c_has_sinit*/, 0 /* c_has_sset*/, "0" /* c_sinit_val*/, 0 /* c_sync_enable*/, 0 /* c_sync_priority*/, 1 /* c_width*/ ) BU2469( .D(BU2469_D), .Q(BU2469_Q), .CLK(BU2469_CLK), .CE(BU2469_CE) ); wire [0 : 0] BU2473_D; assign BU2473_D[0] = n6403; wire [0 : 0] BU2473_Q; assign n6463 = BU2473_Q[0]; wire BU2473_CLK; assign BU2473_CLK = n659; wire BU2473_CE; assign BU2473_CE = n660; C_REG_FD_V7_0 #( "0" /* c_ainit_val*/, 0 /* c_enable_rlocs*/, 0 /* c_has_aclr*/, 0 /* c_has_ainit*/, 0 /* c_has_aset*/, 1 /* c_has_ce*/, 0 /* c_has_sclr*/, 0 /* c_has_sinit*/, 0 /* c_has_sset*/, "0" /* c_sinit_val*/, 0 /* c_sync_enable*/, 0 /* c_sync_priority*/, 1 /* c_width*/ ) BU2473( .D(BU2473_D), .Q(BU2473_Q), .CLK(BU2473_CLK), .CE(BU2473_CE) ); wire [19 : 0] BU2333_A; assign BU2333_A[0] = n6385; assign BU2333_A[1] = n6386; assign BU2333_A[2] = n6387; assign BU2333_A[3] = n6388; assign BU2333_A[4] = n6389; assign BU2333_A[5] = n6390; assign BU2333_A[6] = n6391; assign BU2333_A[7] = n6392; assign BU2333_A[8] = n6393; assign BU2333_A[9] = n6394; assign BU2333_A[10] = n6395; assign BU2333_A[11] = n6396; assign BU2333_A[12] = n6397; assign BU2333_A[13] = n6398; assign BU2333_A[14] = n6399; assign BU2333_A[15] = n6400; assign BU2333_A[16] = n6401; assign BU2333_A[17] = n6402; assign BU2333_A[18] = n6403; assign BU2333_A[19] = n6404; wire [0 : 0] BU2333_B; assign BU2333_B[0] = n6428; wire [20 : 0] BU2333_Q; assign n6407 = BU2333_Q[0]; assign n6408 = BU2333_Q[1]; assign n6409 = BU2333_Q[2]; assign n6410 = BU2333_Q[3]; assign n6411 = BU2333_Q[4]; assign n6412 = BU2333_Q[5]; assign n6413 = BU2333_Q[6]; assign n6414 = BU2333_Q[7]; assign n6415 = BU2333_Q[8]; assign n6416 = BU2333_Q[9]; assign n6417 = BU2333_Q[10]; assign n6418 = BU2333_Q[11]; assign n6419 = BU2333_Q[12]; assign n6420 = BU2333_Q[13]; assign n6421 = BU2333_Q[14]; assign n6422 = BU2333_Q[15]; assign n6423 = BU2333_Q[16]; assign n6424 = BU2333_Q[17]; assign n6425 = BU2333_Q[18]; assign n6426 = BU2333_Q[19]; wire BU2333_CLK; assign BU2333_CLK = n659; wire BU2333_CE; assign BU2333_CE = n660; C_ADDSUB_V7_0 #( 0 /* c_add_mode*/, "000000000000000000000" /* c_ainit_val*/, 0 /* c_a_type*/, 20 /* c_a_width*/, 0 /* c_bypass_enable*/, 0 /* c_bypass_low*/, 0 /* c_b_constant*/, 1 /* c_b_type*/, "000000000000000000000" /* c_b_value*/, 1 /* c_b_width*/, 0 /* c_enable_rlocs*/, 0 /* c_has_aclr*/, 0 /* c_has_add*/, 0 /* c_has_ainit*/, 0 /* c_has_aset*/, 0 /* c_has_a_signed*/, 0 /* c_has_bypass*/, 0 /* c_has_bypass_with_cin*/, 0 /* c_has_b_in*/, 0 /* c_has_b_out*/, 0 /* c_has_b_signed*/, 1 /* c_has_ce*/, 0 /* c_has_c_in*/, 0 /* c_has_c_out*/, 0 /* c_has_ovfl*/, 1 /* c_has_q*/, 0 /* c_has_q_b_out*/, 0 /* c_has_q_c_out*/, 0 /* c_has_q_ovfl*/, 1 /* c_has_s*/, 0 /* c_has_sclr*/, 0 /* c_has_sinit*/, 0 /* c_has_sset*/, 20 /* c_high_bit*/, 1 /* c_latency*/, 0 /* c_low_bit*/, 21 /* c_out_width*/, 0 /* c_pipe_stages*/, "000000000000000000000" /* c_sinit_val*/, 0 /* c_sync_enable*/, 0 /* c_sync_priority*/ ) BU2333( .A(BU2333_A), .B(BU2333_B), .Q(BU2333_Q), .CLK(BU2333_CLK), .CE(BU2333_CE) ); defparam BU2477.INIT = 'h7340; wire BU2477_I0; assign BU2477_I0 = n6462; wire BU2477_I1; assign BU2477_I1 = n6461; wire BU2477_I2; assign BU2477_I2 = n660; wire BU2477_I3; assign BU2477_I3 = n6465; wire BU2477_O; assign n6464 = BU2477_O; LUT4 BU2477( .I0(BU2477_I0), .I1(BU2477_I1), .I2(BU2477_I2), .I3(BU2477_I3), .O(BU2477_O) ); defparam BU2479.INIT = 'h0200; wire BU2479_I0; assign BU2479_I0 = n6462; wire BU2479_I1; assign BU2479_I1 = n6463; wire BU2479_I2; assign BU2479_I2 = n6426; wire BU2479_I3; assign BU2479_I3 = n660; wire BU2479_O; assign n6465 = BU2479_O; LUT4 BU2479( .I0(BU2479_I0), .I1(BU2479_I1), .I2(BU2479_I2), .I3(BU2479_I3), .O(BU2479_O) ); defparam BU2481.INIT = 'ha040; wire BU2481_I0; assign BU2481_I0 = n6462; wire BU2481_I1; assign BU2481_I1 = n6426; wire BU2481_I2; assign BU2481_I2 = n660; wire BU2481_I3; assign BU2481_I3 = n6461; wire BU2481_O; assign n6467 = BU2481_O; LUT4 BU2481( .I0(BU2481_I0), .I1(BU2481_I1), .I2(BU2481_I2), .I3(BU2481_I3), .O(BU2481_O) ); wire [18 : 0] BU2483_D; assign BU2483_D[0] = n6407; assign BU2483_D[1] = n6408; assign BU2483_D[2] = n6409; assign BU2483_D[3] = n6410; assign BU2483_D[4] = n6411; assign BU2483_D[5] = n6412; assign BU2483_D[6] = n6413; assign BU2483_D[7] = n6414; assign BU2483_D[8] = n6415; assign BU2483_D[9] = n6416; assign BU2483_D[10] = n6417; assign BU2483_D[11] = n6418; assign BU2483_D[12] = n6419; assign BU2483_D[13] = n6420; assign BU2483_D[14] = n6421; assign BU2483_D[15] = n6422; assign BU2483_D[16] = n6423; assign BU2483_D[17] = n6424; assign BU2483_D[18] = n6425; wire [18 : 0] BU2483_Q; assign n580 = BU2483_Q[0]; assign n581 = BU2483_Q[1]; assign n582 = BU2483_Q[2]; assign n583 = BU2483_Q[3]; assign n584 = BU2483_Q[4]; assign n585 = BU2483_Q[5]; assign n586 = BU2483_Q[6]; assign n587 = BU2483_Q[7]; assign n588 = BU2483_Q[8]; assign n589 = BU2483_Q[9]; assign n590 = BU2483_Q[10]; assign n591 = BU2483_Q[11]; assign n592 = BU2483_Q[12]; assign n593 = BU2483_Q[13]; assign n594 = BU2483_Q[14]; assign n595 = BU2483_Q[15]; assign n596 = BU2483_Q[16]; assign n597 = BU2483_Q[17]; assign n598 = BU2483_Q[18]; wire BU2483_CLK; assign BU2483_CLK = n659; wire BU2483_CE; assign BU2483_CE = n660; wire BU2483_SCLR; assign BU2483_SCLR = n6464; wire BU2483_SSET; assign BU2483_SSET = n6467; C_REG_FD_V7_0 #( "0000000000000000000" /* c_ainit_val*/, 0 /* c_enable_rlocs*/, 0 /* c_has_aclr*/, 0 /* c_has_ainit*/, 0 /* c_has_aset*/, 1 /* c_has_ce*/, 1 /* c_has_sclr*/, 0 /* c_has_sinit*/, 1 /* c_has_sset*/, "0000000000000000000" /* c_sinit_val*/, 0 /* c_sync_enable*/, 0 /* c_sync_priority*/, 19 /* c_width*/ ) BU2483( .D(BU2483_D), .Q(BU2483_Q), .CLK(BU2483_CLK), .CE(BU2483_CE), .SCLR(BU2483_SCLR), .SSET(BU2483_SSET) ); wire [0 : 0] BU2564_D; assign BU2564_D[0] = n6426; wire [0 : 0] BU2564_Q; assign n599 = BU2564_Q[0]; wire BU2564_CLK; assign BU2564_CLK = n659; wire BU2564_CE; assign BU2564_CE = n660; wire BU2564_SCLR; assign BU2564_SCLR = n6467; wire BU2564_SSET; assign BU2564_SSET = n6464; C_REG_FD_V7_0 #( "0" /* c_ainit_val*/, 0 /* c_enable_rlocs*/, 0 /* c_has_aclr*/, 0 /* c_has_ainit*/, 0 /* c_has_aset*/, 1 /* c_has_ce*/, 1 /* c_has_sclr*/, 0 /* c_has_sinit*/, 1 /* c_has_sset*/, "0" /* c_sinit_val*/, 0 /* c_sync_enable*/, 0 /* c_sync_priority*/, 1 /* c_width*/ ) BU2564( .D(BU2564_D), .Q(BU2564_Q), .CLK(BU2564_CLK), .CE(BU2564_CE), .SCLR(BU2564_SCLR), .SSET(BU2564_SSET) ); wire [0 : 0] BU2894_D; assign BU2894_D[0] = n7246; wire [0 : 0] BU2894_Q; assign n7214 = BU2894_Q[0]; wire BU2894_CLK; assign BU2894_CLK = n659; wire BU2894_CE; assign BU2894_CE = n660; C_REG_FD_V7_0 #( "0" /* c_ainit_val*/, 0 /* c_enable_rlocs*/, 0 /* c_has_aclr*/, 0 /* c_has_ainit*/, 0 /* c_has_aset*/, 1 /* c_has_ce*/, 0 /* c_has_sclr*/, 0 /* c_has_sinit*/, 0 /* c_has_sset*/, "0" /* c_sinit_val*/, 0 /* c_sync_enable*/, 0 /* c_sync_priority*/, 1 /* c_width*/ ) BU2894( .D(BU2894_D), .Q(BU2894_Q), .CLK(BU2894_CLK), .CE(BU2894_CE) ); defparam BU2898.INIT = 'hc4c4; wire BU2898_I0; assign BU2898_I0 = n7190; wire BU2898_I1; assign BU2898_I1 = n557; wire BU2898_I2; assign BU2898_I2 = n7231; wire BU2898_I3; assign BU2898_I3 = 1'b0; wire BU2898_O; assign n7246 = BU2898_O; LUT4 BU2898( .I0(BU2898_I0), .I1(BU2898_I1), .I2(BU2898_I2), .I3(BU2898_I3), .O(BU2898_O) ); wire [13 : 0] BU2875_I; assign BU2875_I[0] = n543; assign BU2875_I[1] = n544; assign BU2875_I[2] = n545; assign BU2875_I[3] = n546; assign BU2875_I[4] = n547; assign BU2875_I[5] = n548; assign BU2875_I[6] = n549; assign BU2875_I[7] = n550; assign BU2875_I[8] = n551; assign BU2875_I[9] = n552; assign BU2875_I[10] = n553; assign BU2875_I[11] = n554; assign BU2875_I[12] = n555; assign BU2875_I[13] = n556; wire BU2875_T; assign BU2875_T = 1'b0; wire BU2875_EN; assign BU2875_EN = 1'b0; wire BU2875_Q; wire BU2875_CLK; assign BU2875_CLK = 1'b0; wire BU2875_CE; assign BU2875_CE = 1'b0; wire BU2875_ACLR; assign BU2875_ACLR = 1'b0; wire BU2875_ASET; assign BU2875_ASET = 1'b0; wire BU2875_AINIT; assign BU2875_AINIT = 1'b0; wire BU2875_SCLR; assign BU2875_SCLR = 1'b0; wire BU2875_SSET; assign BU2875_SSET = 1'b0; wire BU2875_SINIT; assign BU2875_SINIT = 1'b0; wire BU2875_O; assign n7231 = BU2875_O; C_GATE_BIT_V7_0 #( "0" /* c_ainit_val*/, 0 /* c_enable_rlocs*/, 2 /* c_gate_type*/, 0 /* c_has_aclr*/, 0 /* c_has_ainit*/, 0 /* c_has_aset*/, 0 /* c_has_ce*/, 1 /* c_has_o*/, 1 /* c_has_q*/, 0 /* c_has_sclr*/, 0 /* c_has_sinit*/, 0 /* c_has_sset*/, 14 /* c_inputs*/, "000000000000000" /* c_input_inv_mask*/, 0 /* c_pipe_stages*/, "0" /* c_sinit_val*/, 0 /* c_sync_enable*/, 1 /* c_sync_priority*/ ) BU2875( .I(BU2875_I), .T(BU2875_T), .EN(BU2875_EN), .Q(BU2875_Q), .CLK(BU2875_CLK), .CE(BU2875_CE), .ACLR(BU2875_ACLR), .ASET(BU2875_ASET), .AINIT(BU2875_AINIT), .SCLR(BU2875_SCLR), .SSET(BU2875_SSET), .SINIT(BU2875_SINIT), .O(BU2875_O) ); wire [19 : 0] BU2834_D; assign BU2834_D[0] = n558; assign BU2834_D[1] = n559; assign BU2834_D[2] = n560; assign BU2834_D[3] = n561; assign BU2834_D[4] = n562; assign BU2834_D[5] = n563; assign BU2834_D[6] = n564; assign BU2834_D[7] = n565; assign BU2834_D[8] = n566; assign BU2834_D[9] = n567; assign BU2834_D[10] = n568; assign BU2834_D[11] = n569; assign BU2834_D[12] = n570; assign BU2834_D[13] = n571; assign BU2834_D[14] = n572; assign BU2834_D[15] = n573; assign BU2834_D[16] = n574; assign BU2834_D[17] = n575; assign BU2834_D[18] = n576; assign BU2834_D[19] = n577; wire [19 : 0] BU2834_Q; assign n7171 = BU2834_Q[0]; assign n7172 = BU2834_Q[1]; assign n7173 = BU2834_Q[2]; assign n7174 = BU2834_Q[3]; assign n7175 = BU2834_Q[4]; assign n7176 = BU2834_Q[5]; assign n7177 = BU2834_Q[6]; assign n7178 = BU2834_Q[7]; assign n7179 = BU2834_Q[8]; assign n7180 = BU2834_Q[9]; assign n7181 = BU2834_Q[10]; assign n7182 = BU2834_Q[11]; assign n7183 = BU2834_Q[12]; assign n7184 = BU2834_Q[13]; assign n7185 = BU2834_Q[14]; assign n7186 = BU2834_Q[15]; assign n7187 = BU2834_Q[16]; assign n7188 = BU2834_Q[17]; assign n7189 = BU2834_Q[18]; assign n7190 = BU2834_Q[19]; wire BU2834_CLK; assign BU2834_CLK = n659; wire BU2834_CE; assign BU2834_CE = n660; C_REG_FD_V7_0 #( "00000000000000000000" /* c_ainit_val*/, 0 /* c_enable_rlocs*/, 0 /* c_has_aclr*/, 0 /* c_has_ainit*/, 0 /* c_has_aset*/, 1 /* c_has_ce*/, 0 /* c_has_sclr*/, 0 /* c_has_sinit*/, 0 /* c_has_sset*/, "00000000000000000000" /* c_sinit_val*/, 0 /* c_sync_enable*/, 0 /* c_sync_priority*/, 20 /* c_width*/ ) BU2834( .D(BU2834_D), .Q(BU2834_Q), .CLK(BU2834_CLK), .CE(BU2834_CE) ); wire BU3029_CLK; assign BU3029_CLK = n659; wire [0 : 0] BU3029_D; assign BU3029_D[0] = n579; wire [0 : 0] BU3029_Q; assign n7247 = BU3029_Q[0]; wire BU3029_CE; assign BU3029_CE = n660; C_SHIFT_RAM_V7_0 #( 1 /* c_addr_width*/, "0" /* c_ainit_val*/, "0" /* c_default_data*/, 2 /* c_default_data_radix*/, 2 /* c_depth*/, 0 /* c_enable_rlocs*/, 0 /* c_generate_mif*/, 0 /* c_has_a*/, 0 /* c_has_aclr*/, 0 /* c_has_ainit*/, 0 /* c_has_aset*/, 1 /* c_has_ce*/, 0 /* c_has_sclr*/, 0 /* c_has_sinit*/, 0 /* c_has_sset*/, "null" /* c_mem_init_file*/, 2 /* c_mem_init_radix*/, 0 /* c_read_mif*/, 1 /* c_reg_last_bit*/, 0 /* c_shift_type*/, "0" /* c_sinit_val*/, 0 /* c_sync_enable*/, 0 /* c_sync_priority*/, 1 /* c_width*/ ) BU3029( .CLK(BU3029_CLK), .D(BU3029_D), .Q(BU3029_Q), .CE(BU3029_CE) ); wire [0 : 0] BU3037_D; assign BU3037_D[0] = n7190; wire [0 : 0] BU3037_Q; assign n7248 = BU3037_Q[0]; wire BU3037_CLK; assign BU3037_CLK = n659; wire BU3037_CE; assign BU3037_CE = n660; C_REG_FD_V7_0 #( "0" /* c_ainit_val*/, 0 /* c_enable_rlocs*/, 0 /* c_has_aclr*/, 0 /* c_has_ainit*/, 0 /* c_has_aset*/, 1 /* c_has_ce*/, 0 /* c_has_sclr*/, 0 /* c_has_sinit*/, 0 /* c_has_sset*/, "0" /* c_sinit_val*/, 0 /* c_sync_enable*/, 0 /* c_sync_priority*/, 1 /* c_width*/ ) BU3037( .D(BU3037_D), .Q(BU3037_Q), .CLK(BU3037_CLK), .CE(BU3037_CE) ); wire [0 : 0] BU3041_D; assign BU3041_D[0] = n7189; wire [0 : 0] BU3041_Q; assign n7249 = BU3041_Q[0]; wire BU3041_CLK; assign BU3041_CLK = n659; wire BU3041_CE; assign BU3041_CE = n660; C_REG_FD_V7_0 #( "0" /* c_ainit_val*/, 0 /* c_enable_rlocs*/, 0 /* c_has_aclr*/, 0 /* c_has_ainit*/, 0 /* c_has_aset*/, 1 /* c_has_ce*/, 0 /* c_has_sclr*/, 0 /* c_has_sinit*/, 0 /* c_has_sset*/, "0" /* c_sinit_val*/, 0 /* c_sync_enable*/, 0 /* c_sync_priority*/, 1 /* c_width*/ ) BU3041( .D(BU3041_D), .Q(BU3041_Q), .CLK(BU3041_CLK), .CE(BU3041_CE) ); wire [19 : 0] BU2901_A; assign BU2901_A[0] = n7171; assign BU2901_A[1] = n7172; assign BU2901_A[2] = n7173; assign BU2901_A[3] = n7174; assign BU2901_A[4] = n7175; assign BU2901_A[5] = n7176; assign BU2901_A[6] = n7177; assign BU2901_A[7] = n7178; assign BU2901_A[8] = n7179; assign BU2901_A[9] = n7180; assign BU2901_A[10] = n7181; assign BU2901_A[11] = n7182; assign BU2901_A[12] = n7183; assign BU2901_A[13] = n7184; assign BU2901_A[14] = n7185; assign BU2901_A[15] = n7186; assign BU2901_A[16] = n7187; assign BU2901_A[17] = n7188; assign BU2901_A[18] = n7189; assign BU2901_A[19] = n7190; wire [0 : 0] BU2901_B; assign BU2901_B[0] = n7214; wire [20 : 0] BU2901_Q; assign n7193 = BU2901_Q[0]; assign n7194 = BU2901_Q[1]; assign n7195 = BU2901_Q[2]; assign n7196 = BU2901_Q[3]; assign n7197 = BU2901_Q[4]; assign n7198 = BU2901_Q[5]; assign n7199 = BU2901_Q[6]; assign n7200 = BU2901_Q[7]; assign n7201 = BU2901_Q[8]; assign n7202 = BU2901_Q[9]; assign n7203 = BU2901_Q[10]; assign n7204 = BU2901_Q[11]; assign n7205 = BU2901_Q[12]; assign n7206 = BU2901_Q[13]; assign n7207 = BU2901_Q[14]; assign n7208 = BU2901_Q[15]; assign n7209 = BU2901_Q[16]; assign n7210 = BU2901_Q[17]; assign n7211 = BU2901_Q[18]; assign n7212 = BU2901_Q[19]; wire BU2901_CLK; assign BU2901_CLK = n659; wire BU2901_CE; assign BU2901_CE = n660; C_ADDSUB_V7_0 #( 0 /* c_add_mode*/, "000000000000000000000" /* c_ainit_val*/, 0 /* c_a_type*/, 20 /* c_a_width*/, 0 /* c_bypass_enable*/, 0 /* c_bypass_low*/, 0 /* c_b_constant*/, 1 /* c_b_type*/, "000000000000000000000" /* c_b_value*/, 1 /* c_b_width*/, 0 /* c_enable_rlocs*/, 0 /* c_has_aclr*/, 0 /* c_has_add*/, 0 /* c_has_ainit*/, 0 /* c_has_aset*/, 0 /* c_has_a_signed*/, 0 /* c_has_bypass*/, 0 /* c_has_bypass_with_cin*/, 0 /* c_has_b_in*/, 0 /* c_has_b_out*/, 0 /* c_has_b_signed*/, 1 /* c_has_ce*/, 0 /* c_has_c_in*/, 0 /* c_has_c_out*/, 0 /* c_has_ovfl*/, 1 /* c_has_q*/, 0 /* c_has_q_b_out*/, 0 /* c_has_q_c_out*/, 0 /* c_has_q_ovfl*/, 1 /* c_has_s*/, 0 /* c_has_sclr*/, 0 /* c_has_sinit*/, 0 /* c_has_sset*/, 20 /* c_high_bit*/, 1 /* c_latency*/, 0 /* c_low_bit*/, 21 /* c_out_width*/, 0 /* c_pipe_stages*/, "000000000000000000000" /* c_sinit_val*/, 0 /* c_sync_enable*/, 0 /* c_sync_priority*/ ) BU2901( .A(BU2901_A), .B(BU2901_B), .Q(BU2901_Q), .CLK(BU2901_CLK), .CE(BU2901_CE) ); defparam BU3045.INIT = 'h7340; wire BU3045_I0; assign BU3045_I0 = n7248; wire BU3045_I1; assign BU3045_I1 = n7247; wire BU3045_I2; assign BU3045_I2 = n660; wire BU3045_I3; assign BU3045_I3 = n7251; wire BU3045_O; assign n7250 = BU3045_O; LUT4 BU3045( .I0(BU3045_I0), .I1(BU3045_I1), .I2(BU3045_I2), .I3(BU3045_I3), .O(BU3045_O) ); defparam BU3047.INIT = 'h0200; wire BU3047_I0; assign BU3047_I0 = n7248; wire BU3047_I1; assign BU3047_I1 = n7249; wire BU3047_I2; assign BU3047_I2 = n7212; wire BU3047_I3; assign BU3047_I3 = n660; wire BU3047_O; assign n7251 = BU3047_O; LUT4 BU3047( .I0(BU3047_I0), .I1(BU3047_I1), .I2(BU3047_I2), .I3(BU3047_I3), .O(BU3047_O) ); defparam BU3049.INIT = 'ha040; wire BU3049_I0; assign BU3049_I0 = n7248; wire BU3049_I1; assign BU3049_I1 = n7212; wire BU3049_I2; assign BU3049_I2 = n660; wire BU3049_I3; assign BU3049_I3 = n7247; wire BU3049_O; assign n7253 = BU3049_O; LUT4 BU3049( .I0(BU3049_I0), .I1(BU3049_I1), .I2(BU3049_I2), .I3(BU3049_I3), .O(BU3049_O) ); wire [18 : 0] BU3051_D; assign BU3051_D[0] = n7193; assign BU3051_D[1] = n7194; assign BU3051_D[2] = n7195; assign BU3051_D[3] = n7196; assign BU3051_D[4] = n7197; assign BU3051_D[5] = n7198; assign BU3051_D[6] = n7199; assign BU3051_D[7] = n7200; assign BU3051_D[8] = n7201; assign BU3051_D[9] = n7202; assign BU3051_D[10] = n7203; assign BU3051_D[11] = n7204; assign BU3051_D[12] = n7205; assign BU3051_D[13] = n7206; assign BU3051_D[14] = n7207; assign BU3051_D[15] = n7208; assign BU3051_D[16] = n7209; assign BU3051_D[17] = n7210; assign BU3051_D[18] = n7211; wire [18 : 0] BU3051_Q; assign n600 = BU3051_Q[0]; assign n601 = BU3051_Q[1]; assign n602 = BU3051_Q[2]; assign n603 = BU3051_Q[3]; assign n604 = BU3051_Q[4]; assign n605 = BU3051_Q[5]; assign n606 = BU3051_Q[6]; assign n607 = BU3051_Q[7]; assign n608 = BU3051_Q[8]; assign n609 = BU3051_Q[9]; assign n610 = BU3051_Q[10]; assign n611 = BU3051_Q[11]; assign n612 = BU3051_Q[12]; assign n613 = BU3051_Q[13]; assign n614 = BU3051_Q[14]; assign n615 = BU3051_Q[15]; assign n616 = BU3051_Q[16]; assign n617 = BU3051_Q[17]; assign n618 = BU3051_Q[18]; wire BU3051_CLK; assign BU3051_CLK = n659; wire BU3051_CE; assign BU3051_CE = n660; wire BU3051_SCLR; assign BU3051_SCLR = n7250; wire BU3051_SSET; assign BU3051_SSET = n7253; C_REG_FD_V7_0 #( "0000000000000000000" /* c_ainit_val*/, 0 /* c_enable_rlocs*/, 0 /* c_has_aclr*/, 0 /* c_has_ainit*/, 0 /* c_has_aset*/, 1 /* c_has_ce*/, 1 /* c_has_sclr*/, 0 /* c_has_sinit*/, 1 /* c_has_sset*/, "0000000000000000000" /* c_sinit_val*/, 0 /* c_sync_enable*/, 0 /* c_sync_priority*/, 19 /* c_width*/ ) BU3051( .D(BU3051_D), .Q(BU3051_Q), .CLK(BU3051_CLK), .CE(BU3051_CE), .SCLR(BU3051_SCLR), .SSET(BU3051_SSET) ); wire [0 : 0] BU3132_D; assign BU3132_D[0] = n7212; wire [0 : 0] BU3132_Q; assign n619 = BU3132_Q[0]; wire BU3132_CLK; assign BU3132_CLK = n659; wire BU3132_CE; assign BU3132_CE = n660; wire BU3132_SCLR; assign BU3132_SCLR = n7253; wire BU3132_SSET; assign BU3132_SSET = n7250; C_REG_FD_V7_0 #( "0" /* c_ainit_val*/, 0 /* c_enable_rlocs*/, 0 /* c_has_aclr*/, 0 /* c_has_ainit*/, 0 /* c_has_aset*/, 1 /* c_has_ce*/, 1 /* c_has_sclr*/, 0 /* c_has_sinit*/, 1 /* c_has_sset*/, "0" /* c_sinit_val*/, 0 /* c_sync_enable*/, 0 /* c_sync_priority*/, 1 /* c_width*/ ) BU3132( .D(BU3132_D), .Q(BU3132_Q), .CLK(BU3132_CLK), .CE(BU3132_CE), .SCLR(BU3132_SCLR), .SSET(BU3132_SSET) ); wire [19 : 0] BU2573_D; assign BU2573_D[0] = n580; assign BU2573_D[1] = n581; assign BU2573_D[2] = n582; assign BU2573_D[3] = n583; assign BU2573_D[4] = n584; assign BU2573_D[5] = n585; assign BU2573_D[6] = n586; assign BU2573_D[7] = n587; assign BU2573_D[8] = n588; assign BU2573_D[9] = n589; assign BU2573_D[10] = n590; assign BU2573_D[11] = n591; assign BU2573_D[12] = n592; assign BU2573_D[13] = n593; assign BU2573_D[14] = n594; assign BU2573_D[15] = n595; assign BU2573_D[16] = n596; assign BU2573_D[17] = n597; assign BU2573_D[18] = n598; assign BU2573_D[19] = n599; wire [19 : 0] BU2573_Q; assign n662 = BU2573_Q[0]; assign n663 = BU2573_Q[1]; assign n664 = BU2573_Q[2]; assign n665 = BU2573_Q[3]; assign n666 = BU2573_Q[4]; assign n667 = BU2573_Q[5]; assign n668 = BU2573_Q[6]; assign n669 = BU2573_Q[7]; assign n670 = BU2573_Q[8]; assign n671 = BU2573_Q[9]; assign n672 = BU2573_Q[10]; assign n673 = BU2573_Q[11]; assign n674 = BU2573_Q[12]; assign n675 = BU2573_Q[13]; assign n676 = BU2573_Q[14]; assign n677 = BU2573_Q[15]; assign n678 = BU2573_Q[16]; assign n679 = BU2573_Q[17]; assign n680 = BU2573_Q[18]; assign n681 = BU2573_Q[19]; wire BU2573_CLK; assign BU2573_CLK = n659; wire BU2573_CE; assign BU2573_CE = n331; C_REG_FD_V7_0 #( "00000000000000000000" /* c_ainit_val*/, 0 /* c_enable_rlocs*/, 0 /* c_has_aclr*/, 0 /* c_has_ainit*/, 0 /* c_has_aset*/, 1 /* c_has_ce*/, 0 /* c_has_sclr*/, 0 /* c_has_sinit*/, 0 /* c_has_sset*/, "00000000000000000000" /* c_sinit_val*/, 0 /* c_sync_enable*/, 0 /* c_sync_priority*/, 20 /* c_width*/ ) BU2573( .D(BU2573_D), .Q(BU2573_Q), .CLK(BU2573_CLK), .CE(BU2573_CE) ); wire [19 : 0] BU3141_D; assign BU3141_D[0] = n600; assign BU3141_D[1] = n601; assign BU3141_D[2] = n602; assign BU3141_D[3] = n603; assign BU3141_D[4] = n604; assign BU3141_D[5] = n605; assign BU3141_D[6] = n606; assign BU3141_D[7] = n607; assign BU3141_D[8] = n608; assign BU3141_D[9] = n609; assign BU3141_D[10] = n610; assign BU3141_D[11] = n611; assign BU3141_D[12] = n612; assign BU3141_D[13] = n613; assign BU3141_D[14] = n614; assign BU3141_D[15] = n615; assign BU3141_D[16] = n616; assign BU3141_D[17] = n617; assign BU3141_D[18] = n618; assign BU3141_D[19] = n619; wire [19 : 0] BU3141_Q; assign n682 = BU3141_Q[0]; assign n683 = BU3141_Q[1]; assign n684 = BU3141_Q[2]; assign n685 = BU3141_Q[3]; assign n686 = BU3141_Q[4]; assign n687 = BU3141_Q[5]; assign n688 = BU3141_Q[6]; assign n689 = BU3141_Q[7]; assign n690 = BU3141_Q[8]; assign n691 = BU3141_Q[9]; assign n692 = BU3141_Q[10]; assign n693 = BU3141_Q[11]; assign n694 = BU3141_Q[12]; assign n695 = BU3141_Q[13]; assign n696 = BU3141_Q[14]; assign n697 = BU3141_Q[15]; assign n698 = BU3141_Q[16]; assign n699 = BU3141_Q[17]; assign n700 = BU3141_Q[18]; assign n701 = BU3141_Q[19]; wire BU3141_CLK; assign BU3141_CLK = n659; wire BU3141_CE; assign BU3141_CE = n331; C_REG_FD_V7_0 #( "00000000000000000000" /* c_ainit_val*/, 0 /* c_enable_rlocs*/, 0 /* c_has_aclr*/, 0 /* c_has_ainit*/, 0 /* c_has_aset*/, 1 /* c_has_ce*/, 0 /* c_has_sclr*/, 0 /* c_has_sinit*/, 0 /* c_has_sset*/, "00000000000000000000" /* c_sinit_val*/, 0 /* c_sync_enable*/, 0 /* c_sync_priority*/, 20 /* c_width*/ ) BU3141( .D(BU3141_D), .Q(BU3141_Q), .CLK(BU3141_CLK), .CE(BU3141_CE) ); //synopsys translate_on endmodule