Problem 1. Consider the following diagram of a simple sequential circuit:

The components labeled CL1 and CL2 are combinational; R1 and R2 are D-registers. Timing parameters for each component are as noted.

Write the timing specifications (tS, tH, tCD, tPD, tCLK) for the system as a whole using the timing specifications for the internal components that are given in the figure.

Suppose you had available a faster version of CL2 having a propagation delay of 3 and a contamination delay of zero. Could you substitute the faster CL2 for the one shown in the diagram? Explain.

We've been treating wires as idealized components that introduce no delay of their own. In the real world, wires have resistance, capacitance and inductance that will cause different frequencies to propagate along the wire at different rates. This means that wires will delay the arrival of sharp rising and falling transitions (which you'll remember from Fourier analysis have signal components at many different frequencies). This effect is particularly bothersome in connection with clock signals since the clock may arrive at separate parts of the circuit at slightly different times. This difference in arrival times of the clock is called clock skew, which we'll model in our simple circuit above as explicit delays along each clock path:

Rewrite the timing specifications for the system as a whole taking into account d1 and d2. Don't make any assumption about the relative sizes of the two delays.

The relative clock skew (d2 - d1) between two registers connected in a "pipeline" - where the output of the first register is connected, usually through logic, to the input of the second register - can also affect the design of a circuit. Explain how relative clock skew affects the maximum clock frequency of the circuit shown above. Remember that the relative skew might be positive or negative.

[Why clock skew keeps integrated circuit designers awake at night.] If d2 > d1, the circuit shown above will not operate correctly. Explain why. Will changing the frequency of CLK solve the problem? Why or why not?

Suggest a way for the designer to change his circuit to guarantee correct operation given an upper bound, tskew > abs(d2 - d1), on the maximum relative clock skew. Assume that the timing parameters of the registers cannot be adjusted.

Problem 2. Consider the following circuit diagram: S0 and S1:

What is the smallest clock period for which the circuit still operates correctly?

A sharp-eyed student suggests optimizing the circuit by removing the pair of inverters and connecting the Q output of the left register directly to the D input of the right register. If the clock period could be adjusted appropriately, would the optimized circuit operate correctly? If yes, explain the adjustment to the clock period that would be needed.

When the RESET signal is set to "1" for several cycles, what values are loaded into the registers? (Give values for S0 and S1.)

Assuming the RESET signal has been set to "0" and will stay that way, what value will with the registers have after the next clock edge assuming the current values are S0=1 and S1=1?

Now suppose there is skew in the CLK signal such that the rising edge of CLK always arrives at the left register exactly 1ns before it arrives at the right register. What is the smallest clock period for which the FSM still operates correctly?

Problem 3. A possible implementation of a sequential circuit with one input and one output is shown below.

What is the smallest value for the ROM's contamination delay that ensures the necessary timing specifications are met?

Assume that the ROM's tCD = 3ns. What is the smallest clock period that ensures that the necessary timing specifications are met.

Problem 4. The following schematic has two D-registers and two blocks of combinational logic with the indicated timing specifications. Assume that the registers and that the clock has zero rise and fall time.

Assuming that the clock period is 25ns, what is the maximum setup time for the registers for which this circuit will operate correctly?

Assuming that the clock period is 25ns, what is the maximum hold time for the registers for which this circuit will operate correctly?

Problem 5. Use the following circuit in answering the questions below.

Each of the edge-triggered D flip-flops has a setup time of tS, a hold time of tH, a propagation delay of tPD and a contamination delay of tCD. Assume that IN is stable tS before the rising edge of CLK and tH after the rising edge of CLK.

In order for the circuit shown above to operate correctly what constraints on tH and tS are necessary? Express them in terms of tCD, tPD and the clock period.

What is the minimum clock period at which this circuit can be clocked and still be guaranteed to work? Express your answer in terms of tH, tS, tCD and tPD. Assume that timing constraints that do not depend on the clock period are met.

For just this question suppose there is skew in the CLK signal such that the rising edge of CLK arrives at the flip-flop labeled F1 1ns before it arrives at the other three flip-flops. Assume that hold times are not violated. How does this change the minimum clock period at which the circuit above can be clocked and still be guaranteed to work?

Consider the following waveform plot for the circuit above. Assume that IN is stable tS before the rising edge of CLK and tH after the rising edge of CLK and that time T is more than tPD after the preceding rising edge of CLK.

What is the value of OUT at time T?

Problem 6. Consider the following two waveforms, one of which has 1/6th the frequency of the other.

Write a Verilog module that takes the top waveform as an input and produces the bottom waveform as an output.

Problem 7. The figure below shows a 4-bit synchronous binary counter:

I/O	Description
D[3:0]	4-bit data input
LD	when LD is asserted, load D[3:0] into the counter at the next rising edge of CLK
EN	when EN is asserted, the counter increments by one at the next rising edge of CLK. If LD is asserted, the load takes precedence.
CLK	clock input
Q[3:0]	4-bit counter output

Write a Verilog module that implements the 4-bit synchronous binary counter.

Add an asynchronous clear input, CLR, to your Verilog module. When asserted it should immediately (not waiting until the next clock edge) set the counter to 0.

Problem 8. The figure and truth table below describe a positive-edge triggered J-K flip-flop with active-low asynchronous preset and clear.

Inputs					Outputs
preset	clear	clk	J	K	Q	Qbar
0	X	X	X	X	1	0
1	0	X	X	X	0	1
1	1	no edge	X	X	Q	Qbar
1	1		0	0	Q	Qbar
1	1		1	0	1	0
1	1		0	1	0	1
1	1		1	1	toggle

Write a Verilog module that implements the J-K flip-flop described above.

Sequential Logic