A B C | F ========|=== 0 0 0 | 1 0 0 1 | 0 0 1 0 | 0 0 1 1 | 1 1 0 0 | 1 1 0 1 | 1 1 1 0 | 0 1 1 1 | 1
_ _ _ _ _ _ _ F = A*B*C + A*B*C + A*B*C + A*B*C + A*B*C
_ _ _ F = B*C + A*B + B*COne possible schematic diagram is shown below. Note that the final 3-input NAND gate has been drawn in it's Demorganized form, i.e., an OR gate with inverting inputs.
_ _ _ F = B*C + A*B*C
_____ (A) A + B _ _ _ _ _ _ _ (B) A*B*C + A*B*C + A*B*C + A*B*C + A*B*C + A*B*C
_ _ (A) A*B (B) B + C
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ F = (C + D)*(A + B*C) = A*C + A*D + B*C + B*C*D = A*C + A*D + B*C
_ top term is pulled down when A = 1 => product term is A _ _ _ bottom term is pulled down when A or B or C is 1 => product term is A*B*CThe rightmost column is just a distributed 2-input NOR gate that combines the product terms, and the final inverter converts this into a OR of the product terms. So:
_ H = A + A*B*C = A + B*C
_ _ _ top term is pulled down when A or B or C = 1 => product term is A*B*C _ _ _ next term is pulled down when A or B or C is 1 => product term is A*B*C ...So, for a particular set of input values only one of these products will be true.
_ _ _ _ _ Z = A*B*C + A*B*C + A*B*C + A*B*C + A*B*C
_ _ _ term 1: A*C term 2: B*C term 3: A*B term 4: A*BG is simply the OR of terms 1 and 3. With a little thought we can rewrite F as:
_ _ _ _ _ F = A + C = A + A*C = A(B + B) + A*C = A*B + A*B + A*Cwhich is the OR of terms 1, 3 and 4. We can now fill in the necessary pulldowns:
_ _ _ G = A*C + A*C + B
____ __ Gn = Gn+1 + Ln+1*An*Bn ____ __ Ln = Ln+1 + Gn+1*An*BnIf we construct a schematic using INV, AND and OR, the resulting circuit would have a Tpd of 3 gate delays.
____ ____ ____ ____ __ Gn = Gn+2 + Ln+2*(An+1*Bn+1 + (An+1*Bn+1 + An+1*Bn+1)*An*Bn) ____ ____ ____ ____ __ Ln = Ln+2 + Gn+2*(An+1*Bn+1 + (An+1*Bn+1 + An+1*Bn+1)*An*Bn)