6.111 Lab #2

Goal: implement simple circuits in Verilog; download and run a sample circuit on the labkit.

Useful links

Exercise 1: Writing Verilog code

In this exercise you'll design a Verilog module that implements a 74LS163. Here are the steps:

  1. Log into one of the workstations in the Digital Lab. Your username is your Athena login name and your initial password is "changeme".

  2. Download lab2_1.v by right-clicking on the link and select "Save As" (or "Save Link As"), specify your home directory (U:) as the destination.

The steps below describe how to use our Verilog simulator Modelsim as a standalone application. One can also run the simulator from the Xilinx ISE toolkit -- see the labkit documentation Simulating with Modelsim for details on how to do this. Feel free to use either approach for this part of the lab.

  1. Start Modelsim (look in the Programs listing under the Start menu). If it complains about a missing license file, go to Start -> Programs -> Modelsim -> Licensing Wizard. Click the Continue button and specify 27000@mtlcad.mit.edu as the location of the licensing file. If it offers to add the appropriate environment variable, let it! The wizard will complete, click OK when it's done. Now restart Modelsim and everything should be happy.

  2. At the bottom of the Modelsim window there's a frame labeled "Transcript" where you can type in commands and see various messages from the simulator. Type in "cd u:" to change to your home directory.

  3. Type "vlib work" to set up the simulator's working library

  4. Type "vlog lab2_1.v" to compile the verilog file you downloaded above. Output from the compiler is displayed in the transcript window.

  5. Type "vsim test" to start simulating the test module found in lab2_1.v.

  6. Type "run 2000ns" to run the simulation for 2000ns. You should see the following printout in the Transcript window
         # Starting test of LS163...
         # clear was asserted low, but counter didn't clear
         # out = xxxx, expected 0000
         # Break at lab2_1.v line 48

    These messages were generated by code inside the test module as it runs through various tests of the LS163 module. The LS163 module supplied in lab2_1.v is empty which is why the test failed. Your job is to fill in the body for the LS163 module, implementing the correct functionality. Refer to the 74LS163 datasheet to see what functionality your code needs to implement.

    You can use the editor of your choice to edit lab2_1.v appropriately; Modelsim has a simple built-in editor which should be displaying lab2_1.v after you completed step 8. As you edit lab2_1.v, repeat steps 6 through 8 above to test your code. When you're successful you'll see

         # Starting test of LS163...
         # Finished test of LS163...

  7. When your code passes the tests, have a staff member check you off. They may ask a simple question or two, but mostly they just want to see it working under Modelsim.

  8. After checkoff, please upload your Verilog file using the "Submit Verilog" page on the course website. We'll review your code and post some comments to help you improve your Verilog style. We'll be looking for proper use of comments and formatting to make your code easy to understand.

Exercise 2: Compiling and running Verilog on the labkit

In this exercise you'll design a Verilog module that reads a 4-bit value from labkit's switches and displays the appropriate hex digit on a 7-segment display.

  1. To learn more about the Xilinx FPGA tools please read the Getting Started section of the Labkit documentation. You'll follow the steps outlined there whenever creating a new project for the labkit.

  2. Download labkit.v and labkit.ucf by right-clicking on the links and selecting "Save As" (or "Save Link As"), specify your home directory (U:) as the destination. Note that the browser may save your downloads with a ".txt" extension -- you'll have to rename the files to have ".v" and ".ucf" extensions in order for the Xilinx tools to recognize them correctly.

    The labkit module (defined in labkit.v) has port declarations for all the labkit peripherals as well as supplying default values for all the output ports. This is the top-level module for all labkit projects -- you should make a copy of it using a meaningful file name (eg, lab2_2.v) and modify the copy to implement the circuitry for your project. labkit.ucf (which you'll never need to modify) specifies which FPGA pin is connected to which named port in labkit.v.

  3. Start the Xilinx ISE tool and create a new project following the steps outlined in the Getting Started document. The Xilinx tools create a very large number of files, so to keep things neat and tidy I recommend keeping your .v files separate from the project directory. For example, if you keep your .v files in U:, specify U: as the location for your project directories, and when you supply a name for the project (eg, lab2_2) a directory of that name will be created in U: and used to store all the Xilinx-created files. When you add verilog source files to the project, just go up one directory level to locate your source files.

  4. We'll be using the 7-segment display from your kit of parts (this is the display you used in Exercise 6 of Lab 1), this time wired to the FPGA via the labkit's breadboard (see photo below). Wire up the display connecting its ground pins to the appropriate columns of the breadboard, and the signal pins to the User 1 connector at the top of the labkit (I used pins 0 through 7).

  5. Add Verilog code to the labkit module using four of the labkit's slide switches to specify which hex digit to display on a 7-segment display. The switch port of the labkit module is an 8-bit value reflecting the current settings of the labkit's slide switches. Use switch[3:0] as the 4-bit hex digit to be displayed. Here's the appropriate pattern of segments for each digit:

    Compute the appropriate value for each of segment control signals and drive them onto the appropriate FPGA output pins (I used user1[7:0]). Note that you'll have modify or comment-out the existing line in the code that sets a default value for the output pins you're using.

    Synthesize and implement your design. Generate a programming file and configure the FPGA. When your circuit is working, ask a staff member to check you off. For checkoff be prepared to show your circuit in operation, displaying different digits as the switches are turned on and off.

  6. After checkoff, please upload your Verilog file using the "Submit Verilog" page on the course website. We'll review your code and post some comments to help you improve your Verilog style.