Week of |
Tue |
Thu |
Sep 07 |
Registration Day |
L01: Course overview. Digital abstraction, static discipline, logic families
|
Sep 14 |
L02: Combinational logic, canonical representations, simplification and synthesis
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L03: Verilog hardware description languge. FPGA architectures
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Sep 21 |
L04: Sequential building blocks, state and feedback, registers
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L05: Finite state machines, Verilog implementation examples
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Sep 28 |
L06: CI-M requirements. Clocking, synchronization and metastability
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L07: Memories: on-chip, SRAM, DRAM, Flash
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Oct 5 |
L08: Number representations, adders, improving latency
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L09: Multipliers, behavioral transformations
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Oct 12 |
No lecture Monday schedule
|
L10: Analog building blocks (opamps, DACs, ADCs), sampling, reconstruction, filtering.
|
Oct 19 |
L11: Project kickoff
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L12: Case study: video circuits
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Oct 26 |
L13: Datapaths and control logic, microsequencers, programmable components
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L14: Case study: communication links
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Nov 02 |
Project Abstract due
|
Writing workshop (attendance required)
Project Proposal Meeting before 11/6 @ 5pm |
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Nov 09 |
Project Block Diagram Meeting before 11/13 @ 5pm
Lab #3 Revised Report due 11/13 @ 5pm |
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Nov 16 |
Project Design Presentations (Tue/Thu during class time)
Project Checklist due 11/20 @ 5p
|
Nov 23 |
|
Thanksgiving |
Nov 30 |
|
Dec 07 |
Project Demos and videotaping (Wed, Thu)
Project Report due 12/10 @ 5pm
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