| Week of |
Tue |
Thu |
| Sep 02 |
Registration Day |
L01: Course overview. Digital abstraction, static discipline, logic families
|
| Sep 09 |
L02: Combinational logic, canonical representations, simplification and synthesis
|
L03: Verilog hardware description languge. FPGA architectures
|
| Sep 16 |
L04: Sequential building blocks, state and feedback, registers
|
L05: Finite state machines, Verilog implementation examples
|
| Sep 23 |
L06: Case study: video circuits
|
L07: System Integration, Clocking, number encoding
| Lab #3 finish Part 1 - no checkoff needed |
|
| Sep 30 |
L08: Arithmetic circuits, adder, multipliers
|
L09: Behavioral transformations, FPGA
|
| Oct 07 |
L10: Memories: on-chip, SRAM, DRAM, Flash
|
L11: Project kickoff and writing workshop: proposals and presentations (attendance required)
|
| Oct 14 |
No lecture
|
L12: Analog building blocks (opamps, DACs, ADCs), sampling, reconstruction, filtering.
|
| Oct 21 |
L13: Potpourri: FFT, FPGAs, RFID, Tools
|
Lab 4 Report due by 10/22 23:59 |
|
L14: VLSI and power
|
| Oct 28 |
|
Work on Project Proposal
|
| Nov 04 |
Writing workshop: final report (attendance required)
Project Proposal Draft due
Schedule optional presentation rehearsal with staff
|
Project Block Diagram Meeting by 11/07 by 5pm
|
| Nov 11 |
Project Design Presentations (Tue/Thu during class time) - attendance required
Revised Project Proposals due 11/15 (Fri) by 5pm
Project Checklist Meeting with Staff by 11/15 (Fri) by 5pm
|
| Nov 18 |
Final project integration and debugging
One week remaining!
|
| Nov 25 |
|
Thanksgiving |
| Dec 2 |
Final project debugged - finishing touches!
The last week!
|
| Dec 09 |
Project Checkoffs 12/09, 4-9 pm (Mon)
|
Project demos and taping; return tool kits 12/10 @ 6-11 pm (Tue) |
|
Project Report due 12/11 @ Noon (Wed)
|