| Week of |
Tue |
Thu |
| Sep 05 |
Registration Day |
L01: Course overview. Digital abstraction, static discipline, logic families
|
| Sep 12 |
L02: Combinational logic, canonical representations, simplification and synthesis
|
L03: Verilog hardware description languge. FPGA architectures
|
| Sep 19 |
L04: Sequential building blocks, state and feedback, registers
|
L05: Finite state machines, Verilog implementation examples
|
| Sep 26 |
L06: Case study: video circuits
|
L07: System Integration, Clocking, number encoding
|
| Oct 03 |
L08: Arithmetic circuits, adder, multipliers
|
L09: Behavioral transformations, FPGA
|
| Oct 10 |
Student Holiday |
L10: Analog building blocks (op-amps, DACs, ADCs), sampling, reconstruction, filtering
|
| Oct 17 |
L11: Project kickoff; proposals and presentations
|
L12: Memories: on-chip, SRAM, DRAM, Flash
|
| Oct 24 |
L13: Potpourri: FFT, FPGAs, RFID, Tools
|
L14: VLSI and power
|
| Oct 31 |
Project Proposal Draft due
.
|
Project Block Diagram Meeting
by 11/04 (Fri) by 5pm
|
| Nov 07 |
Project Design Presentations
(2:30-5PM room TBD) - attendance required
|
Project Design Presentations
(2:30-5PM room TBD) - attendance required
|
| Nov 14 |
|
Project Checklist Meeting with Staff |
|
Revised Project Proposals due 11/18 (Fri) by 5pm |
|
Final project
Project Checklist Meeting with Staff by 11/18 (Fri) by 5pm
|
| Nov 21 |
Final project
Short week |
Thanksgiving |
| Nov 28 |
Final project integrtion and debugging - finishing touches!
Two weeks remaining!
|
| Dec 05 |
|
Final project - finishing touches! |
|
Final project - polishing!
|
| Dec 12 |
Project Checkoff/Video recording Mon/Tue
|
Wed project Report due 12/14@ 5PM (Wed)
|