6.111 Fall 2017

Key:

Week of Tue Thu
Sep 04 Registration Day L01: Course overview. Digital abstraction, static discipline, logic families
Sep 11 L02: Combinational logic, canonical representations, simplification and synthesis L03: Verilog hardware description languge. FPGA architectures
Lab #1 checkoff
Sep 18 L04: Sequential building blocks, state and feedback, registers L05: Finite state machines, Verilog implementation examples
Lab #2 checkoff
Sep 25 L06: Case study: video circuits L07: System Integration, Clocking, number encoding
Oct 02 L08: Arithmetic circuits, adder, multipliers
Lab #3, Checkoff
L09: Behavioral transformations, FPGA
Oct 09 Student Holiday L10: Analog building blocks (op-amps, DACs, ADCs), sampling, reconstruction, filtering
Lab #4, Checkoff
Oct 16 L11: Project kickoff; proposals and presentations L12: Memories: on-chip, SRAM, DRAM, Flash
Project abstract due
Lab #5 checkoff
Oct 23 L13: Communications
Proposal Conferences
Work on Project Proposal
L14: Image Processing - Let's go to Fenway!
Proposal Conferences
Work on Project Proposal
Oct 30 L15: VLSI and power
Project Proposal
Project Block Diagram Meeting
by 11/03 (Fri) by 5pm
Nov 06 Project Design Presentations
(2:30-5PM room TBD) - attendance required
Project Design Presentations
(2:30-5PM room TBD) - attendance required
Nov 13
Project Checklist Meeting with Staff
Revised Project Proposals due 11/17 (Fri) by 5pm
Final project
Project Checklist Meeting with Staff by 11/18 (Fri) by 5pm
Nov 20 Final project
Short week
Thanksgiving
Nov 27 Final project integrtion and debugging - finishing touches!
Two weeks remaining!
Dec 04
Final project - finishing touches!
Final project - polishing!
...
Dec 11 Project Checkoff/Video recording Mon/Tue
Return tool kits Tue
Wed project Report due 12/13@ 5PM (Wed)
Tie up loose ends

Last modified on 06/21/2017