///////////////////////////////////////////////////////////////////////////////
//
// 6.111 FPGA Labkit -- AC'97 Example: Audio Analog Loopback
//
// For Labkit Revision 003
//
//
// Created: April 18, 2004
// Author: Nathan Ickes
//
///////////////////////////////////////////////////////////////////////////////
//
// This design illustrates how to generate AC'97 frames using an FSM, and how
// to write to configuration registers in the codec. This design clears the 
// mute bits in three of the volume control registers, so that signals on the
// line-level inputs are played through on the line-level and headphone
// outputs. Playback is accomplished by routing the analog inputs directly 
// into the codec's output mixer: the ADCs and DACs are not involved.
//
///////////////////////////////////////////////////////////////////////////////

module audioloopback (clock, audio_reset_b, ac97_sdata_out, ac97_sdata_in,
		      ac97_synch, ac97_bit_clock);

   input clock;
   output audio_reset_b;
   output ac97_sdata_out;
   input ac97_sdata_in;
   output ac97_synch;
   input ac97_bit_clock;

   reg audio_reset_b;
   reg ac97_sdata_out;
   reg ac97_synch;
   
   reg [7:0] bit_count;
   reg [3:0] frame_count;
   
   reg [23:0] command;
   wire [19:0] command_data;
   wire [19:0] command_address;

   reg [7:0] reset_count;

   initial begin
      reset_count = 0;
      // synthesis attribute init of reset_count is "00";
      audio_reset_b = 1'b0;
      // synthesis attribute init of audio_reset_b is "0";
   end
   
   always @(posedge clock)
     if (reset_count == 255)
       audio_reset_b <= 1;
     else
       reset_count = reset_count+1;
   
   initial begin
      bit_count = 8'h00;
      // synthesis attribute init of bit_count is "00";
      frame_count = 4'h0;
      // synthesis attribute init of frame_count is "0";
   end
   
   always @(posedge ac97_bit_clock) begin
      // Generate the sync signal
      if (bit_count == 255)
	ac97_synch <= 1'b1;
      if (bit_count == 15)
	ac97_synch <= 1'b0;

      if ((bit_count >= 0) && (bit_count <= 15))
	// Slot 0: Tags
	case (bit_count[3:0])
	  4'h0: ac97_sdata_out <= 1; // Frame valid
	  4'h1: ac97_sdata_out <= 1; // Command address valid
	  4'h2: ac97_sdata_out <= 1; // Command data valid
	  default: ac97_sdata_out <= 1'b0;
	endcase
      
      else if ((bit_count >= 16) && (bit_count <= 35))
	// Slot 1: Command address
	ac97_sdata_out <= command_address[35-bit_count];
      
      else if ((bit_count >= 36) && (bit_count <= 55))
	// Slot 2: Command data
	ac97_sdata_out <= command_data[55-bit_count];
      
      else 
	ac97_sdata_out <= 1'b0;

      if (bit_count == 255)
	frame_count <= frame_count+1;
      bit_count <= bit_count+1;      
   end

   always @(frame_count)
     case (frame_count)
       4'h0: command = 24'h02_0000; // Unmute line outputs
       4'h1: command = 24'h04_0000; // Unmute headphones
       4'h2: command = 24'h10_0808; // Unmute line inputs
       default: command = 24'hFC_0000; // Read vendor ID
     endcase

   // Separate the address and data portions of the command
   // and pad them to 20 bits
   assign command_address = {command[23:16], 12'h000};
   assign command_data = {command[15:0], 4'h0};
   
endmodule

///////////////////////////////////////////////////////////////////////////////
//
// 6.111 FPGA Labkit -- Template Toplevel Module
//
// For Labkit Revision 003
//
//
// Created: March 15, 2004, from revision 002 file
// Author: Nathan Ickes
//
///////////////////////////////////////////////////////////////////////////////
//
// CHANGES FOR BOARD REVISION 003
//
// 1) Combined flash chip enables into a single signal, flash_ce_b.
// 2) Combined the "parity" buses for each RAM into the "data" buses.
// 3) Combined the byte write enable signals for each RAM into the four-bit
//    signals "ram0_bwe_b" and "ram1_bwe_b"
//
// CHANGES FOR BOARD REVISION 002
//
// 1) Added SRAM clock feedback path input and output
// 2) Renamed "mousedata" to "mouse_data"
// 3) Renamed some ZBT memory signals. Parity bits are now incorporated into 
//    the data bus, and the byte write enables have been combined into the
//    4-bit ram#_bwe_b bus.
// 4) Removed the "systemace_clock" net, since the SystemACE clock is now
//    hardwired on the PCB to the oscillator.
//
///////////////////////////////////////////////////////////////////////////////

module labkit (beep, audio_reset_b, ac97_sdata_out, ac97_sdata_in, ac97_synch,
	       ac97_bit_clock,
	       
	       vga_out_red, vga_out_green, vga_out_blue, vga_out_sync_b,
	       vga_out_blank_b, vga_out_pixel_clock, vga_out_hsync,
	       vga_out_vsync,

	       tv_out_ycrcb, tv_out_reset_b, tv_out_clock, tv_out_sclk,
	       tv_out_data, tv_out_pal_ntsc, tv_out_hsync_b, tv_out_vsync_b,
	       tv_out_blank_b, tv_out_subcar_reset,

	       tv_in_ycrcb, tv_in_data_valid, tv_in_line_clock1,
	       tv_in_line_clock2, tv_in_aef, tv_in_hff, tv_in_aff,
	       tv_in_i2c_clock, tv_in_i2c_data, tv_in_fifo_read,
	       tv_in_fifo_clock, tv_in_iso, tv_in_reset_b, tv_in_clock,

	       ram0_data, ram0_address, ram0_adv_ld, ram0_clk, ram0_cen_b,
	       ram0_ce_b, ram0_oe_b, ram0_we_b, ram0_bwe_b, 

	       ram1_data, ram1_address, ram1_adv_ld, ram1_clk, ram1_cen_b,
	       ram1_ce_b, ram1_oe_b, ram1_we_b, ram1_bwe_b,

	       clock_feedback_out, clock_feedback_in,

	       flash_data, flash_address, flash_ce_b, flash_oe_b, flash_we_b,
	       flash_reset_b, flash_sts, flash_byte_b,

	       rs232_txd, rs232_rxd, rs232_rts, rs232_cts,

	       mouse_clock, mouse_data, keyboard_clock, keyboard_data,

	       clock_27mhz, clock1, clock2,

	       disp_blank, disp_data_out, disp_clock, disp_rs, disp_ce_b,
	       disp_reset_b, disp_data_in,

	       button0, button1, button2, button3, button_enter, button_right,
	       button_left, button_down, button_up,

	       switch,

	       led,
	       
	       user1, user2, user3, user4,
	       
	       daughtercard,

	       systemace_data, systemace_address, systemace_ce_b,
	       systemace_we_b, systemace_oe_b, systemace_irq, systemace_mpbrdy,
	       
	       analyzer1_data, analyzer1_clock);

   output beep, audio_reset_b, ac97_synch, ac97_sdata_out;
   input  ac97_bit_clock, ac97_sdata_in;
   
   output [7:0] vga_out_red, vga_out_green, vga_out_blue;
   output vga_out_sync_b, vga_out_blank_b, vga_out_pixel_clock,
	  vga_out_hsync, vga_out_vsync;

   output [9:0] tv_out_ycrcb;
   output tv_out_reset_b, tv_out_clock, tv_out_sclk, tv_out_data,
	  tv_out_pal_ntsc, tv_out_hsync_b, tv_out_vsync_b, tv_out_blank_b,
	  tv_out_subcar_reset;
   
   input  [9:0] tv_in_ycrcb;
   input  tv_in_data_valid, tv_in_line_clock1, tv_in_line_clock2, tv_in_aef,
	  tv_in_hff, tv_in_aff;
   output tv_in_i2c_clock, tv_in_fifo_read, tv_in_fifo_clock, tv_in_iso,
	  tv_in_reset_b, tv_in_clock;
   inout  tv_in_i2c_data;
        
   inout  [35:0] ram0_data;
   output [20:0] ram0_address;
   output ram0_adv_ld, ram0_clk, ram0_cen_b, ram0_ce_b, ram0_oe_b, ram0_we_b;
   output [3:0] ram0_bwe_b;
   
   inout  [35:0] ram1_data;
   output [20:0] ram1_address;
   output ram1_adv_ld, ram1_clk, ram1_cen_b, ram1_ce_b, ram1_oe_b, ram1_we_b;
   output [3:0] ram1_bwe_b;

   input  clock_feedback_in;
   output clock_feedback_out;
   
   inout  [15:0] flash_data;
   output [24:0] flash_address;
   output flash_ce_b, flash_oe_b, flash_we_b, flash_reset_b, flash_byte_b;
   input  flash_sts;
   
   output rs232_txd, rs232_rts;
   input  rs232_rxd, rs232_cts;

   input  mouse_clock, mouse_data, keyboard_clock, keyboard_data;

   input  clock_27mhz, clock1, clock2;

   output disp_blank, disp_clock, disp_rs, disp_ce_b, disp_reset_b;  
   input  disp_data_out;
   input  disp_data_in;
   
   input  button0, button1, button2, button3, button_enter, button_right,
	  button_left, button_down, button_up;
   input  [7:0] switch;
   output [7:0] led;

   inout [31:0] user1, user2, user3, user4;
   
   inout [43:0] daughtercard;

   inout  [15:0] systemace_data;
   output [6:0]  systemace_address;
   output systemace_ce_b, systemace_we_b, systemace_oe_b;
   input  systemace_irq, systemace_mpbrdy;

   output [15:0] analyzer1_data;
   output analyzer1_clock;

   ////////////////////////////////////////////////////////////////////////////
   //
   // I/O Assignments
   //
   ////////////////////////////////////////////////////////////////////////////
   
   // Audio Input and Output

   audioloopback alp (clock_27mhz, audio_reset_b, ac97_sdata_out, ac97_sdata_in,
		      ac97_synch, ac97_bit_clock);
   
   // VGA Output
   assign vga_out_red = 8'h0;
   assign vga_out_green = 8'h0;
   assign vga_out_blue = 8'h0;
   assign vga_out_sync_b = 1'b1;
   assign vga_out_blank_b = 1'b1;
   assign vga_out_pixel_clock = 1'b0;
   assign vga_out_hsync = 1'b0;
   assign vga_out_vsync = 1'b0;

   // Video Output
   assign tv_out_ycrcb = 10'h0;
   assign tv_out_reset_b = 1'b0;
   assign tv_out_clock = 1'b0;
   assign tv_out_sclk = 1'b0;
   assign tv_out_data = 1'b0;
   assign tv_out_pal_ntsc = 1'b0;
   assign tv_out_hsync_b = 1'b1;
   assign tv_out_vsync_b = 1'b1;
   assign tv_out_blank_b = 1'b1;
   assign tv_out_subcar_reset = 1'b0;
   
   // Video Input
   assign tv_in_i2c_clock = 1'b0;
   assign tv_in_fifo_read = 1'b0;
   assign tv_in_fifo_clock = 1'b0;
   assign tv_in_iso = 1'b0;
   assign tv_in_reset_b = 1'b0; // Hold video encoder in reset
   assign tv_in_clock = 1'b0;
   assign tv_in_i2c_data = 1'bZ;
   // tv_in_ycrcb, tv_in_data_valid, tv_in_line_clock1, tv_in_line_clock2, 
   // tv_in_aef, tv_in_hff, and tv_in_aff are inputs
   
   // SRAMs
   assign ram0_data = 36'hZ; // Tristate data bus
   assign ram0_address = 21'h0;
   assign ram0_adv_ld = 1'b0;
   assign ram0_clk = 1'b0;
   assign ram0_cen_b = 1'b1;
   assign ram0_ce_b = 1'b1;
   assign ram0_oe_b = 1'b1;
   assign ram0_we_b = 1'b1;
   assign ram0_bwe_b = 4'hF;
   assign ram1_data = 36'hZ; // Tristate data bus
   assign ram1_address = 21'h0;
   assign ram1_adv_ld = 1'b0;
   assign ram1_clk = 1'b0;
   assign ram1_cen_b = 1'b1;
   assign ram1_ce_b = 1'b1;
   assign ram1_oe_b = 1'b1;
   assign ram1_we_b = 1'b1;
   assign ram1_bwe_b = 4'hF;
   assign clock_feedback_out = 1'b0;
   // clock_feedback_in is an input
   
   // Flash ROM
   assign flash_data = 16'hZ; // Trisatate data bus
   assign flash_address = 15'h0;
   assign flash_ce_b = 1'b1;
   assign flash_oe_b = 1'b1;
   assign flash_we_b = 1'b1;
   assign flash_reset_b = 1'b0; // Hold flash in reset
   assign flash_byte_b = 1'b1; // Put flash in 16-bit mode
   // flash_sts is an input

   // RS-232 Interface
   assign rs232_txd = 1'b1;
   assign rs232_rts = 1'b1;
   // rs232_rxd and rs232_cts are inputs

   // PS/2 Ports
   // mouse_clock, mouse_data, keyboard_clock, and keyboard_data are inputs

   // LED Displays
   assign disp_blank = 1'b1; // Blank displays
   assign disp_clock = 1'b0;
   assign disp_rs = 1'b0;
   assign disp_ce_b = 1'b1;
   assign disp_reset_b = 1'b0; // Hold displays in reset
   // disp_data_out is an input

   // Buttons, Switches, and Individual LEDs
   assign led = 8'hFF; // Turn off all LEDs
   // button0, button1, button2, button3, button_enter, button_right,
   // button_left, button_down, button_up, and switches are inputs

   // User I/Os
   assign user1 = 32'hZ;
   assign user2 = 32'hZ;
   assign user3 = 32'hZ;
   assign user4 = 32'hZ;

   // Daughtercard Connectors
   assign daughtercard = 44'hZ;

   // SystemACE Microprocessor Port
   assign systemace_data = 16'hZ; // Tristate data bus
   assign systemace_address = 7'h0;
   assign systemace_ce_b = 1'b1;
   assign systemace_we_b = 1'b1;
   assign systemace_oe_b = 1'b1;
   // systemace_irq and systemace_mpbrdy are inputs

   // Logic Analyzer
   assign analyzer1_data = {12'h0,
			    audio_reset_b,
			    ac97_synch,
			    ac97_sdata_in,
			    ac97_sdata_out};
   assign analyzer1_clock = ac97_bit_clock;
   
endmodule