module vga (reset, clock_27mhz, vga_out_red, vga_out_green, vga_out_blue,
	    vga_out_sync_b, vga_out_blank_b, vga_out_pixel_clock,
	    vga_out_hsync, vga_out_vsync);

   input reset; // Active high reset, synchronous with 27MHz clock
   input clock_27mhz; // 27MHz input clock
   output [7:0] vga_out_red, vga_out_green, vga_out_blue; // Outputs to DAC
   output vga_out_sync_b, vga_out_blank_b; // Composite sync/blank outputs to DAC
   output vga_out_pixel_clock; // Pixel clock for DAC
   output vga_out_hsync, vga_out_vsync; // Sync outputs to VGA connector


   ////////////////////////////////////////////////////////////////////////////
   //
   // Timing values
   //
   ////////////////////////////////////////////////////////////////////////////
   
   // 1024 X 768 @ 75Hz with a 78.750MHz pixel clock
`define H_ACTIVE	1024 // pixels
`define H_FRONT_PORCH	  16 // pixels
`define H_SYNCH		  96 // pixels
`define H_BACK_PORCH	 176 // pixels
`define H_TOTAL		1312 // pixels
   
`define V_ACTIVE	 768 // lines
`define V_FRONT_PORCH	   1 // lines
`define V_SYNCH		   3 // lines
`define V_BACK_PORCH	  28 // lines
`define V_TOTAL		 800 // lines

   ////////////////////////////////////////////////////////////////////////////
   //
   // Internal signals
   //
   ////////////////////////////////////////////////////////////////////////////
   
   wire pixel_clock;
   reg prst, pixel_reset; // Active high reset, synchronous with pixel clock

   reg [7:0] vga_out_red, vga_out_blue, vga_out_green;
   wire vga_out_sync_b, vga_out_blank_b;	     
   reg hsync1, hsync2, vga_out_hsync, vsync1, vsync2, vga_out_vsync;
   
   reg [10:0] pixel_count; // Counts pixels in each line
   reg [10:0] line_count; // Counts lines in each frame

   ////////////////////////////////////////////////////////////////////////////
   //
   // Generate the pixel clock (78.750MHz)
   //
   ////////////////////////////////////////////////////////////////////////////
   
   // synthesis attribute period of clock_27mhz is 37ns;
   
   DCM vga_dcm (.CLKIN(clock_27mhz), 
			.RST(1'b0),
			.CLKFX(pixel_clock));
   // synthesis attribute DLL_FREQUENCY_MODE of vga_dcm is "LOW"
   // synthesis attribute DUTY_CYCLE_CORRECTION of vga_dcm is "TRUE"
   // synthesis attribute STARTUP_WAIT of vga_dcm is "TRUE"
   // synthesis attribute DFS_FREQUENCY_MODE of vga_dcm is "LOW"
   // synthesis attribute CLKFX_DIVIDE of vga_dcm is 9
   // synthesis attribute CLKFX_MULTIPLY of vga_dcm is 26
   // synthesis attribute CLK_FEEDBACK of vga_dcm  is "1X"
   // synthesis attribute CLKOUT_PHASE_SHIFT of vga_dcm is "NONE"
   // synthesis attribute PHASE_SHIFT of vga_dcm is 0
   // synthesis attribute clkin_period of vga_dcm is "37.04ns"
   
   assign vga_out_pixel_clock = ~pixel_clock;

   always @(posedge pixel_clock)
     begin
	prst <= reset;
	pixel_reset <= prst;
     end
   
   ////////////////////////////////////////////////////////////////////////////
   //
   // Pixel and Line Counters
   //
   ////////////////////////////////////////////////////////////////////////////

   always @(posedge pixel_clock)
     if (pixel_reset)
       begin
	  pixel_count <= 0;
	  line_count <= 0;
       end
     else if (pixel_count == (`H_TOTAL-1)) // last pixel in the line
       begin
	  pixel_count <= 0;
	  if (line_count == (`V_TOTAL-1)) // last line of the frame
	    line_count <= 0;
	  else
	    line_count <= line_count + 1;
       end
     else
       pixel_count <= pixel_count +1;		

   ////////////////////////////////////////////////////////////////////////////
   //
   // Sync and Blank Signals
   //
   ////////////////////////////////////////////////////////////////////////////

   always @ (posedge pixel_clock)
     begin
	if (pixel_reset)
	  begin
	     hsync1 <= 1;
	     hsync2 <= 1;
	     vga_out_hsync <= 1;
	     vsync1 <= 1;
	     vsync2 <= 1;
	     vga_out_vsync <= 1;
	  end
	else 
	  begin

	     // Horizontal sync
	     if (pixel_count == (`H_ACTIVE+`H_FRONT_PORCH))
	       hsync1 <= 0; // start of h_sync
	     else if (pixel_count == (`H_ACTIVE+`H_FRONT_PORCH+`H_SYNCH))
	       hsync1 <= 1; // end of h_sync

	     // Vertical sync
	     if (pixel_count == (`H_TOTAL-1))
	       begin
		  if (line_count == (`V_ACTIVE+`V_FRONT_PORCH))
		    vsync1 <= 0; // start of v_sync
		  else if (line_count == (`V_ACTIVE+`V_FRONT_PORCH+`V_SYNCH))
		    vsync1 <= 1; // end of v_sync
	       end
	     
	  end

	// Delay hsync and vsync by two cycles to compensate for 2 cycles of
	// pipeline delay in the DAC.
	hsync2 <= hsync1;
	vga_out_hsync <= hsync2;
	vsync2 <= vsync1;
	vga_out_vsync <= vsync2;
		
     end

   // Blanking   
   assign vga_out_blank_b = ((pixel_count<`H_ACTIVE) & (line_count<`V_ACTIVE));

   // Composite sync
   assign vga_out_sync_b = hsync1 ^ vsync1;

   ////////////////////////////////////////////////////////////////////////////
   //
   // Generate a pretty picture
   //
   ////////////////////////////////////////////////////////////////////////////

   reg [15:0] frame_count;
   
   always @(posedge pixel_clock)
     if (pixel_reset)
       frame_count <= 0;
     else if ((pixel_count == `H_TOTAL-1) && (line_count == `V_TOTAL-1))
       frame_count <= frame_count + 1;

   wire [6:0] grad;
   assign grad = pixel_count[5:0]+line_count[5:0];
      
   always @ (posedge pixel_clock)
     begin
	vga_out_red <= (line_count[7]^pixel_count[7]) ? grad*2 : 255-grad*2;
	vga_out_green <= (line_count[8]^pixel_count[8]) ? grad*2 : 0;
	vga_out_blue <= (line_count[9]^pixel_count[9]) ? grad*2 : 0;
     end
   
endmodule