///////////////////////////////////////////////////////////////////////////////
//
// 6.111 FPGA Labkit -- Video (TV) Test Code
//
// For Labkit Revision 004
//
//
// Created: November 3, 2004
// Author: Nathan Ickes
//
///////////////////////////////////////////////////////////////////////////////

`include "i2c.v"
`include "adv7194init.v"
`include "adv7185init.v"

module video (reset, clock_27mhz, tv_out_ycrcb, tv_out_reset_b, tv_out_clock,
	      tv_out_i2c_clock, tv_out_i2c_data, tv_out_pal_ntsc,
	      tv_out_hsync_b, tv_out_vsync_b, tv_out_blank_b,
	      tv_out_subcar_reset, tv_in_ycrcb, tv_in_data_valid,
	      tv_in_line_clock1, tv_in_line_clock2,  tv_in_aef, tv_in_hff,
	      tv_in_aff, tv_in_i2c_clock, tv_in_i2c_data, tv_in_fifo_read,
	      tv_in_fifo_clock, tv_in_iso, tv_in_reset_b, tv_in_clock, mode);

   input reset;
   input clock_27mhz;   
   
   output [9:0] tv_out_ycrcb;
   output tv_out_reset_b, tv_out_clock, tv_out_i2c_clock, tv_out_i2c_data,
	  tv_out_pal_ntsc, tv_out_hsync_b, tv_out_vsync_b, tv_out_blank_b,
	  tv_out_subcar_reset;
   
   input [9:0] tv_in_ycrcb;
   input tv_in_data_valid, tv_in_line_clock1, tv_in_line_clock2, tv_in_aef,
	 tv_in_hff, tv_in_aff;
   output tv_in_i2c_clock, tv_in_i2c_data, tv_in_fifo_read, tv_in_fifo_clock,
	  tv_in_iso, tv_in_reset_b, tv_in_clock;
   input [1:0] mode;

   // Mode Decoding
   //
   // 0 = colorbars, 1 = MIT logo, 2 = composite passthrough,
   // 3 = s-video passthrough

   wire colorbars, logo, svideo;
   assign colorbars = (mode == 0);
   assign logo = (mode == 1);
   assign svideo = (mode == 3);

   //
   // Logo generator
   //

   wire [9:0] logo_ycrcb; 
   videologo logo1 (reset, clock_27mhz, logo_ycrcb);
   
   //
   // ADV7194 (Output)
   //

   assign tv_out_clock = (logo||colorbars) ? clock_27mhz : tv_in_line_clock1;
   assign tv_out_pal_ntsc = 1'b0;
   assign tv_out_vsync_b = 0;
   assign tv_out_hsync_b = 0;
   assign tv_out_subcar_reset = 0;
   assign tv_out_blank_b = 0;
   
   adv7194init init7194 (reset, clock_27mhz, colorbars, 
			 tv_out_reset_b, tv_out_i2c_clock, tv_out_i2c_data);

   assign tv_out_ycrcb = logo ? logo_ycrcb : tv_in_ycrcb;

   //
   // ADV7185 (Input)
   //

   assign tv_in_fifo_read = 1'b1;
   assign tv_in_fifo_clock = 1'b0;
   assign tv_in_iso = 1'b1;
   assign tv_in_clock = clock_27mhz;
   
   adv7185init init7185 (reset, clock_27mhz, svideo, tv_in_reset_b,
			 tv_in_i2c_clock, tv_in_i2c_data);
   
endmodule

module videologo (reset, clock_27mhz, ycrcb);

   input reset, clock_27mhz;
   output [9:0] ycrcb;

   reg [9:0] y, cr, cb;
   
   reg [10:0] sample_count;
   reg [9:0] line_count;
   reg f, v, h;
   reg [7:0] xy;
   reg [9:0] ycrcb;
   reg [9:0] h_position, v_position;
   
   always @(negedge clock_27mhz)
     if (reset)
       begin
	  sample_count <= 0;
	  line_count <= 0;
       end
     else 
       begin
	  if (sample_count < 1440)
	    // Output active video 
	    // 720 pixels per line,  two samples (Y and C) per sposition
	    // Sample order is Cb0, Y0, Cr1, Y1, Cb2, Y2, . . .
	    case (sample_count[1:0])
	      2'b00: ycrcb <= cb;
	      2'b01: ycrcb <= y;
	      2'b10: ycrcb <= cr;
	      2'b11: ycrcb <= y;
	    endcase
	  else if (sample_count == 1440)
	    // Start header for the EAV timecode
	    ycrcb <= 10'h3FC;
	  else if (sample_count == 1441)
	    ycrcb <= 10'h000;
	  else if (sample_count == 1442)
	    ycrcb <= 10'h000;
	  else if (sample_count == 1443)
	    // EAV timecode
	    begin
	       ycrcb <= {xy, 2'b00};
	       $display("EAV at line %d, sample %d is 0b%B",
			line_count, sample_count, xy);
	    end
	  else if (sample_count < 1712)
	    ycrcb <= sample_count[0] ? 10'h200 : 10'h040;
	  else if (sample_count == 1712)
	    // Begin header for SAV timecode
	    ycrcb <= 10'h3fC;
	  else if (sample_count == 1713)
	    ycrcb <= 10'h000;
	  else if (sample_count == 1714)
	    ycrcb <= 10'h000;
	  else if (sample_count == 1715)
	    // SAV timecode
	    begin
	       ycrcb <= {xy, 2'b00};
	       $display("SAV at line %d, sample %d is 0b%B",
			line_count, sample_count, xy);
   	    end

	  if (sample_count == 1715)
	    begin
	       sample_count <= 0;
	       if (line_count == 524)
		 line_count <= 0;
	       else
		 line_count <= line_count+1;
	    end
	  else
	    sample_count <= sample_count+1;
       end
   
   // Compute the F, V, H, X, and Y bits for the timecodes   
   always @(sample_count or line_count)
     begin
	f <= (line_count < 9) || (line_count > 271);
	v <= (line_count < 19) || ((line_count > 262) && (line_count < 282));
	h <= (sample_count > 1439) & (sample_count < 1715);
	xy <= {1'b1, f, v, h, v^h, f^h, f^v, f^v^h};
     end

   always @(sample_count or line_count)
     if (line_count < 19)
       begin
	  h_position <= 0;
	  v_position <= 0;
       end
     else if (line_count < 262)
       begin
	  h_position <= (sample_count[10:1] < 719) ? 
		       sample_count[10:1]+sample_count[0] : 0;
	  v_position <= {line_count-19, 1'b1};
       end
     else if (line_count < 282)
       begin
	  h_position <= 0;
	  v_position <= 0;
       end
     else
       begin
	  h_position <= (sample_count[10:1] < 719) ? 
			sample_count[10:1]+sample_count[0] : 0;
	  v_position <= {line_count-281, 1'b0};
       end
   
   always @(h_position or v_position)
     if ((h_position > 248) && (h_position < 472)
	 && (v_position > 131) && (v_position < 355))
       begin
	  y <= 10'h3AC; // maximum brightness
	  cr <= (h_position-248)*4+64;
	  cb <= (v_position-131)*4+64;
       end
     else
       begin
	  y <= 64;
	  cr <= 64;
	  cb <= 64;
       end
   
endmodule