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 FPGA Labkit

for 6.111 Introduction to Digital Systems

6.111 home → Labkit home → Test Programs → Flash ROM Test

Flash ROM Test

by Nathan Ickes

Introduction

This test verifies that the labkit's flash ROM chip is working properly. As part of the test, the entire ROM is erased, so any data previously stored in it will be lost. At the end of the test, the ROM is erased again, so that it is left in a blank state.

Setup

No setup is necessary for this test, other than configuring the FPGA with the test program. Precompiled bitstreams can be downloaded below

Procedure

The test begins running as soon as the FPGA is configured. First, the flash ROM's manufacturer and size identification codes are read. The expected manufacturer code is 0x0089 (Intel), and the expected size code is 0x0018 (128Mbit). If an incorrect code is read from the flash, the alphanumeric display will read "ERR: MANUF 00000" or "ERR: SIZE 0000", where 0000 indicates the actual code value read.

After the identification codes are successfully read, the block write protection bits are cleared. Once the "clear lock bits" command has been issued to the ROM, the test program waits for the operation to finish, and then reads the ROM's status register. If any error flags are set, the test is stopped and the alphanumeric display will read "ERR: LOCKS 0000", where 000 indicates the value read from the status register, in hexadecimal.

Next, the entire ROM is erased. It takes approximately one second to erase each of the 128 blocks in device. During this process, the alphanumeric display indicates the address of the current block being erased. (The address of the last block is 0x7F0000.) The ROM's status register is checked after the erasure of every block. If an error flag becomes set, the test stops and the alphanumeric display will read "ERR: ERASE 0000", where 0000 indicates the value read from the status register, in hexadecimal.

Once the ROM is erased, the test program proceeds to write to every location in the ROM. The value written to a given location is computed from the location's address by the following Verilog expression: 

data <= address[15:0] ^ address[22:16];
The test program writes one word at a time: the write acceleration buffer is not used. The process of writing to the entire ROM therefore takes a long time: approximately 15 minutes. As in the other phases of the test, the ROM's status register is checked after every write, and any error codes cause the test process to stop. The display will read "ERR: WRITE 0000", where 0000 indicates the value read from the status register, in hexadecimal.

Next, the entire contents of the ROM are read back and compared with the expected values. If any location fails to verify, the test is stopped, and the display will read "ERR: 000000 0000", where 000000 is the address of the failing location and 0000 is the data actually read back at that location.

Finally, the entire ROM is erased again. If the erase completes without errors, the test is finished, and the display will read " *** PASSED *** ".

A few additional notes: the flash ROM is tested in 16-bit mode, so address line 0 is not used. The status signal (STS) from the ROM is not used either. (The status of the write state machine is monitored by repetitively reading the status register.) The STS signal is passed through the FPGA, however, and can be monitored on user I/O bank 1, pin 4. Since STS is an open-drain output on the flash device, and there is no pullup on the PCB, a pullup resistor is implemented inside the FPGA.

Signals Available for Probing

The following signals can be probed through either the logic analyzer connectors, or the user I/O banks. Note that these signals are only copies of the actual signals present at the flash device, buffered by the FPGA.
Signal Description Verilog Name Logic Analyzer User I/O
Labkit clock (27MHz) clock_27mhz Pod 1, clock Bank 1, pin 0
FPGA internal reset reset Pod 1, channel 0 Bank 1, pin 1
ROM operation (00=idle, 10=write, 01=read) fop[1:0] Pod 1, channels 2-1 Bank 1, pins 3-2
ROM status pin flash_sts Pod 1, channel 3 Bank 1, pin 4
ROM reset flash_reset_b Pod 1, channel 4 Bank 1, pin 5
ROM write enable flash_we_b Pod 1, channel 5 Bank 1, pin 6
ROM output enable flash_oe_b Pod 1, channel 6 Bank 1, pin 7
ROM chip enable flash_ce_b Pod 1, channel 7 Bank 1, pin 8
ROM data bus flash_data[15:0] Pod 2, channels 15-0 Bank 1, pins 31-16
ROM address bus flash_address[22:0] [15:0]: Pod 3, channels 15-0
[22:16]: Pod 4, channels 6-0		 Bank 2, pins 22-0

Source Code

MIT 6.111 Introduction to Digital Systems, Updated April 05, 2005