///////////////////////////////////////////////////////////////////////////////
//
// 6.111 FPGA Labkit -- I/O Test Program
//
// For Labkit Revision 004
//
//
// Created: October 31, 2004
// Author: Nathan Ickes
//
///////////////////////////////////////////////////////////////////////////////

module labkit (beep, audio_reset_b, ac97_sdata_out, ac97_sdata_in, ac97_synch,
	       ac97_bit_clock,
	       
	       vga_out_red, vga_out_green, vga_out_blue, vga_out_sync_b,
	       vga_out_blank_b, vga_out_pixel_clock, vga_out_hsync,
	       vga_out_vsync,

	       tv_out_ycrcb, tv_out_reset_b, tv_out_clock, tv_out_i2c_clock,
	       tv_out_i2c_data, tv_out_pal_ntsc, tv_out_hsync_b,
	       tv_out_vsync_b, tv_out_blank_b, tv_out_subcar_reset,

	       tv_in_ycrcb, tv_in_data_valid, tv_in_line_clock1,
	       tv_in_line_clock2, tv_in_aef, tv_in_hff, tv_in_aff,
	       tv_in_i2c_clock, tv_in_i2c_data, tv_in_fifo_read,
	       tv_in_fifo_clock, tv_in_iso, tv_in_reset_b, tv_in_clock,

	       ram0_data, ram0_address, ram0_adv_ld, ram0_clk, ram0_cen_b,
	       ram0_ce_b, ram0_oe_b, ram0_we_b, ram0_bwe_b, 

	       ram1_data, ram1_address, ram1_adv_ld, ram1_clk, ram1_cen_b,
	       ram1_ce_b, ram1_oe_b, ram1_we_b, ram1_bwe_b,

	       clock_feedback_out, clock_feedback_in,

	       flash_data, flash_address, flash_ce_b, flash_oe_b, flash_we_b,
	       flash_reset_b, flash_sts, flash_byte_b,

	       rs232_txd, rs232_rxd, rs232_rts, rs232_cts,

	       mouse_clock, mouse_data, keyboard_clock, keyboard_data,

	       clock_27mhz, clock1, clock2,

	       disp_blank, disp_data_out, disp_clock, disp_rs, disp_ce_b,
	       disp_reset_b, disp_data_in,

	       button0, button1, button2, button3, button_enter, button_right,
	       button_left, button_down, button_up,

	       switch,

	       led,
	       
	       user1, user2, user3, user4,
	       
	       daughtercard,

	       systemace_data, systemace_address, systemace_ce_b,
	       systemace_we_b, systemace_oe_b, systemace_irq, systemace_mpbrdy,
	       
	       analyzer1_data, analyzer1_clock,
 	       analyzer2_data, analyzer2_clock,
 	       analyzer3_data, analyzer3_clock,
 	       analyzer4_data, analyzer4_clock);

   output beep, audio_reset_b, ac97_synch, ac97_sdata_out;
   input  ac97_bit_clock, ac97_sdata_in;
   
   output [7:0] vga_out_red, vga_out_green, vga_out_blue;
   output vga_out_sync_b, vga_out_blank_b, vga_out_pixel_clock,
	  vga_out_hsync, vga_out_vsync;

   output [9:0] tv_out_ycrcb;
   output tv_out_reset_b, tv_out_clock, tv_out_i2c_clock, tv_out_i2c_data,
	  tv_out_pal_ntsc, tv_out_hsync_b, tv_out_vsync_b, tv_out_blank_b,
	  tv_out_subcar_reset;
   
   input  [19:0] tv_in_ycrcb;
   input  tv_in_data_valid, tv_in_line_clock1, tv_in_line_clock2, tv_in_aef,
	  tv_in_hff, tv_in_aff;
   output tv_in_i2c_clock, tv_in_fifo_read, tv_in_fifo_clock, tv_in_iso,
	  tv_in_reset_b, tv_in_clock;
   inout  tv_in_i2c_data;
        
   inout  [35:0] ram0_data;
   output [20:0] ram0_address;
   output ram0_adv_ld, ram0_clk, ram0_cen_b, ram0_ce_b, ram0_oe_b, ram0_we_b;
   output [3:0] ram0_bwe_b;
   
   inout  [35:0] ram1_data;
   output [20:0] ram1_address;
   output ram1_adv_ld, ram1_clk, ram1_cen_b, ram1_ce_b, ram1_oe_b, ram1_we_b;
   output [3:0] ram1_bwe_b;

   input  clock_feedback_in;
   output clock_feedback_out;
   
   inout  [15:0] flash_data;
   output [24:0] flash_address;
   output flash_ce_b, flash_oe_b, flash_we_b, flash_reset_b, flash_byte_b;
   input  flash_sts;
   
   output rs232_txd, rs232_rts;
   input  rs232_rxd, rs232_cts;

   input  mouse_clock, mouse_data, keyboard_clock, keyboard_data;

   input  clock_27mhz, clock1, clock2;

   output disp_blank, disp_clock, disp_rs, disp_ce_b, disp_reset_b;  
   output disp_data_out;
   input  disp_data_in;
   
   input  button0, button1, button2, button3, button_enter, button_right,
	  button_left, button_down, button_up;
   input  [7:0] switch;
   output [7:0] led;

   inout [31:0] user1, user2, user3, user4;
   
   inout [43:0] daughtercard;

   inout  [15:0] systemace_data;
   output [6:0]  systemace_address;
   output systemace_ce_b, systemace_we_b, systemace_oe_b;
   input  systemace_irq, systemace_mpbrdy;

   inout [15:0] analyzer1_data, analyzer2_data, analyzer3_data, 
		analyzer4_data;
   inout analyzer1_clock, analyzer2_clock, analyzer3_clock, analyzer4_clock;

   ////////////////////////////////////////////////////////////////////////////
   //
   // Reset Generation
   //
   // A shift register primitive is used to generate an active-high reset
   // signal that remains high for 16 clock cycles after configuration finishes
   // and the FPGA's internal clocks begin toggling.
   //
   ////////////////////////////////////////////////////////////////////////////

   wire reset;
   SRL16 reset_sr (.D(1'b0), .CLK(clock_27mhz), .Q(reset),
		   .A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1));
   defparam reset_sr.INIT = 16'hFFFF;
   
   ////////////////////////////////////////////////////////////////////////////
   //
   // Clocks
   //
   ////////////////////////////////////////////////////////////////////////////

   // synthesis attribute period of clock_27mhz is 37ns;

   reg clock_500khz;
   reg [4:0] clock_500khz_count;
   always @(posedge clock_27mhz)
     if (reset)
       begin
	  clock_500khz_count <= 0;
	  clock_500khz <= 0;
       end
   else
     if (clock_500khz_count == 27)
       begin
	  clock_500khz <= !clock_500khz;
	  clock_500khz_count <= 0;
       end
     else
       clock_500khz_count <= clock_500khz_count+1;
   
   ////////////////////////////////////////////////////////////////////////////
   //
   // LED, Switch, and Pushbutton Test Logic
   //
   ////////////////////////////////////////////////////////////////////////////
   
   reg [7:0] led;
   reg [31:0] blink_counter;
   reg blink;

   always @(posedge clock_27mhz)
     if (reset)
       begin
	  blink_counter = 0;
	  blink = 0;
       end
     else if (blink_counter == 1350000)
       begin
	  blink = !blink;
	  blink_counter = 0;
       end
     else
       blink_counter = blink_counter+1;

   always @(blink or switch or button_enter or button_up or button_down 
	    or button_left or button_right or button0 or button1 or button2
	    or button3)
     if (!button_enter)
       led <= 8'h00;
     else
       begin
	  led[0] <= button0      ? !switch[0] : blink;
	  led[1] <= button1      ? !switch[1] : blink;
	  led[2] <= button2      ? !switch[2] : blink;
	  led[3] <= button3      ? !switch[3] : blink;
	  led[4] <= button_right ? !switch[4] : blink;
	  led[5] <= button_left  ? !switch[5] : blink;
	  led[6] <= button_down  ? !switch[6] : blink;
	  led[7] <= button_up    ? !switch[7] : blink;
       end	  
   
   ////////////////////////////////////////////////////////////////////////////
   //
   // Logic Analyzer, User I/O, and Daughtercard Test Logic
   //
   ////////////////////////////////////////////////////////////////////////////
   
   wire [119:0] ain, aout, bin, bout;
   wire [7:0]  gpioindex;
   wire gpiodir, gpiopass, gpiofail;
   
   gpiolb gpiolb1 (reset, clock_500khz, ain, aout, bin, bout, 
		   gpiodir, gpiopass, gpiofail, gpioindex);
   defparam gpiolb1.bank_width = 120;
   defparam gpiolb1.index_width = 8;

   // User 1
   assign user1[0] = (!gpiodir && aout[0]) ? 1'b1 : 1'bZ;
   assign ain[0] = user1[0];
   assign user1[1] = (!gpiodir && aout[1]) ? 1'b1 : 1'bZ;
   assign ain[1] = user1[1];
   assign user1[2] = (!gpiodir && aout[2]) ? 1'b1 : 1'bZ;
   assign ain[2] = user1[2];
   assign user1[3] = (!gpiodir && aout[3]) ? 1'b1 : 1'bZ;
   assign ain[3] = user1[3];
   assign user1[4] = (!gpiodir && aout[4]) ? 1'b1 : 1'bZ;
   assign ain[4] = user1[4];
   assign user1[5] = (!gpiodir && aout[5]) ? 1'b1 : 1'bZ;
   assign ain[5] = user1[5];
   assign user1[6] = (!gpiodir && aout[6]) ? 1'b1 : 1'bZ;
   assign ain[6] = user1[6];
   assign user1[7] = (!gpiodir && aout[7]) ? 1'b1 : 1'bZ;
   assign ain[7] = user1[7];
   assign user1[8] = (!gpiodir && aout[8]) ? 1'b1 : 1'bZ;
   assign ain[8] = user1[8];
   assign user1[9] = (!gpiodir && aout[9]) ? 1'b1 : 1'bZ;
   assign ain[9] = user1[9];
   assign user1[10] = (!gpiodir && aout[10]) ? 1'b1 : 1'bZ;
   assign ain[10] = user1[10];
   assign user1[11] = (!gpiodir && aout[11]) ? 1'b1 : 1'bZ;
   assign ain[11] = user1[11];
   assign user1[12] = (!gpiodir && aout[12]) ? 1'b1 : 1'bZ;
   assign ain[12] = user1[12];
   assign user1[13] = (!gpiodir && aout[13]) ? 1'b1 : 1'bZ;
   assign ain[13] = user1[13];
   assign user1[14] = (!gpiodir && aout[14]) ? 1'b1 : 1'bZ;
   assign ain[14] = user1[14];
   assign user1[15] = (!gpiodir && aout[15]) ? 1'b1 : 1'bZ;
   assign ain[15] = user1[15];
   assign user1[16] = (!gpiodir && aout[16]) ? 1'b1 : 1'bZ;
   assign ain[16] = user1[16];
   assign user1[17] = (!gpiodir && aout[17]) ? 1'b1 : 1'bZ;
   assign ain[17] = user1[17];
   assign user1[18] = (!gpiodir && aout[18]) ? 1'b1 : 1'bZ;
   assign ain[18] = user1[18];
   assign user1[19] = (!gpiodir && aout[19]) ? 1'b1 : 1'bZ;
   assign ain[19] = user1[19];
   assign user1[20] = (!gpiodir && aout[20]) ? 1'b1 : 1'bZ;
   assign ain[20] = user1[20];
   assign user1[21] = (!gpiodir && aout[21]) ? 1'b1 : 1'bZ;
   assign ain[21] = user1[21];
   assign user1[22] = (!gpiodir && aout[22]) ? 1'b1 : 1'bZ;
   assign ain[22] = user1[22];
   assign user1[23] = (!gpiodir && aout[23]) ? 1'b1 : 1'bZ;
   assign ain[23] = user1[23];
   assign user1[24] = (!gpiodir && aout[24]) ? 1'b1 : 1'bZ;
   assign ain[24] = user1[24];
   assign user1[25] = (!gpiodir && aout[25]) ? 1'b1 : 1'bZ;
   assign ain[25] = user1[25];
   assign user1[26] = (!gpiodir && aout[26]) ? 1'b1 : 1'bZ;
   assign ain[26] = user1[26];
   assign user1[27] = (!gpiodir && aout[27]) ? 1'b1 : 1'bZ;
   assign ain[27] = user1[27];
   assign user1[28] = (!gpiodir && aout[28]) ? 1'b1 : 1'bZ;
   assign ain[28] = user1[28];
   assign user1[29] = (!gpiodir && aout[29]) ? 1'b1 : 1'bZ;
   assign ain[29] = user1[29];
   assign user1[30] = (!gpiodir && aout[30]) ? 1'b1 : 1'bZ;
   assign ain[30] = user1[30];
   assign user1[31] = (!gpiodir && aout[31]) ? 1'b1 : 1'bZ;
   assign ain[31] = user1[31];
   
   // User 2
   assign user2[0] = (!gpiodir && aout[32]) ? 1'b1 : 1'bZ;
   assign ain[32] = user2[0];
   assign user2[1] = (!gpiodir && aout[33]) ? 1'b1 : 1'bZ;
   assign ain[33] = user2[1];
   assign user2[2] = (!gpiodir && aout[34]) ? 1'b1 : 1'bZ;
   assign ain[34] = user2[2];
   assign user2[3] = (!gpiodir && aout[35]) ? 1'b1 : 1'bZ;
   assign ain[35] = user2[3];
   assign user2[4] = (!gpiodir && aout[36]) ? 1'b1 : 1'bZ;
   assign ain[36] = user2[4];
   assign user2[5] = (!gpiodir && aout[37]) ? 1'b1 : 1'bZ;
   assign ain[37] = user2[5];
   assign user2[6] = (!gpiodir && aout[38]) ? 1'b1 : 1'bZ;
   assign ain[38] = user2[6];
   assign user2[7] = (!gpiodir && aout[39]) ? 1'b1 : 1'bZ;
   assign ain[39] = user2[7];
   assign user2[8] = (!gpiodir && aout[40]) ? 1'b1 : 1'bZ;
   assign ain[40] = user2[8];
   assign user2[9] = (!gpiodir && aout[41]) ? 1'b1 : 1'bZ;
   assign ain[41] = user2[9];
   assign user2[10] = (!gpiodir && aout[42]) ? 1'b1 : 1'bZ;
   assign ain[42] = user2[10];
   assign user2[11] = (!gpiodir && aout[43]) ? 1'b1 : 1'bZ;
   assign ain[43] = user2[11];
   assign user2[12] = (!gpiodir && aout[44]) ? 1'b1 : 1'bZ;
   assign ain[44] = user2[12];
   assign user2[13] = (!gpiodir && aout[45]) ? 1'b1 : 1'bZ;
   assign ain[45] = user2[13];
   assign user2[14] = (!gpiodir && aout[46]) ? 1'b1 : 1'bZ;
   assign ain[46] = user2[14];
   assign user2[15] = (!gpiodir && aout[47]) ? 1'b1 : 1'bZ;
   assign ain[47] = user2[15];
   assign user2[16] = (!gpiodir && aout[48]) ? 1'b1 : 1'bZ;
   assign ain[48] = user2[16];
   assign user2[17] = (!gpiodir && aout[49]) ? 1'b1 : 1'bZ;
   assign ain[49] = user2[17];
   assign user2[18] = (!gpiodir && aout[50]) ? 1'b1 : 1'bZ;
   assign ain[50] = user2[18];
   assign user2[19] = (!gpiodir && aout[51]) ? 1'b1 : 1'bZ;
   assign ain[51] = user2[19];
   assign user2[20] = (!gpiodir && aout[52]) ? 1'b1 : 1'bZ;
   assign ain[52] = user2[20];
   assign user2[21] = (!gpiodir && aout[53]) ? 1'b1 : 1'bZ;
   assign ain[53] = user2[21];
   assign user2[22] = (!gpiodir && aout[54]) ? 1'b1 : 1'bZ;
   assign ain[54] = user2[22];
   assign user2[23] = (!gpiodir && aout[55]) ? 1'b1 : 1'bZ;
   assign ain[55] = user2[23];
   assign user2[24] = (!gpiodir && aout[56]) ? 1'b1 : 1'bZ;
   assign ain[56] = user2[24];
   assign user2[25] = (!gpiodir && aout[57]) ? 1'b1 : 1'bZ;
   assign ain[57] = user2[25];
   assign user2[26] = (!gpiodir && aout[58]) ? 1'b1 : 1'bZ;
   assign ain[58] = user2[26];
   assign user2[27] = (!gpiodir && aout[59]) ? 1'b1 : 1'bZ;
   assign ain[59] = user2[27];
   assign user2[28] = (!gpiodir && aout[60]) ? 1'b1 : 1'bZ;
   assign ain[60] = user2[28];
   assign user2[29] = (!gpiodir && aout[61]) ? 1'b1 : 1'bZ;
   assign ain[61] = user2[29];
   assign user2[30] = (!gpiodir && aout[62]) ? 1'b1 : 1'bZ;
   assign ain[62] = user2[30];
   assign user2[31] = (!gpiodir && aout[63]) ? 1'b1 : 1'bZ;
   assign ain[63] = user2[31];
   
   // User 3
   assign user3[2] = (gpiodir && bout[0]) ? 1'b1 : 1'bZ;
   assign bin[0] = user3[2];
   assign user3[3] = (gpiodir && bout[1]) ? 1'b1 : 1'bZ;
   assign bin[1] = user3[3];
   assign user3[4] = (gpiodir && bout[2]) ? 1'b1 : 1'bZ;
   assign bin[2] = user3[4];
   assign user3[5] = (gpiodir && bout[3]) ? 1'b1 : 1'bZ;
   assign bin[3] = user3[5];
   assign user3[6] = (gpiodir && bout[4]) ? 1'b1 : 1'bZ;
   assign bin[4] = user3[6];
   assign user3[7] = (gpiodir && bout[5]) ? 1'b1 : 1'bZ;
   assign bin[5] = user3[7];
   assign user3[8] = (gpiodir && bout[6]) ? 1'b1 : 1'bZ;
   assign bin[6] = user3[8];
   assign user3[9] = (gpiodir && bout[7]) ? 1'b1 : 1'bZ;
   assign bin[7] = user3[9];
   assign user3[10] = (gpiodir && bout[8]) ? 1'b1 : 1'bZ;
   assign bin[8] = user3[10];
   assign user3[11] = (gpiodir && bout[9]) ? 1'b1 : 1'bZ;
   assign bin[9] = user3[11];
   assign user3[12] = (gpiodir && bout[10]) ? 1'b1 : 1'bZ;
   assign bin[10] = user3[12];
   assign user3[13] = (gpiodir && bout[11]) ? 1'b1 : 1'bZ;
   assign bin[11] = user3[13];
   assign user3[14] = (gpiodir && bout[12]) ? 1'b1 : 1'bZ;
   assign bin[12] = user3[14];
   assign user3[15] = (gpiodir && bout[13]) ? 1'b1 : 1'bZ;
   assign bin[13] = user3[15];
   assign user3[16] = (gpiodir && bout[14]) ? 1'b1 : 1'bZ;
   assign bin[14] = user3[16];
   assign user3[17] = (gpiodir && bout[15]) ? 1'b1 : 1'bZ;
   assign bin[15] = user3[17];
   assign user3[18] = (gpiodir && bout[16]) ? 1'b1 : 1'bZ;
   assign bin[16] = user3[18];
   assign user3[19] = (gpiodir && bout[17]) ? 1'b1 : 1'bZ;
   assign bin[17] = user3[19];
   assign user3[20] = (gpiodir && bout[18]) ? 1'b1 : 1'bZ;
   assign bin[18] = user3[20];
   assign user3[21] = (gpiodir && bout[19]) ? 1'b1 : 1'bZ;
   assign bin[19] = user3[21];
   assign user3[22] = (gpiodir && bout[20]) ? 1'b1 : 1'bZ;
   assign bin[20] = user3[22];
   assign user3[23] = (gpiodir && bout[21]) ? 1'b1 : 1'bZ;
   assign bin[21] = user3[23];
   assign user3[24] = (gpiodir && bout[22]) ? 1'b1 : 1'bZ;
   assign bin[22] = user3[24];
   assign user3[25] = (gpiodir && bout[23]) ? 1'b1 : 1'bZ;
   assign bin[23] = user3[25];
   assign user3[26] = (gpiodir && bout[24]) ? 1'b1 : 1'bZ;
   assign bin[24] = user3[26];
   assign user3[27] = (gpiodir && bout[25]) ? 1'b1 : 1'bZ;
   assign bin[25] = user3[27];
   assign user3[28] = (gpiodir && bout[26]) ? 1'b1 : 1'bZ;
   assign bin[26] = user3[28];
   assign user3[29] = (gpiodir && bout[27]) ? 1'b1 : 1'bZ;
   assign bin[27] = user3[29];
   assign user3[30] = (gpiodir && bout[28]) ? 1'b1 : 1'bZ;
   assign bin[28] = user3[30];
   assign user3[31] = (gpiodir && bout[29]) ? 1'b1 : 1'bZ;
   assign bin[29] = user3[31];
   assign user3[0] = (gpiodir && bout[30]) ? 1'b1 : 1'bZ;
   assign bin[30] = user3[0];
   assign user3[1] = (gpiodir && bout[31]) ? 1'b1 : 1'bZ;
   assign bin[31] = user3[1];
   
   // User 4
   assign user4[2] = (gpiodir && bout[32]) ? 1'b1 : 1'bZ;
   assign bin[32] = user4[2];
   assign user4[3] = (gpiodir && bout[33]) ? 1'b1 : 1'bZ;
   assign bin[33] = user4[3];
   assign user4[4] = (gpiodir && bout[34]) ? 1'b1 : 1'bZ;
   assign bin[34] = user4[4];
   assign user4[5] = (gpiodir && bout[35]) ? 1'b1 : 1'bZ;
   assign bin[35] = user4[5];
   assign user4[6] = (gpiodir && bout[36]) ? 1'b1 : 1'bZ;
   assign bin[36] = user4[6];
   assign user4[7] = (gpiodir && bout[37]) ? 1'b1 : 1'bZ;
   assign bin[37] = user4[7];
   assign user4[8] = (gpiodir && bout[38]) ? 1'b1 : 1'bZ;
   assign bin[38] = user4[8];
   assign user4[9] = (gpiodir && bout[39]) ? 1'b1 : 1'bZ;
   assign bin[39] = user4[9];
   assign user4[10] = (gpiodir && bout[40]) ? 1'b1 : 1'bZ;
   assign bin[40] = user4[10];
   assign user4[11] = (gpiodir && bout[41]) ? 1'b1 : 1'bZ;
   assign bin[41] = user4[11];
   assign user4[12] = (gpiodir && bout[42]) ? 1'b1 : 1'bZ;
   assign bin[42] = user4[12];
   assign user4[13] = (gpiodir && bout[43]) ? 1'b1 : 1'bZ;
   assign bin[43] = user4[13];
   assign user4[14] = (gpiodir && bout[44]) ? 1'b1 : 1'bZ;
   assign bin[44] = user4[14];
   assign user4[15] = (gpiodir && bout[45]) ? 1'b1 : 1'bZ;
   assign bin[45] = user4[15];
   assign user4[16] = (gpiodir && bout[46]) ? 1'b1 : 1'bZ;
   assign bin[46] = user4[16];
   assign user4[17] = (gpiodir && bout[47]) ? 1'b1 : 1'bZ;
   assign bin[47] = user4[17];
   assign user4[18] = (gpiodir && bout[48]) ? 1'b1 : 1'bZ;
   assign bin[48] = user4[18];
   assign user4[19] = (gpiodir && bout[49]) ? 1'b1 : 1'bZ;
   assign bin[49] = user4[19];
   assign user4[20] = (gpiodir && bout[50]) ? 1'b1 : 1'bZ;
   assign bin[50] = user4[20];
   assign user4[21] = (gpiodir && bout[51]) ? 1'b1 : 1'bZ;
   assign bin[51] = user4[21];
   assign user4[22] = (gpiodir && bout[52]) ? 1'b1 : 1'bZ;
   assign bin[52] = user4[22];
   assign user4[23] = (gpiodir && bout[53]) ? 1'b1 : 1'bZ;
   assign bin[53] = user4[23];
   assign user4[24] = (gpiodir && bout[54]) ? 1'b1 : 1'bZ;
   assign bin[54] = user4[24];
   assign user4[25] = (gpiodir && bout[55]) ? 1'b1 : 1'bZ;
   assign bin[55] = user4[25];
   assign user4[26] = (gpiodir && bout[56]) ? 1'b1 : 1'bZ;
   assign bin[56] = user4[26];
   assign user4[27] = (gpiodir && bout[57]) ? 1'b1 : 1'bZ;
   assign bin[57] = user4[27];
   assign user4[28] = (gpiodir && bout[58]) ? 1'b1 : 1'bZ;
   assign bin[58] = user4[28];
   assign user4[29] = (gpiodir && bout[59]) ? 1'b1 : 1'bZ;
   assign bin[59] = user4[29];
   assign user4[30] = (gpiodir && bout[60]) ? 1'b1 : 1'bZ;
   assign bin[60] = user4[30];
   assign user4[31] = (gpiodir && bout[61]) ? 1'b1 : 1'bZ;
   assign bin[61] = user4[31];
   assign user4[0] = (gpiodir && bout[62]) ? 1'b1 : 1'bZ;
   assign bin[62] = user4[0];
   assign user4[1] = (gpiodir && bout[63]) ? 1'b1 : 1'bZ;
   assign bin[63] = user4[1];
   
   // Daughtercard
   assign daughtercard[0] = (!gpiodir && aout[64]) ? 1'b1 : 1'bZ;
   assign ain[64] = daughtercard[0];
   assign daughtercard[1] = (!gpiodir && aout[65]) ? 1'b1 : 1'bZ;
   assign ain[65] = daughtercard[1];
   assign daughtercard[2] = (!gpiodir && aout[66]) ? 1'b1 : 1'bZ;
   assign ain[66] = daughtercard[2];
   assign daughtercard[3] = (!gpiodir && aout[67]) ? 1'b1 : 1'bZ;
   assign ain[67] = daughtercard[3];
   assign daughtercard[4] = (!gpiodir && aout[68]) ? 1'b1 : 1'bZ;
   assign ain[68] = daughtercard[4];
   assign daughtercard[5] = (!gpiodir && aout[69]) ? 1'b1 : 1'bZ;
   assign ain[69] = daughtercard[5];
   assign daughtercard[6] = (!gpiodir && aout[70]) ? 1'b1 : 1'bZ;
   assign ain[70] = daughtercard[6];
   assign daughtercard[7] = (!gpiodir && aout[71]) ? 1'b1 : 1'bZ;
   assign ain[71] = daughtercard[7];
   assign daughtercard[8] = (!gpiodir && aout[72]) ? 1'b1 : 1'bZ;
   assign ain[72] = daughtercard[8];
   assign daughtercard[9] = (!gpiodir && aout[73]) ? 1'b1 : 1'bZ;
   assign ain[73] = daughtercard[9];
   assign daughtercard[10] = (!gpiodir && aout[74]) ? 1'b1 : 1'bZ;
   assign ain[74] = daughtercard[10];
   assign daughtercard[11] = (!gpiodir && aout[75]) ? 1'b1 : 1'bZ;
   assign ain[75] = daughtercard[11];
   assign daughtercard[12] = (!gpiodir && aout[76]) ? 1'b1 : 1'bZ;
   assign ain[76] = daughtercard[12];
   assign daughtercard[13] = (!gpiodir && aout[77]) ? 1'b1 : 1'bZ;
   assign ain[77] = daughtercard[13];
   assign daughtercard[14] = (!gpiodir && aout[78]) ? 1'b1 : 1'bZ;
   assign ain[78] = daughtercard[14];
   assign daughtercard[15] = (!gpiodir && aout[79]) ? 1'b1 : 1'bZ;
   assign ain[79] = daughtercard[15];
   assign daughtercard[16] = (!gpiodir && aout[80]) ? 1'b1 : 1'bZ;
   assign ain[80] = daughtercard[16];
   assign daughtercard[17] = (!gpiodir && aout[81]) ? 1'b1 : 1'bZ;
   assign ain[81] = daughtercard[17];
   assign daughtercard[18] = (!gpiodir && aout[82]) ? 1'b1 : 1'bZ;
   assign ain[82] = daughtercard[18];
   assign daughtercard[19] = (!gpiodir && aout[83]) ? 1'b1 : 1'bZ;
   assign ain[83] = daughtercard[19];
   assign daughtercard[20] = (!gpiodir && aout[84]) ? 1'b1 : 1'bZ;
   assign ain[84] = daughtercard[20];
   assign daughtercard[21] = (!gpiodir && aout[85]) ? 1'b1 : 1'bZ;
   assign ain[85] = daughtercard[21];
   assign daughtercard[43] = (gpiodir && bout[64]) ? 1'b1 : 1'bZ;
   assign bin[64] = daughtercard[43];
   assign daughtercard[42] = (gpiodir && bout[65]) ? 1'b1 : 1'bZ;
   assign bin[65] = daughtercard[42];
   assign daughtercard[41] = (gpiodir && bout[66]) ? 1'b1 : 1'bZ;
   assign bin[66] = daughtercard[41];
   assign daughtercard[40] = (gpiodir && bout[67]) ? 1'b1 : 1'bZ;
   assign bin[67] = daughtercard[40];
   assign daughtercard[39] = (gpiodir && bout[68]) ? 1'b1 : 1'bZ;
   assign bin[68] = daughtercard[39];
   assign daughtercard[38] = (gpiodir && bout[69]) ? 1'b1 : 1'bZ;
   assign bin[69] = daughtercard[38];
   assign daughtercard[37] = (gpiodir && bout[70]) ? 1'b1 : 1'bZ;
   assign bin[70] = daughtercard[37];
   assign daughtercard[36] = (gpiodir && bout[71]) ? 1'b1 : 1'bZ;
   assign bin[71] = daughtercard[36];
   assign daughtercard[35] = (gpiodir && bout[72]) ? 1'b1 : 1'bZ;
   assign bin[72] = daughtercard[35];
   assign daughtercard[34] = (gpiodir && bout[73]) ? 1'b1 : 1'bZ;
   assign bin[73] = daughtercard[34];
   assign daughtercard[33] = (gpiodir && bout[74]) ? 1'b1 : 1'bZ;
   assign bin[74] = daughtercard[33];
   assign daughtercard[32] = (gpiodir && bout[75]) ? 1'b1 : 1'bZ;
   assign bin[75] = daughtercard[32];
   assign daughtercard[31] = (gpiodir && bout[76]) ? 1'b1 : 1'bZ;
   assign bin[76] = daughtercard[31];
   assign daughtercard[30] = (gpiodir && bout[77]) ? 1'b1 : 1'bZ;
   assign bin[77] = daughtercard[30];
   assign daughtercard[29] = (gpiodir && bout[78]) ? 1'b1 : 1'bZ;
   assign bin[78] = daughtercard[29];
   assign daughtercard[28] = (gpiodir && bout[79]) ? 1'b1 : 1'bZ;
   assign bin[79] = daughtercard[28];
   assign daughtercard[27] = (gpiodir && bout[80]) ? 1'b1 : 1'bZ;
   assign bin[80] = daughtercard[27];
   assign daughtercard[26] = (gpiodir && bout[81]) ? 1'b1 : 1'bZ;
   assign bin[81] = daughtercard[26];
   assign daughtercard[25] = (gpiodir && bout[82]) ? 1'b1 : 1'bZ;
   assign bin[82] = daughtercard[25];
   assign daughtercard[24] = (gpiodir && bout[83]) ? 1'b1 : 1'bZ;
   assign bin[83] = daughtercard[24];
   assign daughtercard[23] = (gpiodir && bout[84]) ? 1'b1 : 1'bZ;
   assign bin[84] = daughtercard[23];
   assign daughtercard[22] = (gpiodir && bout[85]) ? 1'b1 : 1'bZ;
   assign bin[85] = daughtercard[22];
   
   // Analyzer 1
   assign analyzer1_data[0] = (!gpiodir && aout[86]) ? 1'b1 : 1'bZ;
   assign ain[86] = analyzer1_data[0];
   assign analyzer1_data[1] = (!gpiodir && aout[87]) ? 1'b1 : 1'bZ;
   assign ain[87] = analyzer1_data[1];
   assign analyzer1_data[2] = (!gpiodir && aout[88]) ? 1'b1 : 1'bZ;
   assign ain[88] = analyzer1_data[2];
   assign analyzer1_data[3] = (!gpiodir && aout[89]) ? 1'b1 : 1'bZ;
   assign ain[89] = analyzer1_data[3];
   assign analyzer1_data[4] = (!gpiodir && aout[90]) ? 1'b1 : 1'bZ;
   assign ain[90] = analyzer1_data[4];
   assign analyzer1_data[5] = (!gpiodir && aout[91]) ? 1'b1 : 1'bZ;
   assign ain[91] = analyzer1_data[5];
   assign analyzer1_data[6] = (!gpiodir && aout[92]) ? 1'b1 : 1'bZ;
   assign ain[92] = analyzer1_data[6];
   assign analyzer1_data[7] = (!gpiodir && aout[93]) ? 1'b1 : 1'bZ;
   assign ain[93] = analyzer1_data[7];
   assign analyzer1_data[8] = (!gpiodir && aout[94]) ? 1'b1 : 1'bZ;
   assign ain[94] = analyzer1_data[8];
   assign analyzer1_data[9] = (!gpiodir && aout[95]) ? 1'b1 : 1'bZ;
   assign ain[95] = analyzer1_data[9];
   assign analyzer1_data[10] = (!gpiodir && aout[96]) ? 1'b1 : 1'bZ;
   assign ain[96] = analyzer1_data[10];
   assign analyzer1_data[11] = (!gpiodir && aout[97]) ? 1'b1 : 1'bZ;
   assign ain[97] = analyzer1_data[11];
   assign analyzer1_data[12] = (!gpiodir && aout[98]) ? 1'b1 : 1'bZ;
   assign ain[98] = analyzer1_data[12];
   assign analyzer1_data[13] = (!gpiodir && aout[99]) ? 1'b1 : 1'bZ;
   assign ain[99] = analyzer1_data[13];
   assign analyzer1_data[14] = (!gpiodir && aout[100]) ? 1'b1 : 1'bZ;
   assign ain[100] = analyzer1_data[14];
   assign analyzer1_data[15] = (!gpiodir && aout[101]) ? 1'b1 : 1'bZ;
   assign ain[101] = analyzer1_data[15];
   assign analyzer1_clock = (!gpiodir && aout[102]) ? 1'b1 : 1'bZ;
   assign ain[102] = analyzer1_clock;
   
   // Analyzer 2
   assign analyzer2_data[0] = (gpiodir && bout[86]) ? 1'b1 : 1'bZ;
   assign bin[86] = analyzer2_data[0];
   assign analyzer2_data[1] = (gpiodir && bout[87]) ? 1'b1 : 1'bZ;
   assign bin[87] = analyzer2_data[1];
   assign analyzer2_data[2] = (gpiodir && bout[88]) ? 1'b1 : 1'bZ;
   assign bin[88] = analyzer2_data[2];
   assign analyzer2_data[3] = (gpiodir && bout[89]) ? 1'b1 : 1'bZ;
   assign bin[89] = analyzer2_data[3];
   assign analyzer2_data[4] = (gpiodir && bout[90]) ? 1'b1 : 1'bZ;
   assign bin[90] = analyzer2_data[4];
   assign analyzer2_data[5] = (gpiodir && bout[91]) ? 1'b1 : 1'bZ;
   assign bin[91] = analyzer2_data[5];
   assign analyzer2_data[6] = (gpiodir && bout[92]) ? 1'b1 : 1'bZ;
   assign bin[92] = analyzer2_data[6];
   assign analyzer2_data[7] = (gpiodir && bout[93]) ? 1'b1 : 1'bZ;
   assign bin[93] = analyzer2_data[7];
   assign analyzer2_data[8] = (gpiodir && bout[94]) ? 1'b1 : 1'bZ;
   assign bin[94] = analyzer2_data[8];
   assign analyzer2_data[9] = (gpiodir && bout[95]) ? 1'b1 : 1'bZ;
   assign bin[95] = analyzer2_data[9];
   assign analyzer2_data[10] = (gpiodir && bout[96]) ? 1'b1 : 1'bZ;
   assign bin[96] = analyzer2_data[10];
   assign analyzer2_data[11] = (gpiodir && bout[97]) ? 1'b1 : 1'bZ;
   assign bin[97] = analyzer2_data[11];
   assign analyzer2_data[12] = (gpiodir && bout[98]) ? 1'b1 : 1'bZ;
   assign bin[98] = analyzer2_data[12];
   assign analyzer2_data[13] = (gpiodir && bout[99]) ? 1'b1 : 1'bZ;
   assign bin[99] = analyzer2_data[13];
   assign analyzer2_data[14] = (gpiodir && bout[100]) ? 1'b1 : 1'bZ;
   assign bin[100] = analyzer2_data[14];
   assign analyzer2_data[15] = (gpiodir && bout[101]) ? 1'b1 : 1'bZ;
   assign bin[101] = analyzer2_data[15];
   assign analyzer2_clock = (gpiodir && bout[102]) ? 1'b1 : 1'bZ;
   assign bin[102] = analyzer2_clock;
   
   // Analyzer 3
   assign analyzer3_data[0] = (!gpiodir && aout[103]) ? 1'b1 : 1'bZ;
   assign ain[103] = analyzer3_data[0];
   assign analyzer3_data[1] = (!gpiodir && aout[104]) ? 1'b1 : 1'bZ;
   assign ain[104] = analyzer3_data[1];
   assign analyzer3_data[2] = (!gpiodir && aout[105]) ? 1'b1 : 1'bZ;
   assign ain[105] = analyzer3_data[2];
   assign analyzer3_data[3] = (!gpiodir && aout[106]) ? 1'b1 : 1'bZ;
   assign ain[106] = analyzer3_data[3];
   assign analyzer3_data[4] = (!gpiodir && aout[107]) ? 1'b1 : 1'bZ;
   assign ain[107] = analyzer3_data[4];
   assign analyzer3_data[5] = (!gpiodir && aout[108]) ? 1'b1 : 1'bZ;
   assign ain[108] = analyzer3_data[5];
   assign analyzer3_data[6] = (!gpiodir && aout[109]) ? 1'b1 : 1'bZ;
   assign ain[109] = analyzer3_data[6];
   assign analyzer3_data[7] = (!gpiodir && aout[110]) ? 1'b1 : 1'bZ;
   assign ain[110] = analyzer3_data[7];
   assign analyzer3_data[8] = (!gpiodir && aout[111]) ? 1'b1 : 1'bZ;
   assign ain[111] = analyzer3_data[8];
   assign analyzer3_data[9] = (!gpiodir && aout[112]) ? 1'b1 : 1'bZ;
   assign ain[112] = analyzer3_data[9];
   assign analyzer3_data[10] = (!gpiodir && aout[113]) ? 1'b1 : 1'bZ;
   assign ain[113] = analyzer3_data[10];
   assign analyzer3_data[11] = (!gpiodir && aout[114]) ? 1'b1 : 1'bZ;
   assign ain[114] = analyzer3_data[11];
   assign analyzer3_data[12] = (!gpiodir && aout[115]) ? 1'b1 : 1'bZ;
   assign ain[115] = analyzer3_data[12];
   assign analyzer3_data[13] = (!gpiodir && aout[116]) ? 1'b1 : 1'bZ;
   assign ain[116] = analyzer3_data[13];
   assign analyzer3_data[14] = (!gpiodir && aout[117]) ? 1'b1 : 1'bZ;
   assign ain[117] = analyzer3_data[14];
   assign analyzer3_data[15] = (!gpiodir && aout[118]) ? 1'b1 : 1'bZ;
   assign ain[118] = analyzer3_data[15];
   assign analyzer3_clock = (!gpiodir && aout[119]) ? 1'b1 : 1'bZ;
   assign ain[119] = analyzer3_clock;
   
   // Analyzer 4
   assign analyzer4_data[0] = (gpiodir && bout[103]) ? 1'b1 : 1'bZ;
   assign bin[103] = analyzer4_data[0];
   assign analyzer4_data[1] = (gpiodir && bout[104]) ? 1'b1 : 1'bZ;
   assign bin[104] = analyzer4_data[1];
   assign analyzer4_data[2] = (gpiodir && bout[105]) ? 1'b1 : 1'bZ;
   assign bin[105] = analyzer4_data[2];
   assign analyzer4_data[3] = (gpiodir && bout[106]) ? 1'b1 : 1'bZ;
   assign bin[106] = analyzer4_data[3];
   assign analyzer4_data[4] = (gpiodir && bout[107]) ? 1'b1 : 1'bZ;
   assign bin[107] = analyzer4_data[4];
   assign analyzer4_data[5] = (gpiodir && bout[108]) ? 1'b1 : 1'bZ;
   assign bin[108] = analyzer4_data[5];
   assign analyzer4_data[6] = (gpiodir && bout[109]) ? 1'b1 : 1'bZ;
   assign bin[109] = analyzer4_data[6];
   assign analyzer4_data[7] = (gpiodir && bout[110]) ? 1'b1 : 1'bZ;
   assign bin[110] = analyzer4_data[7];
   assign analyzer4_data[8] = (gpiodir && bout[111]) ? 1'b1 : 1'bZ;
   assign bin[111] = analyzer4_data[8];
   assign analyzer4_data[9] = (gpiodir && bout[112]) ? 1'b1 : 1'bZ;
   assign bin[112] = analyzer4_data[9];
   assign analyzer4_data[10] = (gpiodir && bout[113]) ? 1'b1 : 1'bZ;
   assign bin[113] = analyzer4_data[10];
   assign analyzer4_data[11] = (gpiodir && bout[114]) ? 1'b1 : 1'bZ;
   assign bin[114] = analyzer4_data[11];
   assign analyzer4_data[12] = (gpiodir && bout[115]) ? 1'b1 : 1'bZ;
   assign bin[115] = analyzer4_data[12];
   assign analyzer4_data[13] = (gpiodir && bout[116]) ? 1'b1 : 1'bZ;
   assign bin[116] = analyzer4_data[13];
   assign analyzer4_data[14] = (gpiodir && bout[117]) ? 1'b1 : 1'bZ;
   assign bin[117] = analyzer4_data[14];
   assign analyzer4_data[15] = (gpiodir && bout[118]) ? 1'b1 : 1'bZ;
   assign bin[118] = analyzer4_data[15];
   assign analyzer4_clock = (gpiodir && bout[119]) ? 1'b1 : 1'bZ;
   assign bin[119] = analyzer4_clock;
   
   // Place pulldowns on all I/O signals
   //
   // synthesis attribute pulldown of user1 is yes;
   // synthesis attribute pulldown of user2 is yes;
   // synthesis attribute pulldown of user3 is yes;
   // synthesis attribute pulldown of user4 is yes;
   // synthesis attribute pulldown of daughtercard is yes;
   // synthesis attribute pulldown of analyzer1_data is yes;
   // synthesis attribute pulldown of analyzer1_clock is yes;
   // synthesis attribute pulldown of analyzer2_data is yes;
   // synthesis attribute pulldown of analyzer2_clock is yes;
   // synthesis attribute pulldown of analyzer3_data is yes;
   // synthesis attribute pulldown of analyzer3_clock is yes;
   // synthesis attribute pulldown of analyzer4_data is yes;
   // synthesis attribute pulldown of analyzer4_clock is yes;
   
   wire [79:0] gpiodots, gpiodotsi;
   hex_rom gpio_rom1 (gpioindex[3:0], gpiodotsi[39:0]);
   hex_rom gpio_rom2 (gpioindex[7:4], gpiodotsi[79:40]);
   assign gpiodots = gpiopass
	  ? {40'b00000000_00000000_00000000_00000000_00000000, // ' ',
	     40'b01111111_00001001_00001001_00001001_00000110} // 'P'
	  : gpiofail
	  ? gpiodotsi
	  : {40'b00001000_00001000_00001000_00001000_00001000, // '-'
	     40'b00001000_00001000_00001000_00001000_00001000}; // '-'

   ////////////////////////////////////////////////////////////////////////////
   //
   // Oscillator Sockets Test Logic
   //
   ////////////////////////////////////////////////////////////////////////////

   reg [15:0] phase_counter;
   reg [1:0]  phases1, phases2;
   reg [39:0] clock1_dots, clock2_dots;
   
   always @(posedge clock_27mhz)
     begin
	if (phase_counter == 0)
	  begin
	     phases1 <= 0;
	     phases2 <= 0;
	  end
	else
	  begin
	     if (clock1)
	       phases1[0] <= 1;
	     else
	       phases1[1] <= 1;
	     if (clock2)
	       phases2[0] <= 1;
	     else
	       phases2[1] <= 1;
	  end
	phase_counter = phase_counter+1;
     end

   always @(phases1)
     case (phases1)
       2'b00: clock1_dots <= 40'b00001000_00001000_00001000_00001000_00001000;
       2'b01: clock1_dots <= 40'b00010000_00100000_01111111_00100000_00010000;
       2'b10: clock1_dots <= 40'b00000100_00000010_11111111_00000010_00000100;
       2'b11: clock1_dots <= 40'b00010100_00100010_01111111_00100010_00010100;
     endcase

   always @(phases2)
     case (phases2)
       2'b00: clock2_dots <= 40'b00001000_00001000_00001000_00001000_00001000;
       2'b01: clock2_dots <= 40'b00010000_00100000_01111111_00100000_00010000;
       2'b10: clock2_dots <= 40'b00000100_00000010_11111111_00000010_00000100;
       2'b11: clock2_dots <= 40'b00010100_00100010_01111111_00100010_00010100;
     endcase

   ////////////////////////////////////////////////////////////////////////////
   //
   // RS-232 Interface Test Logic
   //
   ////////////////////////////////////////////////////////////////////////////

   // Trivial loopback logic, with flow control
   assign rs232_txd = rs232_rxd;
   assign rs232_rts = rs232_cts;

   ////////////////////////////////////////////////////////////////////////////
   //
   // PS/2 Interface Test Logic
   //
   ////////////////////////////////////////////////////////////////////////////

   wire [39:0] mouse_dots, keyboard_dots;
   
   ps2 ps2_mouse (.clock(mouse_clock), 
		  .data(mouse_data),
		  .reset(!button_enter),
		  .disp(mouse_dots));
   
   ps2 ps2_keyboard (.clock(keyboard_clock),
		     .data(keyboard_data),
		     .reset(!button_enter),
		     .disp(keyboard_dots));
   
   ////////////////////////////////////////////////////////////////////////////
   //
   // Alphanumeric displays
   //
   ////////////////////////////////////////////////////////////////////////////
   //
   // 0123456701234567
   // K:A M:A C:||  12
   //
   
   wire [639:0] dots;

   assign dots = { 40'b01111111_00001000_00010100_00100010_01000001, // 'K'
		   40'b00000000_00110110_00110110_00000000_00000000, // ':'
		   keyboard_dots,
		   40'b00000000_00000000_00000000_00000000_00000000, // ' '
		   40'b01111111_00000010_00001100_00000010_01111111, // 'M'
		   40'b00000000_00110110_00110110_00000000_00000000, // ':'
		   mouse_dots,
		   40'b00000000_00000000_00000000_00000000_00000000, // ' '
		   40'b00111110_01000001_01000001_01000001_00100010, // 'C'
		   40'b00000000_00110110_00110110_00000000_00000000, // ':'
		   clock1_dots,
		   clock2_dots,
		   40'b00000000_00000000_00000000_00000000_00000000, // ' '
		   40'b00000000_00000000_00000000_00000000_00000000, // ' '
		   gpiodots
		   };

   display disp (reset, clock_27mhz, disp_blank, disp_clock, disp_rs,
		 disp_ce_b, disp_reset_b, disp_data_out, dots);
   
   ////////////////////////////////////////////////////////////////////////////
   //
   // Default I/O Assignments
   //
   ////////////////////////////////////////////////////////////////////////////

   // Audio Input and Output
   assign beep= 1'b0;
   assign audio_reset_b = 1'b0;
   assign ac97_synch = 1'b0;
   assign ac97_sdata_out = 1'b0;
   
   // VGA Output
   assign vga_out_red = 10'h0;
   assign vga_out_green = 10'h0;
   assign vga_out_blue = 10'h0;
   assign vga_out_sync_b = 1'b1;
   assign vga_out_blank_b = 1'b1;
   assign vga_out_pixel_clock = 1'b0;
   assign vga_out_hsync = 1'b0;
   assign vga_out_vsync = 1'b0;

   // Video Output
   assign tv_out_ycrcb = 10'h0;
   assign tv_out_reset_b = 1'b0;
   assign tv_out_clock = 1'b0;
   assign tv_out_i2c_clock = 1'b0;
   assign tv_out_i2c_data = 1'b0;
   assign tv_out_pal_ntsc = 1'b0;
   assign tv_out_hsync_b = 1'b1;
   assign tv_out_vsync_b = 1'b1;
   assign tv_out_blank_b = 1'b1;
   assign tv_out_subcar_reset = 1'b0;
   
   // Video Input
   assign tv_in_i2c_clock = 1'b0;
   assign tv_in_fifo_read = 1'b0;
   assign tv_in_fifo_clock = 1'b0;
   assign tv_in_iso = 1'b0;
   assign tv_in_reset_b = 1'b0;
   assign tv_in_clock = 1'b0;
   assign tv_in_i2c_data = 1'bZ;
   
   // SRAMs
   assign ram0_data = 36'hZ;
   assign ram0_address = 21'h0;
   assign ram0_adv_ld = 1'b0;
   assign ram0_clk = 1'b0;
   assign ram0_cen_b = 1'b1;
   assign ram0_ce_b = 1'b1;
   assign ram0_oe_b = 1'b1;
   assign ram0_we_b = 1'b1;
   assign ram0_bwe_b = 4'hF;
   assign ram1_data = 36'hZ;
   assign ram1_address = 21'h0;
   assign ram1_adv_ld = 1'b0;
   assign ram1_clk = 1'b0;
   assign ram1_cen_b = 1'b1;
   assign ram1_ce_b = 1'b1;
   assign ram1_oe_b = 1'b1;
   assign ram1_we_b = 1'b1;
   assign ram1_bwe_b = 4'hF;
   assign clock_feedback_out = 1'b0;
   
   // Flash ROM
   assign flash_data = 16'hZ;
   assign flash_address = 15'h0;
   assign flash_ce_b = 1'b1;
   assign flash_oe_b = 1'b1;
   assign flash_we_b = 1'b1;
   assign flash_reset_b = 1'b0;
   assign flash_byte_b = 1'b1;

   // SystemACE Microprocessor Port
   assign systemace_data = 16'hZ;
   assign systemace_address = 7'h0;
   assign systemace_ce_b = 1'b1;
   assign systemace_we_b = 1'b1;
   assign systemace_oe_b = 1'b1;

endmodule