///////////////////////////////////////////////////////////////////////////////
//
// 6.111 FPGA Labkit -- I/O Test Program 2
//
// For Labkit Revision 004
//
//
// Created: January 24, 2005
// Author: Nathan Ickes
//
///////////////////////////////////////////////////////////////////////////////

`include "display.v"
`include "ps2.v"

module labkit (beep, audio_reset_b, ac97_sdata_out, ac97_sdata_in, ac97_synch,
	       ac97_bit_clock,
	       
	       vga_out_red, vga_out_green, vga_out_blue, vga_out_sync_b,
	       vga_out_blank_b, vga_out_pixel_clock, vga_out_hsync,
	       vga_out_vsync,

	       tv_out_ycrcb, tv_out_reset_b, tv_out_clock, tv_out_i2c_clock,
	       tv_out_i2c_data, tv_out_pal_ntsc, tv_out_hsync_b,
	       tv_out_vsync_b, tv_out_blank_b, tv_out_subcar_reset,

	       tv_in_ycrcb, tv_in_data_valid, tv_in_line_clock1,
	       tv_in_line_clock2, tv_in_aef, tv_in_hff, tv_in_aff,
	       tv_in_i2c_clock, tv_in_i2c_data, tv_in_fifo_read,
	       tv_in_fifo_clock, tv_in_iso, tv_in_reset_b, tv_in_clock,

	       ram0_data, ram0_address, ram0_adv_ld, ram0_clk, ram0_cen_b,
	       ram0_ce_b, ram0_oe_b, ram0_we_b, ram0_bwe_b, 

	       ram1_data, ram1_address, ram1_adv_ld, ram1_clk, ram1_cen_b,
	       ram1_ce_b, ram1_oe_b, ram1_we_b, ram1_bwe_b,

	       clock_feedback_out, clock_feedback_in,

	       flash_data, flash_address, flash_ce_b, flash_oe_b, flash_we_b,
	       flash_reset_b, flash_sts, flash_byte_b,

	       rs232_txd, rs232_rxd, rs232_rts, rs232_cts,

	       mouse_clock, mouse_data, keyboard_clock, keyboard_data,

	       clock_27mhz, clock1, clock2,

	       disp_blank, disp_data_out, disp_clock, disp_rs, disp_ce_b,
	       disp_reset_b, disp_data_in,

	       button0, button1, button2, button3, button_enter, button_right,
	       button_left, button_down, button_up,

	       switch,

	       led,
	       
	       user1, user2, user3, user4,
	       
	       daughtercard,

	       systemace_data, systemace_address, systemace_ce_b,
	       systemace_we_b, systemace_oe_b, systemace_irq, systemace_mpbrdy,
	       
	       analyzer1_data, analyzer1_clock,
 	       analyzer2_data, analyzer2_clock,
 	       analyzer3_data, analyzer3_clock,
 	       analyzer4_data, analyzer4_clock);

   output beep, audio_reset_b, ac97_synch, ac97_sdata_out;
   input  ac97_bit_clock, ac97_sdata_in;
   
   output [7:0] vga_out_red, vga_out_green, vga_out_blue;
   output vga_out_sync_b, vga_out_blank_b, vga_out_pixel_clock,
	  vga_out_hsync, vga_out_vsync;

   output [9:0] tv_out_ycrcb;
   output tv_out_reset_b, tv_out_clock, tv_out_i2c_clock, tv_out_i2c_data,
	  tv_out_pal_ntsc, tv_out_hsync_b, tv_out_vsync_b, tv_out_blank_b,
	  tv_out_subcar_reset;
   
   input  [19:0] tv_in_ycrcb;
   input  tv_in_data_valid, tv_in_line_clock1, tv_in_line_clock2, tv_in_aef,
	  tv_in_hff, tv_in_aff;
   output tv_in_i2c_clock, tv_in_fifo_read, tv_in_fifo_clock, tv_in_iso,
	  tv_in_reset_b, tv_in_clock;
   inout  tv_in_i2c_data;
        
   inout  [35:0] ram0_data;
   output [20:0] ram0_address;
   output ram0_adv_ld, ram0_clk, ram0_cen_b, ram0_ce_b, ram0_oe_b, ram0_we_b;
   output [3:0] ram0_bwe_b;
   
   inout  [35:0] ram1_data;
   output [20:0] ram1_address;
   output ram1_adv_ld, ram1_clk, ram1_cen_b, ram1_ce_b, ram1_oe_b, ram1_we_b;
   output [3:0] ram1_bwe_b;

   input  clock_feedback_in;
   output clock_feedback_out;
   
   inout  [15:0] flash_data;
   output [24:0] flash_address;
   output flash_ce_b, flash_oe_b, flash_we_b, flash_reset_b, flash_byte_b;
   input  flash_sts;
   
   output rs232_txd, rs232_rts;
   input  rs232_rxd, rs232_cts;

   input  mouse_clock, mouse_data, keyboard_clock, keyboard_data;

   input  clock_27mhz, clock1, clock2;

   output disp_blank, disp_clock, disp_rs, disp_ce_b, disp_reset_b;  
   output disp_data_out;
   input  disp_data_in;
   
   input  button0, button1, button2, button3, button_enter, button_right,
	  button_left, button_down, button_up;
   input  [7:0] switch;
   output [7:0] led;

   inout [31:0] user1, user2, user3, user4;
   
   inout [43:0] daughtercard;

   inout  [15:0] systemace_data;
   output [6:0]  systemace_address;
   output systemace_ce_b, systemace_we_b, systemace_oe_b;
   input  systemace_irq, systemace_mpbrdy;

   inout [15:0] analyzer1_data, analyzer2_data, analyzer3_data, 
		analyzer4_data;
   inout analyzer1_clock, analyzer2_clock, analyzer3_clock, analyzer4_clock;

   ////////////////////////////////////////////////////////////////////////////
   //
   // Clocks
   //
   ////////////////////////////////////////////////////////////////////////////

   // synthesis attribute period of clock_27mhz is 37ns;

   wire fclock;
   DCM fclock_dcm (.CLKIN(clock_27mhz), .CLKFX(fclock));
   // synthesis attribute CLKFX_MULTIPLY of fclock_dcm is 4;
   // synthesis attribute CLKFX_DIVIDE of fclock_dcm is 1;

   ////////////////////////////////////////////////////////////////////////////
   //
   // Reset Generation
   //
   // A shift register primitive is used to generate an active-high reset
   // signal that remains high for 16 clock cycles after configuration finishes
   // and the FPGA's internal clocks begin toggling.
   //
   ////////////////////////////////////////////////////////////////////////////

   wire reset;
   SRL16 reset_sr (.D(1'b0), .CLK(clock_27mhz), .Q(reset),
		   .A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1));
   defparam reset_sr.INIT = 16'hFFFF;

   reg freset;
   always @(posedge fclock)
     freset <= reset;
   
   ////////////////////////////////////////////////////////////////////////////
   //
   // LED, Switch, and Pushbutton Test Logic
   //
   ////////////////////////////////////////////////////////////////////////////
   
   reg [7:0] led;
   reg [31:0] blink_counter;
   reg blink;

   always @(posedge clock_27mhz)
     if (reset)
       begin
	  blink_counter = 0;
	  blink = 0;
       end
     else if (blink_counter == 1350000)
       begin
	  blink = !blink;
	  blink_counter = 0;
       end
     else
       blink_counter = blink_counter+1;

   always @(blink or switch or button_enter or button_up or button_down 
	    or button_left or button_right or button0 or button1 or button2
	    or button3)
     if (!button_enter)
       led <= 8'h00;
     else
       begin
	  led[0] <= button0      ? !switch[0] : blink;
	  led[1] <= button1      ? !switch[1] : blink;
	  led[2] <= button2      ? !switch[2] : blink;
	  led[3] <= button3      ? !switch[3] : blink;
	  led[4] <= button_right ? !switch[4] : blink;
	  led[5] <= button_left  ? !switch[5] : blink;
	  led[6] <= button_down  ? !switch[6] : blink;
	  led[7] <= button_up    ? !switch[7] : blink;
       end	  
   
   ////////////////////////////////////////////////////////////////////////////
   //
   // Logic Analyzer, User I/O, and Daughtercard Test Logic
   //
   ////////////////////////////////////////////////////////////////////////////

   reg [43:0] iodata;
   
   always @(posedge fclock)
     if (freset)
       iodata <= 1;
     else
       iodata <= {iodata[42:0], iodata[43]};

   assign user1 = iodata[31:0];
   assign user2 = iodata[32:1];
   assign user3 = iodata[33:2];
   assign user4 = iodata[34:3];

   assign daughtercard = iodata;
   
   assign analyzer1_clock = fclock;
   assign analyzer1_data = iodata[15:0];
   assign analyzer2_clock = fclock;
   assign analyzer2_data = iodata[19:4];
   assign analyzer3_clock = fclock;
   assign analyzer3_data = iodata[23:8];
   assign analyzer4_clock = fclock;
   assign analyzer4_data = iodata[27:12];
   
   wire [79:0] gpiodots;
   assign gpiodots = {40'b00000000_00000000_00000000_00000000_00000000,
		      40'b00000000_00000000_00000000_00000000_00000000};

   ////////////////////////////////////////////////////////////////////////////
   //
   // Oscillator Sockets Test Logic
   //
   ////////////////////////////////////////////////////////////////////////////

   reg [15:0] phase_counter;
   reg [1:0]  phases1, phases2;
   reg [39:0] clock1_dots, clock2_dots;
   
   always @(posedge clock_27mhz)
     begin
	if (phase_counter == 0)
	  begin
	     phases1 <= 0;
	     phases2 <= 0;
	  end
	else
	  begin
	     if (clock1)
	       phases1[0] <= 1;
	     else
	       phases1[1] <= 1;
	     if (clock2)
	       phases2[0] <= 1;
	     else
	       phases2[1] <= 1;
	  end
	phase_counter = phase_counter+1;
     end

   always @(phases1)
     case (phases1)
       2'b00: clock1_dots <= 40'b00001000_00001000_00001000_00001000_00001000;
       2'b01: clock1_dots <= 40'b00010000_00100000_01111111_00100000_00010000;
       2'b10: clock1_dots <= 40'b00000100_00000010_11111111_00000010_00000100;
       2'b11: clock1_dots <= 40'b00010100_00100010_01111111_00100010_00010100;
     endcase

   always @(phases2)
     case (phases2)
       2'b00: clock2_dots <= 40'b00001000_00001000_00001000_00001000_00001000;
       2'b01: clock2_dots <= 40'b00010000_00100000_01111111_00100000_00010000;
       2'b10: clock2_dots <= 40'b00000100_00000010_11111111_00000010_00000100;
       2'b11: clock2_dots <= 40'b00010100_00100010_01111111_00100010_00010100;
     endcase

   ////////////////////////////////////////////////////////////////////////////
   //
   // RS-232 Interface Test Logic
   //
   ////////////////////////////////////////////////////////////////////////////

   // Trivial loopback logic, with flow control
   assign rs232_txd = rs232_rxd;
   assign rs232_rts = rs232_cts;

   ////////////////////////////////////////////////////////////////////////////
   //
   // PS/2 Interface Test Logic
   //
   ////////////////////////////////////////////////////////////////////////////

   wire [39:0] mouse_dots, keyboard_dots;
   
   ps2 ps2_mouse (.clock(mouse_clock), 
		  .data(mouse_data),
		  .reset(!button_enter),
		  .disp(mouse_dots));
   
   ps2 ps2_keyboard (.clock(keyboard_clock),
		     .data(keyboard_data),
		     .reset(!button_enter),
		     .disp(keyboard_dots));
   
   ////////////////////////////////////////////////////////////////////////////
   //
   // Alphanumeric displays
   //
   ////////////////////////////////////////////////////////////////////////////
   //
   // 0123456701234567
   // K:A M:A C:||  12
   //
   
   wire [639:0] dots;

   assign dots = { 40'b01111111_00001000_00010100_00100010_01000001, // 'K'
		   40'b00000000_00110110_00110110_00000000_00000000, // ':'
		   keyboard_dots,
		   40'b00000000_00000000_00000000_00000000_00000000, // ' '
		   40'b01111111_00000010_00001100_00000010_01111111, // 'M'
		   40'b00000000_00110110_00110110_00000000_00000000, // ':'
		   mouse_dots,
		   40'b00000000_00000000_00000000_00000000_00000000, // ' '
		   40'b00111110_01000001_01000001_01000001_00100010, // 'C'
		   40'b00000000_00110110_00110110_00000000_00000000, // ':'
		   clock1_dots,
		   clock2_dots,
		   40'b00000000_00000000_00000000_00000000_00000000, // ' '
		   40'b00000000_00000000_00000000_00000000_00000000, // ' '
		   gpiodots
		   };
         
   display disp (reset, clock_27mhz, disp_blank, disp_clock, disp_rs,
		 disp_ce_b, disp_reset_b, disp_data_out, dots);
   
   ////////////////////////////////////////////////////////////////////////////
   //
   // Default I/O Assignments
   //
   ////////////////////////////////////////////////////////////////////////////

   // Audio Input and Output
   assign beep= 1'b0;
   assign audio_reset_b = 1'b0;
   assign ac97_synch = 1'b0;

   // VGA Output
   assign vga_out_red = 10'h0;
   assign vga_out_green = 10'h0;
   assign vga_out_blue = 10'h0;
   assign vga_out_sync_b = 1'b1;
   assign vga_out_blank_b = 1'b1;
   assign vga_out_pixel_clock = 1'b0;
   assign vga_out_hsync = 1'b0;
   assign vga_out_vsync = 1'b0;

   // Video Output
   assign tv_out_ycrcb = 10'h0;
   assign tv_out_reset_b = 1'b0;
   assign tv_out_clock = 1'b0;
   assign tv_out_i2c_clock = 1'b0;
   assign tv_out_i2c_data = 1'b0;
   assign tv_out_pal_ntsc = 1'b0;
   assign tv_out_hsync_b = 1'b1;
   assign tv_out_vsync_b = 1'b1;
   assign tv_out_blank_b = 1'b1;
   assign tv_out_subcar_reset = 1'b0;
   
   // Video Input
   assign tv_in_i2c_clock = 1'b0;
   assign tv_in_fifo_read = 1'b0;
   assign tv_in_fifo_clock = 1'b0;
   assign tv_in_iso = 1'b0;
   assign tv_in_reset_b = 1'b0;
   assign tv_in_clock = 1'b0;
   assign tv_in_i2c_data = 1'bZ;
   
   // SRAMs
   assign ram0_data = 36'hZ;
   assign ram0_address = 21'h0;
   assign ram0_adv_ld = 1'b0;
   assign ram0_clk = 1'b0;
   assign ram0_cen_b = 1'b1;
   assign ram0_ce_b = 1'b1;
   assign ram0_oe_b = 1'b1;
   assign ram0_we_b = 1'b1;
   assign ram0_bwe_b = 4'hF;
   assign ram1_data = 36'hZ;
   assign ram1_address = 21'h0;
   assign ram1_adv_ld = 1'b0;
   assign ram1_clk = 1'b0;
   assign ram1_cen_b = 1'b1;
   assign ram1_ce_b = 1'b1;
   assign ram1_oe_b = 1'b1;
   assign ram1_we_b = 1'b1;
   assign ram1_bwe_b = 4'hF;
   assign clock_feedback_out = 1'b0;
   
   // Flash ROM
   assign flash_data = 16'hZ;
   assign flash_address = 15'h0;
   assign flash_ce_b = 1'b1;
   assign flash_oe_b = 1'b1;
   assign flash_we_b = 1'b1;
   assign flash_reset_b = 1'b0;
   assign flash_byte_b = 1'b1;

   // SystemACE Microprocessor Port
   assign systemace_data = 16'hZ;
   assign systemace_address = 7'h0;
   assign systemace_ce_b = 1'b1;
   assign systemace_we_b = 1'b1;
   assign systemace_oe_b = 1'b1;

endmodule