module ps2 (reset, clock, data, disp);

   input reset; // Active high asynchronous reset
   input clock; // PS/2 clock
   input data; // PS/2 data
   output [39:0] disp; // Bitmap for display (1 character)
   
   reg [7:0] keycode;
   reg [39:0] disp;
   reg [3:0] state;

   always @(negedge clock or posedge reset)
     begin
	if (reset)
	  begin
	     state <= 0;
	     keycode <= 0;
	  end
	else		     
	  case(state)
	    4'd0: begin
	       // Idle
	       if (! data)
		 state <= 1; // Detected start bit
	    end
	    4'd1: begin
	       // Bit 0
	       keycode[0] <= data;
	       state <= state+1;
	    end
	    4'd2: begin
	       // Bit 1
	       keycode[1] <= data;
	       state <= state+1;
	    end
	    4'd3: begin
	       // Bit 2
	       keycode[2] <= data;
	       state <= state+1;
	    end
	    4'd4: begin
	       // Bit 3
	       keycode[3] <= data;
	       state <= state+1;
	    end
	    4'd5: begin
	       // Bit 4
	       keycode[4] <= data;
	       state <= state+1;
	    end
	    4'd6: begin
	       // Bit 5
	       keycode[5] <= data;
	       state <= state+1;
	    end
	    4'd7: begin
	       // Bit 6
	       keycode[6] <= data;
	       state <= state+1;
	    end
	    4'd8: begin
	       // Bit 7
	       keycode[7] <= data;
	       state <= state+1;
	    end
	    4'd9: begin
	       // Parity
	       state <= state+1;
	    end
	    4'd10: begin
	       // Stop bit
	       state <= 0;
	    end
	  endcase
     end

   always @(keycode)
     case (keycode)
       8'h1C: disp <= 40'b0111111000001001000010010000100101111110;
       8'h32: disp <= 40'b0111111101001001010010010100100100110110;
       8'h21: disp <= 40'b0011111001000001010000010100000100100010;
       8'h23: disp <= 40'b0111111101000001010000010100000100111110;
       8'h24: disp <= 40'b0111111101001001010010010100100101000001;
       8'h2B: disp <= 40'b0111111100001001000010010000100100000001;
       default: disp <= 40'b0000001000000001010100010000100100000110;
     endcase
   
endmodule