module fsm (reset, clock, go, state);
   input reset;
   input clock;
   input go;
   output [1:0] state;

   reg [1:0] state;

   always @(posedge clock)
     if (reset)
       state <= 0;
     else
       case (state)
	 2'h0: state <= go ? 2'h1 : 2'h0;
	 2'h1: state <= 2'h2;
	 2'h2: state <= 2'h3;
	 2'h3: state <= 2'h0;
       endcase

endmodule