`timescale 1 ns / 1 ns

module tb;

   reg reset;
   reg clock;
   reg go;
   wire [1:0] state;

   // Instantiate the unit-under-test
   fsm uut (.reset(reset), .clock(clock), .go(go), .state(state));

   // Generate the clock
   initial clock <= 0;
   always #5 clock <= !clock; // 5ns half-period = 100MHz
   
   integer i;
   
   initial
     begin
	#100; // Wait for FPGA to come out of reset (GSR clear)
	go <= 0;
	reset <= 1; // Assert reset
	@(negedge clock); // Wait for two falling clock edges
	@(negedge clock);
	reset <= 0; // Release reset
	@(negedge clock);
	if (state !== 2'h0)
	  $display("%t: ERROR: FSM not reset!", $time);
	@(negedge clock);
	go <= 1;
	@(negedge clock);
	go <= 0;

	// Verify that <state> advances properly
	for (i=1; i<4; i=i+1)
	  begin
	     if (state !== i)
	       $display("%t: ERROR: FSM in state %d, expected %d!",
			$time, state, i);
	     @(negedge clock);
	  end

	// Verify that <state> stays zero while <go> is not asserted
	for (i=0; i<4; i=i+1)
	  begin
	     if (state !== 2'h0)
	       $display("%t: ERROR: FSM in state %d, expected %d!",
			$time, state, 0);
	     @(negedge clock);
	  end
	$stop; // Pasue simulation
	
     end

endmodule