############################################################################### # # 6.111 FPGA Labkit -- Constraints File # # For Labkit Revision 003 # # # Created: Mar 15, 2004 from revision 002 contraints file # Author: Nathan Ickes and Isaac Cambron # ############################################################################### # # CHANGES FOR BOARD REVISION 003 # # 1) Combined flash chip enables into a single signal, flash_ce_b. # 2) Moved SRAM feedback clock loop to FPGA pins AL28 (out) and AJ16 (in). # 3) Moved rs232_rts to FPGA pin R3. # # CHANGES FOR BOARD REVISION 002 # # 1) Moved ZBT_BANK1_CLK signal to pin Y9. # 2) Moved user1<30> to J14. # 3) Moved user3<29> to J13. # 4) Added SRAM clock feedback loop between D15 and H15. # 5) Renamed ram#_parity and ram#_we#_b signals. # 6) Removed the constraint on "systemace_clock", since this net no longer # exists. The SystemACE clock is now hardwired to the 27MHz oscillator # on the PCB. # ############################################################################### # # Complete change history (including bug fixes) # # 2004-Apr-29: Change history started # # 2004-Arp-29: Removed constraints for ramX_address[20:19]. The SRAMs actually # populated on the boards are 18Mb devices with only 19 address # lines. # ############################################################################### # Audio CODEC # net "beep" loc="ac19" | slow | iostandard=lvdci_33; net "audio_reset_b" loc="ae18" | fast | iostandard=lvttl; net "ac97_sdata_out" loc="ac18" | slow | iostandard=lvdci_33; net "ac97_sdata_in" loc="aj24"; net "ac97_synch" loc="ac17" | slow | iostandard=lvdci_33; net "ac97_bit_clock" loc="ah24"; # # VGA Output # net "vga_out_red<7>" loc="ae9" | fast | iostandard=lvdci_33; net "vga_out_red<6>" loc="ae8" | fast | iostandard=lvdci_33; net "vga_out_red<5>" loc="ad12" | fast | iostandard=lvdci_33; net "vga_out_red<4>" loc="af8" | fast | iostandard=lvdci_33; net "vga_out_red<3>" loc="af9" | fast | iostandard=lvdci_33; net "vga_out_red<2>" loc="ag9" | fast | iostandard=lvdci_33; net "vga_out_red<1>" loc="ag10" | fast | iostandard=lvdci_33; net "vga_out_red<0>" loc="af11" | fast | iostandard=lvdci_33; net "vga_out_green<7>" loc="ah8" | fast | iostandard=lvdci_33; net "vga_out_green<6>" loc="ah7" | fast | iostandard=lvdci_33; net "vga_out_green<5>" loc="aj6" | fast | iostandard=lvdci_33; net "vga_out_green<4>" loc="ah6" | fast | iostandard=lvdci_33; net "vga_out_green<3>" loc="ad15" | fast | iostandard=lvdci_33; net "vga_out_green<2>" loc="ac14" | fast | iostandard=lvdci_33; net "vga_out_green<1>" loc="ag8" | fast | iostandard=lvdci_33; net "vga_out_green<0>" loc="ac12" | fast | iostandard=lvdci_33; net "vga_out_blue<7>" loc="ag15" | fast | iostandard=lvdci_33; net "vga_out_blue<6>" loc="ag14" | fast | iostandard=lvdci_33; net "vga_out_blue<5>" loc="ag13" | fast | iostandard=lvdci_33; net "vga_out_blue<4>" loc="ag12" | fast | iostandard=lvdci_33; net "vga_out_blue<3>" loc="aj11" | fast | iostandard=lvdci_33; net "vga_out_blue<2>" loc="ah11" | fast | iostandard=lvdci_33; net "vga_out_blue<1>" loc="aj10" | fast | iostandard=lvdci_33; net "vga_out_blue<0>" loc="ah9" | fast | iostandard=lvdci_33; net "vga_out_sync_b" loc="aj9" | fast | iostandard=lvdci_33; net "vga_out_blank_b" loc="aj8" | fast | iostandard=lvdci_33; net "vga_out_pixel_clock" loc="ac10" | fast | iostandard=lvdci_33; net "vga_out_hsync" loc="ac13" | fast | iostandard=lvdci_33; net "vga_out_vsync" loc="ac11" | fast | iostandard=lvdci_33; # # Video Output # net "tv_out_ycrcb<9>" loc = "p27" | slow | iostandard=lvdci_33; net "tv_out_ycrcb<8>" loc = "r27" | slow | iostandard=lvdci_33; net "tv_out_ycrcb<7>" loc = "t29" | slow | iostandard=lvdci_33; net "tv_out_ycrcb<6>" loc = "h26" | slow | iostandard=lvdci_33; net "tv_out_ycrcb<5>" loc = "j26" | slow | iostandard=lvdci_33; net "tv_out_ycrcb<4>" loc = "l26" | slow | iostandard=lvdci_33; net "tv_out_ycrcb<3>" loc = "m26" | slow | iostandard=lvdci_33; net "tv_out_ycrcb<2>" loc = "n26" | slow | iostandard=lvdci_33; net "tv_out_ycrcb<1>" loc = "p26" | slow | iostandard=lvdci_33; net "tv_out_ycrcb<0>" loc = "r26" | slow | iostandard=lvdci_33; net "tv_out_reset_b" loc = "g27" | slow | iostandard=lvdci_33; net "tv_out_clock" loc = "l27" | slow | iostandard=lvdci_33; net "tv_out_sclk" loc = "j27" | slow | iostandard=lvdci_33; net "tv_out_data" loc = "h27" | slow | iostandard=lvdci_33; net "tv_out_pal_ntsc" loc = "j25" | slow | iostandard=lvdci_33; net "tv_out_hsync_b" loc = "n27" | slow | iostandard=lvdci_33; net "tv_out_vsync_b" loc = "m27" | slow | iostandard=lvdci_33; net "tv_out_blank_b" loc = "h25" | slow | iostandard=lvdci_33; net "tv_out_subcar_reset" loc = "k27" | slow | iostandard=lvdci_33; # # Video Input # net "tv_in_ycrcb<9>" loc = "ag17"; net "tv_in_ycrcb<8>" loc = "ag18"; net "tv_in_ycrcb<7>" loc = "ag19"; net "tv_in_ycrcb<6>" loc = "ag20"; net "tv_in_ycrcb<5>" loc = "ae20"; net "tv_in_ycrcb<4>" loc = "af21"; net "tv_in_ycrcb<3>" loc = "ad20"; net "tv_in_ycrcb<2>" loc = "ag23"; net "tv_in_ycrcb<1>" loc = "ah26"; net "tv_in_ycrcb<0>" loc = "aj26"; net "tv_in_data_valid" loc = "ah25"; net "tv_in_line_clock1" loc = "ad16" | slow | iostandard=lvdci_33; net "tv_in_line_clock2" loc = "ad17" | slow | iostandard=lvdci_33; net "tv_in_aef" loc = "aj23"; net "tv_in_hff" loc = "ah23"; net "tv_in_aff" loc = "aj22"; net "tv_in_i2c_clock" loc = "ad21" | slow | iostandard=lvdci_33; net "tv_in_i2c_data" loc = "ad19" | slow | iostandard=lvdci_33; net "tv_in_fifo_read" loc = "ac22" | slow | iostandard=lvdci_33; net "tv_in_fifo_clock" loc = "ag22" | slow | iostandard=lvdci_33; net "tv_in_iso" loc = "aj27" | slow | iostandard=lvdci_33; net "tv_in_reset_b" loc = "ag25" | slow | iostandard=lvdci_33; net "tv_in_clock" loc = "ab21" | slow | iostandard=lvdci_33; # # SRAMs # net "ram0_data<35>" loc="ab25" | fast | iostandard=lvdci_33 | nodelay; net "ram0_data<34>" loc="ah29" | fast | iostandard=lvdci_33 | nodelay; net "ram0_data<33>" loc="ag28" | fast | iostandard=lvdci_33 | nodelay; net "ram0_data<32>" loc="ag29" | fast | iostandard=lvdci_33 | nodelay; net "ram0_data<31>" loc="af27" | fast | iostandard=lvdci_33 | nodelay; net "ram0_data<30>" loc="af29" | fast | iostandard=lvdci_33 | nodelay; net "ram0_data<29>" loc="af28" | fast | iostandard=lvdci_33 | nodelay; net "ram0_data<28>" loc="ae28" | fast | iostandard=lvdci_33 | nodelay; net "ram0_data<27>" loc="ad25" | fast | iostandard=lvdci_33 | nodelay; net "ram0_data<26>" loc="aa25" | fast | iostandard=lvdci_33 | nodelay; net "ram0_data<25>" loc="ah30" | fast | iostandard=lvdci_33 | nodelay; net "ram0_data<24>" loc="ah31" | fast | iostandard=lvdci_33 | nodelay; net "ram0_data<23>" loc="ag30" | fast | iostandard=lvdci_33 | nodelay; net "ram0_data<22>" loc="ag31" | fast | iostandard=lvdci_33 | nodelay; net "ram0_data<21>" loc="af30" | fast | iostandard=lvdci_33 | nodelay; net "ram0_data<20>" loc="af31" | fast | iostandard=lvdci_33 | nodelay; net "ram0_data<19>" loc="ae30" | fast | iostandard=lvdci_33 | nodelay; net "ram0_data<18>" loc="ae31" | fast | iostandard=lvdci_33 | nodelay; net "ram0_data<17>" loc="y27" | fast | iostandard=lvdci_33 | nodelay; net "ram0_data<16>" loc="aa28" | fast | iostandard=lvdci_33 | nodelay; net "ram0_data<15>" loc="y29" | fast | iostandard=lvdci_33 | nodelay; net "ram0_data<14>" loc="y28" | fast | iostandard=lvdci_33 | nodelay; net "ram0_data<13>" loc="w29" | fast | iostandard=lvdci_33 | nodelay; net "ram0_data<12>" loc="w28" | fast | iostandard=lvdci_33 | nodelay; net "ram0_data<11>" loc="v28" | fast | iostandard=lvdci_33 | nodelay; net "ram0_data<10>" loc="u29" | fast | iostandard=lvdci_33 | nodelay; net "ram0_data<9>" loc="u28" | fast | iostandard=lvdci_33 | nodelay; net "ram0_data<8>" loc="aa27" | fast | iostandard=lvdci_33 | nodelay; net "ram0_data<7>" loc="ad31" | fast | iostandard=lvdci_33 | nodelay; net "ram0_data<6>" loc="ac30" | fast | iostandard=lvdci_33 | nodelay; net "ram0_data<5>" loc="ac31" | fast | iostandard=lvdci_33 | nodelay; net "ram0_data<4>" loc="ab30" | fast | iostandard=lvdci_33 | nodelay; net "ram0_data<3>" loc="ab31" | fast | iostandard=lvdci_33 | nodelay; net "ram0_data<2>" loc="aa30" | fast | iostandard=lvdci_33 | nodelay; net "ram0_data<1>" loc="aa31" | fast | iostandard=lvdci_33 | nodelay; net "ram0_data<0>" loc="y30" | fast | iostandard=lvdci_33 | nodelay; net "ram0_address<20>" loc="ac29" | fast | iostandard=lvdci_33; net "ram0_address<19>" loc="ac28" | fast | iostandard=lvdci_33; net "ram0_address<18>" loc="v31" | fast | iostandard=lvdci_33; net "ram0_address<17>" loc="w31" | fast | iostandard=lvdci_33; net "ram0_address<16>" loc="ad28" | fast | iostandard=lvdci_33; net "ram0_address<15>" loc="ad29" | fast | iostandard=lvdci_33; net "ram0_address<14>" loc="ac24" | fast | iostandard=lvdci_33; net "ram0_address<13>" loc="ad26" | fast | iostandard=lvdci_33; net "ram0_address<12>" loc="ad27" | fast | iostandard=lvdci_33; net "ram0_address<11>" loc="ac27" | fast | iostandard=lvdci_33; net "ram0_address<10>" loc="ab27" | fast | iostandard=lvdci_33; net "ram0_address<9>" loc="y31" | fast | iostandard=lvdci_33; net "ram0_address<8>" loc="w30" | fast | iostandard=lvdci_33; net "ram0_address<7>" loc="y26" | fast | iostandard=lvdci_33; net "ram0_address<6>" loc="y25" | fast | iostandard=lvdci_33; net "ram0_address<5>" loc="ab24" | fast | iostandard=lvdci_33; net "ram0_address<4>" loc="ac25" | fast | iostandard=lvdci_33; net "ram0_address<3>" loc="aa26" | fast | iostandard=lvdci_33; net "ram0_address<2>" loc="aa24" | fast | iostandard=lvdci_33; net "ram0_address<1>" loc="ab29" | fast | iostandard=lvdci_33; net "ram0_address<0>" loc="ac26" | fast | iostandard=lvdci_33; net "ram0_adv_ld" loc="v26" | fast | iostandard=lvdci_33; net "ram0_clk" loc="u30" | fast | iostandard=lvdci_33; net "ram0_cen_b" loc="u25" | fast | iostandard=lvdci_33; net "ram0_ce_b" loc="w26" | fast | iostandard=lvdci_33; net "ram0_oe_b" loc="v25" | fast | iostandard=lvdci_33; net "ram0_we_b" loc="u31" | fast | iostandard=lvdci_33; net "ram0_bwe_b<0>" loc="v27" | fast | iostandard=lvdci_33; net "ram0_bwe_b<1>" loc="u27" | fast | iostandard=lvdci_33; net "ram0_bwe_b<2>" loc="w27" | fast | iostandard=lvdci_33; net "ram0_bwe_b<3>" loc="u26" | fast | iostandard=lvdci_33; net "ram1_data<35>" loc="aa9" | fast | iostandard=lvdci_33 | nodelay; net "ram1_data<34>" loc="ah2" | fast | iostandard=lvdci_33 | nodelay; net "ram1_data<33>" loc="ah1" | fast | iostandard=lvdci_33 | nodelay; net "ram1_data<32>" loc="ag2" | fast | iostandard=lvdci_33 | nodelay; net "ram1_data<31>" loc="ag1" | fast | iostandard=lvdci_33 | nodelay; net "ram1_data<30>" loc="af2" | fast | iostandard=lvdci_33 | nodelay; net "ram1_data<29>" loc="af1" | fast | iostandard=lvdci_33 | nodelay; net "ram1_data<28>" loc="ae2" | fast | iostandard=lvdci_33 | nodelay; net "ram1_data<27>" loc="ae1" | fast | iostandard=lvdci_33 | nodelay; net "ram1_data<26>" loc="ab9" | fast | iostandard=lvdci_33 | nodelay; net "ram1_data<25>" loc="ah3" | fast | iostandard=lvdci_33 | nodelay; net "ram1_data<24>" loc="ag4" | fast | iostandard=lvdci_33 | nodelay; net "ram1_data<23>" loc="ag3" | fast | iostandard=lvdci_33 | nodelay; net "ram1_data<22>" loc="af4" | fast | iostandard=lvdci_33 | nodelay; net "ram1_data<21>" loc="af3" | fast | iostandard=lvdci_33 | nodelay; net "ram1_data<20>" loc="ae4" | fast | iostandard=lvdci_33 | nodelay; net "ram1_data<19>" loc="ae5" | fast | iostandard=lvdci_33 | nodelay; net "ram1_data<18>" loc="ad5" | fast | iostandard=lvdci_33 | nodelay; net "ram1_data<17>" loc="v2" | fast | iostandard=lvdci_33 | nodelay; net "ram1_data<16>" loc="ad1" | fast | iostandard=lvdci_33 | nodelay; net "ram1_data<15>" loc="ac2" | fast | iostandard=lvdci_33 | nodelay; net "ram1_data<14>" loc="ac1" | fast | iostandard=lvdci_33 | nodelay; net "ram1_data<13>" loc="ab2" | fast | iostandard=lvdci_33 | nodelay; net "ram1_data<12>" loc="ab1" | fast | iostandard=lvdci_33 | nodelay; net "ram1_data<11>" loc="aa2" | fast | iostandard=lvdci_33 | nodelay; net "ram1_data<10>" loc="aa1" | fast | iostandard=lvdci_33 | nodelay; net "ram1_data<9>" loc="y2" | fast | iostandard=lvdci_33 | nodelay; net "ram1_data<8>" loc="v4" | fast | iostandard=lvdci_33 | nodelay; net "ram1_data<7>" loc="ac3" | fast | iostandard=lvdci_33 | nodelay; net "ram1_data<6>" loc="ac4" | fast | iostandard=lvdci_33 | nodelay; net "ram1_data<5>" loc="aa5" | fast | iostandard=lvdci_33 | nodelay; net "ram1_data<4>" loc="aa3" | fast | iostandard=lvdci_33 | nodelay; net "ram1_data<3>" loc="aa4" | fast | iostandard=lvdci_33 | nodelay; net "ram1_data<2>" loc="y3" | fast | iostandard=lvdci_33 | nodelay; net "ram1_data<1>" loc="y4" | fast | iostandard=lvdci_33 | nodelay; net "ram1_data<0>" loc="w3" | fast | iostandard=lvdci_33 | nodelay; net "ram1_address<20>" loc="ac7" | fast | iostandard=lvdci_33; net "ram1_address<19>" loc="ad6" | fast | iostandard=lvdci_33; net "ram1_address<18>" loc="ab3" | fast | iostandard=lvdci_33; net "ram1_address<17>" loc="ac5" | fast | iostandard=lvdci_33; net "ram1_address<16>" loc="u6" | fast | iostandard=lvdci_33; net "ram1_address<15>" loc="v6" | fast | iostandard=lvdci_33; net "ram1_address<14>" loc="w6" | fast | iostandard=lvdci_33; net "ram1_address<13>" loc="y6" | fast | iostandard=lvdci_33; net "ram1_address<12>" loc="aa7" | fast | iostandard=lvdci_33; net "ram1_address<11>" loc="ab7" | fast | iostandard=lvdci_33; net "ram1_address<10>" loc="ac6" | fast | iostandard=lvdci_33; net "ram1_address<9>" loc="ad3" | fast | iostandard=lvdci_33; net "ram1_address<8>" loc="ad4" | fast | iostandard=lvdci_33; net "ram1_address<7>" loc="u3" | fast | iostandard=lvdci_33; net "ram1_address<6>" loc="w4" | fast | iostandard=lvdci_33; net "ram1_address<5>" loc="ac8" | fast | iostandard=lvdci_33; net "ram1_address<4>" loc="ab8" | fast | iostandard=lvdci_33; net "ram1_address<3>" loc="aa8" | fast | iostandard=lvdci_33; net "ram1_address<2>" loc="y7" | fast | iostandard=lvdci_33; net "ram1_address<1>" loc="y8" | fast | iostandard=lvdci_33; net "ram1_address<0>" loc="ad7" | fast | iostandard=lvdci_33; net "ram1_adv_ld" loc="y5" | fast | iostandard=lvdci_33; net "ram1_clk" loc="y9" | fast | iostandard=lvdci_33; net "ram1_cen_b" loc="v5" | fast | iostandard=lvdci_33; net "ram1_ce_b" loc="u4" | fast | iostandard=lvdci_33; net "ram1_oe_b" loc="w5" | fast | iostandard=lvdci_33; net "ram1_we_b" loc="aa6" | fast | iostandard=lvdci_33; net "ram1_bwe_b<0>" loc="u2" | fast | iostandard=lvdci_33; net "ram1_bwe_b<1>" loc="u1" | fast | iostandard=lvdci_33; net "ram1_bwe_b<2>" loc="v1" | fast | iostandard=lvdci_33; net "ram1_bwe_b<3>" loc="u5" | fast | iostandard=lvdci_33; net "clock_feedback_out" loc="al28" | fast | iostandard=lvdci_33; net "clock_feedback_in" loc="aj16"; # # Flash # net "flash_data<15>" loc="ak10" | slow | iostandard=lvttl; net "flash_data<14>" loc="ak11" | slow | iostandard=lvttl; net "flash_data<13>" loc="ak12" | slow | iostandard=lvttl; net "flash_data<12>" loc="ak13" | slow | iostandard=lvttl; net "flash_data<11>" loc="ak14" | slow | iostandard=lvttl; net "flash_data<10>" loc="ak15" | slow | iostandard=lvttl; net "flash_data<9>" loc="ah12" | slow | iostandard=lvttl; net "flash_data<8>" loc="ah13" | slow | iostandard=lvttl; net "flash_data<7>" loc="al10" | slow | iostandard=lvttl; net "flash_data<6>" loc="al11" | slow | iostandard=lvttl; net "flash_data<5>" loc="al12" | slow | iostandard=lvttl; net "flash_data<4>" loc="al13" | slow | iostandard=lvttl; net "flash_data<3>" loc="al14" | slow | iostandard=lvttl; net "flash_data<2>" loc="al15" | slow | iostandard=lvttl; net "flash_data<1>" loc="aj12" | slow | iostandard=lvttl; net "flash_data<0>" loc="aj13" | slow | iostandard=lvttl; net "flash_address<24>" loc="al7"; net "flash_address<23>" loc="aj15"; net "flash_address<22>" loc="al25"; net "flash_address<21>" loc="ak23"; net "flash_address<20>" loc="al23"; net "flash_address<19>" loc="ak22"; net "flash_address<18>" loc="al22"; net "flash_address<17>" loc="ak21"; net "flash_address<16>" loc="al21"; net "flash_address<15>" loc="ak20"; net "flash_address<14>" loc="al20"; net "flash_address<13>" loc="ak19"; net "flash_address<12>" loc="al19"; net "flash_address<11>" loc="al18"; net "flash_address<10>" loc="ak17"; net "flash_address<9>" loc="al17"; net "flash_address<8>" loc="ah21"; net "flash_address<7>" loc="aj20"; net "flash_address<6>" loc="ah20"; net "flash_address<5>" loc="aj19"; net "flash_address<4>" loc="ah19"; net "flash_address<3>" loc="ah18"; net "flash_address<2>" loc="aj17"; net "flash_address<1>" loc="ah17"; net "flash_address<0>" loc="ah14"; net "flash_ce_b" loc="aj21" | slow | iostandard=lvdci_33; net "flash_oe_b" loc="ak9" | slow | iostandard=lvdci_33; net "flash_we_b" loc="al8" | slow | iostandard=lvdci_33; net "flash_reset_b" loc="ak18" | slow | iostandard=lvdci_33; net "flash_sts" loc="al9"; net "flash_byte_b" loc="ah15" | slow | iostandard=lvdci_33; # # RS-232 # net "rs232_txd" loc="p4" | slow | iostandard=lvdci_33; net "rs232_rxd" loc="p6"; net "rs232_rts" loc="r3" | slow | iostandard=lvdci_33; net "rs232_cts" loc="n8"; # # Mouse and Keyboard # net "mouse_clock" loc="ac16"; net "mouse_data" loc="ac15"; net "keyboard_clock" loc="ag16"; net "keyboard_data" loc="af16"; # # Clocks # net "clock_27mhz" loc="c16"; net "clock1" loc="h16"; net "clock2" loc="c15"; # # Alphanumeric Display # net "disp_blank" loc="af12" | slow | iostandard=lvdci_33; net "disp_data_out" loc="ae12"; net "disp_clock" loc="af14" | slow | iostandard=lvdci_33; net "disp_rs" loc="af15" | slow | iostandard=lvdci_33; net "disp_ce_b" loc="af13" | slow | iostandard=lvdci_33; net "disp_reset_b" loc="ag11" | slow | iostandard=lvdci_33; net "disp_data_in" loc="ae15"; # # Buttons and Switches # net "button0" loc="ae11"; net "button1" loc="ae10"; net "button2" loc="ad11"; net "button3" loc="ab12"; net "button_enter" loc="ak7"; net "button_right" loc="al6"; net "button_left" loc="al5"; net "button_up" loc="al4"; net "button_down" loc="ak6"; net "switch<7>" loc="ad22"; net "switch<6>" loc="ae23"; net "switch<5>" loc="ac20"; net "switch<4>" loc="ab20"; net "switch<3>" loc="ac21"; net "switch<2>" loc="ak25"; net "switch<1>" loc="al26"; net "switch<0>" loc="ak26"; # # Discrete LEDs # net "led<7>" loc="ae17" | slow | iostandard=lvttl; net "led<6>" loc="af17" | slow | iostandard=lvttl; net "led<5>" loc="af18" | slow | iostandard=lvttl; net "led<4>" loc="af19" | slow | iostandard=lvttl; net "led<3>" loc="af20" | slow | iostandard=lvttl; net "led<2>" loc="ag21" | slow | iostandard=lvttl; net "led<1>" loc="ae21" | slow | iostandard=lvttl; net "led<0>" loc="ae22" | slow | iostandard=lvttl; # # User Pins # net "user1<31>" loc="j15" | fast | iostandard=lvttl; net "user1<30>" loc="j14" | fast | iostandard=lvttl; net "user1<29>" loc="g15" | fast | iostandard=lvttl; net "user1<28>" loc="f14" | fast | iostandard=lvttl; net "user1<27>" loc="f12" | fast | iostandard=lvttl; net "user1<26>" loc="h11" | fast | iostandard=lvttl; net "user1<25>" loc="g9" | fast | iostandard=lvttl; net "user1<24>" loc="h9" | fast | iostandard=lvttl; net "user1<23>" loc="b15" | fast | iostandard=lvttl; net "user1<22>" loc="b14" | fast | iostandard=lvttl; net "user1<21>" loc="f15" | fast | iostandard=lvttl; net "user1<20>" loc="e13" | fast | iostandard=lvttl; net "user1<19>" loc="e11" | fast | iostandard=lvttl; net "user1<18>" loc="e9" | fast | iostandard=lvttl; net "user1<17>" loc="f8" | fast | iostandard=lvttl; net "user1<16>" loc="f7" | fast | iostandard=lvttl; net "user1<15>" loc="c13" | fast | iostandard=lvttl; net "user1<14>" loc="c12" | fast | iostandard=lvttl; net "user1<13>" loc="c11" | fast | iostandard=lvttl; net "user1<12>" loc="c10" | fast | iostandard=lvttl; net "user1<11>" loc="c9" | fast | iostandard=lvttl; net "user1<10>" loc="c8" | fast | iostandard=lvttl; net "user1<9>" loc="c6" | fast | iostandard=lvttl; net "user1<8>" loc="e6" | fast | iostandard=lvttl; net "user1<7>" loc="a11" | fast | iostandard=lvttl; net "user1<6>" loc="a10" | fast | iostandard=lvttl; net "user1<5>" loc="a9" | fast | iostandard=lvttl; net "user1<4>" loc="a8" | fast | iostandard=lvttl; net "user1<3>" loc="b6" | fast | iostandard=lvttl; net "user1<2>" loc="b5" | fast | iostandard=lvttl; net "user1<1>" loc="c5" | fast | iostandard=lvttl; net "user1<0>" loc="b3" | fast | iostandard=lvttl; net "user2<31>" loc="b27" | fast | iostandard=lvttl; net "user2<30>" loc="b26" | fast | iostandard=lvttl; net "user2<29>" loc="b25" | fast | iostandard=lvttl; net "user2<28>" loc="a24" | fast | iostandard=lvttl; net "user2<27>" loc="a23" | fast | iostandard=lvttl; net "user2<26>" loc="a22" | fast | iostandard=lvttl; net "user2<25>" loc="a21" | fast | iostandard=lvttl; net "user2<24>" loc="a20" | fast | iostandard=lvttl; net "user2<23>" loc="d26" | fast | iostandard=lvttl; net "user2<22>" loc="d25" | fast | iostandard=lvttl; net "user2<21>" loc="c24" | fast | iostandard=lvttl; net "user2<20>" loc="d23" | fast | iostandard=lvttl; net "user2<19>" loc="d21" | fast | iostandard=lvttl; net "user2<18>" loc="d20" | fast | iostandard=lvttl; net "user2<17>" loc="d19" | fast | iostandard=lvttl; net "user2<16>" loc="d18" | fast | iostandard=lvttl; net "user2<15>" loc="f24" | fast | iostandard=lvttl; net "user2<14>" loc="f23" | fast | iostandard=lvttl; net "user2<13>" loc="e22" | fast | iostandard=lvttl; net "user2<12>" loc="e20" | fast | iostandard=lvttl; net "user2<11>" loc="e18" | fast | iostandard=lvttl; net "user2<10>" loc="e16" | fast | iostandard=lvttl; net "user2<9>" loc="a19" | fast | iostandard=lvttl; net "user2<8>" loc="a18" | fast | iostandard=lvttl; net "user2<7>" loc="h22" | fast | iostandard=lvttl; net "user2<6>" loc="g22" | fast | iostandard=lvttl; net "user2<5>" loc="f21" | fast | iostandard=lvttl; net "user2<4>" loc="f19" | fast | iostandard=lvttl; net "user2<3>" loc="f17" | fast | iostandard=lvttl; net "user2<2>" loc="h19" | fast | iostandard=lvttl; net "user2<1>" loc="g20" | fast | iostandard=lvttl; net "user2<0>" loc="h21" | fast | iostandard=lvttl; net "user3<31>" loc="g12" | fast | iostandard=lvttl; net "user3<30>" loc="h13" | fast | iostandard=lvttl; net "user3<29>" loc="j13" | fast | iostandard=lvttl; net "user3<28>" loc="g14" | fast | iostandard=lvttl; net "user3<27>" loc="f13" | fast | iostandard=lvttl; net "user3<26>" loc="f11" | fast | iostandard=lvttl; net "user3<25>" loc="g10" | fast | iostandard=lvttl; net "user3<24>" loc="h10" | fast | iostandard=lvttl; net "user3<23>" loc="a15" | fast | iostandard=lvttl; net "user3<22>" loc="a14" | fast | iostandard=lvttl; net "user3<21>" loc="e15" | fast | iostandard=lvttl; net "user3<20>" loc="e14" | fast | iostandard=lvttl; net "user3<19>" loc="e12" | fast | iostandard=lvttl; net "user3<18>" loc="e10" | fast | iostandard=lvttl; net "user3<17>" loc="f9" | fast | iostandard=lvttl; net "user3<16>" loc="g8" | fast | iostandard=lvttl; net "user3<15>" loc="d14" | fast | iostandard=lvttl; net "user3<14>" loc="d13" | fast | iostandard=lvttl; net "user3<13>" loc="d12" | fast | iostandard=lvttl; net "user3<12>" loc="d11" | fast | iostandard=lvttl; net "user3<11>" loc="d9" | fast | iostandard=lvttl; net "user3<10>" loc="d8" | fast | iostandard=lvttl; net "user3<9>" loc="d7" | fast | iostandard=lvttl; net "user3<8>" loc="d6" | fast | iostandard=lvttl; net "user3<7>" loc="b12" | fast | iostandard=lvttl; net "user3<6>" loc="b11" | fast | iostandard=lvttl; net "user3<5>" loc="b10" | fast | iostandard=lvttl; net "user3<4>" loc="b9" | fast | iostandard=lvttl; net "user3<3>" loc="a7" | fast | iostandard=lvttl; net "user3<2>" loc="a6" | fast | iostandard=lvttl; net "user3<1>" loc="a5" | fast | iostandard=lvttl; net "user3<0>" loc="a4" | fast | iostandard=lvttl; net "user4<31>" loc="a28" | fast | iostandard=lvttl; net "user4<30>" loc="a27" | fast | iostandard=lvttl; net "user4<29>" loc="a26" | fast | iostandard=lvttl; net "user4<28>" loc="a25" | fast | iostandard=lvttl; net "user4<27>" loc="b23" | fast | iostandard=lvttl; net "user4<26>" loc="b22" | fast | iostandard=lvttl; net "user4<25>" loc="b21" | fast | iostandard=lvttl; net "user4<24>" loc="b20" | fast | iostandard=lvttl; net "user4<23>" loc="e25" | fast | iostandard=lvttl; net "user4<22>" loc="c26" | fast | iostandard=lvttl; net "user4<21>" loc="d24" | fast | iostandard=lvttl; net "user4<20>" loc="c23" | fast | iostandard=lvttl; net "user4<19>" loc="c22" | fast | iostandard=lvttl; net "user4<18>" loc="c21" | fast | iostandard=lvttl; net "user4<17>" loc="c20" | fast | iostandard=lvttl; net "user4<16>" loc="c19" | fast | iostandard=lvttl; net "user4<15>" loc="g24" | fast | iostandard=lvttl; net "user4<14>" loc="e24" | fast | iostandard=lvttl; net "user4<13>" loc="e23" | fast | iostandard=lvttl; net "user4<12>" loc="e21" | fast | iostandard=lvttl; net "user4<11>" loc="e19" | fast | iostandard=lvttl; net "user4<10>" loc="e17" | fast | iostandard=lvttl; net "user4<9>" loc="b19" | fast | iostandard=lvttl; net "user4<8>" loc="b18" | fast | iostandard=lvttl; net "user4<7>" loc="h23" | fast | iostandard=lvttl; net "user4<6>" loc="g23" | fast | iostandard=lvttl; net "user4<5>" loc="g21" | fast | iostandard=lvttl; net "user4<4>" loc="f20" | fast | iostandard=lvttl; net "user4<3>" loc="f18" | fast | iostandard=lvttl; net "user4<2>" loc="f16" | fast | iostandard=lvttl; net "user4<1>" loc="g18" | fast | iostandard=lvttl; net "user4<0>" loc="g17" | fast | iostandard=lvttl; # # Daughter Card # net "daughtercard<43>" loc="L7" | slow | iostandard=lvttl; net "daughtercard<42>" loc="H1" | slow | iostandard=lvttl; net "daughtercard<41>" loc="J2" | slow | iostandard=lvttl; net "daughtercard<40>" loc="J1" | slow | iostandard=lvttl; net "daughtercard<39>" loc="K2" | slow | iostandard=lvttl; net "daughtercard<38>" loc="M7" | slow | iostandard=lvttl; net "daughtercard<37>" loc="M6" | slow | iostandard=lvttl; net "daughtercard<36>" loc="M3" | slow | iostandard=lvttl; net "daughtercard<35>" loc="M4" | slow | iostandard=lvttl; net "daughtercard<34>" loc="L3" | slow | iostandard=lvttl; net "daughtercard<33>" loc="K1" | slow | iostandard=lvttl; net "daughtercard<32>" loc="L4" | slow | iostandard=lvttl; net "daughtercard<31>" loc="K3" | slow | iostandard=lvttl; net "daughtercard<30>" loc="K9" | slow | iostandard=lvttl; net "daughtercard<29>" loc="L9" | slow | iostandard=lvttl; net "daughtercard<28>" loc="K8" | slow | iostandard=lvttl; net "daughtercard<27>" loc="K7" | slow | iostandard=lvttl; net "daughtercard<26>" loc="L8" | slow | iostandard=lvttl; net "daughtercard<25>" loc="L6" | slow | iostandard=lvttl; net "daughtercard<24>" loc="M5" | slow | iostandard=lvttl; net "daughtercard<23>" loc="N5" | slow | iostandard=lvttl; net "daughtercard<22>" loc="P5" | slow | iostandard=lvttl; net "daughtercard<21>" loc="D3" | slow | iostandard=lvttl; net "daughtercard<20>" loc="E4" | slow | iostandard=lvttl; net "daughtercard<19>" loc="E3" | slow | iostandard=lvttl; net "daughtercard<18>" loc="F4" | slow | iostandard=lvttl; net "daughtercard<17>" loc="F3" | slow | iostandard=lvttl; net "daughtercard<16>" loc="G4" | slow | iostandard=lvttl; net "daughtercard<15>" loc="H4" | slow | iostandard=lvttl; net "daughtercard<14>" loc="J3" | slow | iostandard=lvttl; net "daughtercard<13>" loc="J4" | slow | iostandard=lvttl; net "daughtercard<12>" loc="D2" | slow | iostandard=lvttl; net "daughtercard<11>" loc="D1" | slow | iostandard=lvttl; net "daughtercard<10>" loc="E2" | slow | iostandard=lvttl; net "daughtercard<9>" loc="E1" | slow | iostandard=lvttl; net "daughtercard<8>" loc="F5" | slow | iostandard=lvttl; net "daughtercard<7>" loc="G5" | slow | iostandard=lvttl; net "daughtercard<6>" loc="H5" | slow | iostandard=lvttl; net "daughtercard<5>" loc="J5" | slow | iostandard=lvttl; net "daughtercard<4>" loc="K5" | slow | iostandard=lvttl; net "daughtercard<3>" loc="H7" | slow | iostandard=lvttl; net "daughtercard<2>" loc="J8" | slow | iostandard=lvttl; net "daughtercard<1>" loc="J6" | slow | iostandard=lvttl; net "daughtercard<0>" loc="J7" | slow | iostandard=lvttl; # # System Ace # net "systemace_data<15>" loc="F29" | slow | iostandard=lvttl; net "systemace_data<14>" loc="G28" | slow | iostandard=lvttl; net "systemace_data<13>" loc="H29" | slow | iostandard=lvttl; net "systemace_data<12>" loc="H28" | slow | iostandard=lvttl; net "systemace_data<11>" loc="J29" | slow | iostandard=lvttl; net "systemace_data<10>" loc="J28" | slow | iostandard=lvttl; net "systemace_data<9>" loc="K29" | slow | iostandard=lvttl; net "systemace_data<8>" loc="L29" | slow | iostandard=lvttl; net "systemace_data<7>" loc="L28" | slow | iostandard=lvttl; net "systemace_data<6>" loc="M29" | slow | iostandard=lvttl; net "systemace_data<5>" loc="M28" | slow | iostandard=lvttl; net "systemace_data<4>" loc="N29" | slow | iostandard=lvttl; net "systemace_data<3>" loc="N28" | slow | iostandard=lvttl; net "systemace_data<2>" loc="P28" | slow | iostandard=lvttl; net "systemace_data<1>" loc="R29" | slow | iostandard=lvttl; net "systemace_data<0>" loc="R28" | slow | iostandard=lvttl; net "systemace_address<6>" loc="E29" | slow | iostandard=lvttl; net "systemace_address<5>" loc="F28" | slow | iostandard=lvttl; net "systemace_address<4>" loc="H31" | slow | iostandard=lvttl; net "systemace_address<3>" loc="J30" | slow | iostandard=lvttl; net "systemace_address<2>" loc="J31" | slow | iostandard=lvttl; net "systemace_address<1>" loc="K30" | slow | iostandard=lvttl; net "systemace_address<0>" loc="K31" | slow | iostandard=lvttl; net "systemace_ce_b" loc="E28" | slow | iostandard=lvttl; net "systemace_we_b" loc="P31" | slow | iostandard=lvttl; net "systemace_oe_b" loc="R31" | slow | iostandard=lvttl; net "systemace_irq" loc="D29"; net "systemace_mpbrdy" loc="L31"; # # Logic Analyzer # net "analyzer1_data<15>" loc="G1" | slow | iostandard=lvttl; net "analyzer1_data<14>" loc="H3" | slow | iostandard=lvttl; net "analyzer1_data<13>" loc="M9" | slow | iostandard=lvttl; net "analyzer1_data<12>" loc="M8" | slow | iostandard=lvttl; net "analyzer1_data<11>" loc="L5" | slow | iostandard=lvttl; net "analyzer1_data<10>" loc="L1" | slow | iostandard=lvttl; net "analyzer1_data<9>" loc="L2" | slow | iostandard=lvttl; net "analyzer1_data<8>" loc="N9" | slow | iostandard=lvttl; net "analyzer1_data<7>" loc="M1" | slow | iostandard=lvttl; net "analyzer1_data<6>" loc="M2" | slow | iostandard=lvttl; net "analyzer1_data<5>" loc="N1" | slow | iostandard=lvttl; net "analyzer1_data<4>" loc="N2" | slow | iostandard=lvttl; net "analyzer1_data<3>" loc="P1" | slow | iostandard=lvttl; net "analyzer1_data<2>" loc="P2" | slow | iostandard=lvttl; net "analyzer1_data<1>" loc="R1" | slow | iostandard=lvttl; net "analyzer1_data<0>" loc="R2" | slow | iostandard=lvttl; net "analyzer1_clock" loc="G2" | slow | iostandard=lvttl; # # Timing constraints for built-in clocks # net "clock_27mhz" tnm_net="clock_27mhz"; timespec "ts_clock_27mhz" = period "clock_27mhz" 37ns high 50%;