//
// Register 0
//

`define CHROMA_FILTER_SELECT                    3'h0
  // 0: 1.3MHz low-pass
  // 1: 0.65MHz low-pass
  // 2: 1.0MHz low-pass
  // 3: 2.0MHz low-pass
  // 4: [Not valid]
  // 5: CIF
  // 6: QCIF
  // 7: 3.0MHz low-pass
`define LUMA_FILTER_SELECT                      3'h0
  // 0: Low-pass (NTSC)
  // 1: Low-pass (PAL)
  // 2: Notch (NTSC)
  // 3: Notch (PAL)
  // 4: Extended mode
  // 5: CIF
  // 6: QCIF
  // 7: [Not valid]
`define VIDEO_STANDARD_SELECT                   2'h0
  // 0: NTSC
  // 1: PAL (B, D, G, H, I)
  // 2: [Not valid]
  // 3: PAL (N)

`define ADV7194_REGISTER_0 {`CHROMA_FILTER_SELECT, `LUMA_FILTER_SELECT, `VIDEO_STANDARD_SELECT}

//
// Register 1
//

`define FOUR_TIMES_OVERSAMPLING                 1'b1
`define DAC_A_ENABLE                            1'b0
`define DAC_B_ENABLE                            1'b0
`define DAC_C_ENABLE                            1'b0
`define DAC_D_ENABLE                            1'b1
  // Composite video DAC
`define DAC_E_ENABLE                            1'b1
  // S-video cluma DAC
`define DAC_F_ENABLE                            1'b1
  // S-video chroma DAC

`define ADV7194_REGISTER_1 {1'b0, `FOUR_TIMES_OVERSAMPLING, `DAC_A_ENABLE, `DAC_B_ENABLE, `DAC_C_ENABLE, `DAC_D_ENABLE, `DAC_E_ENABLE, `DAC_F_ENABLE}

//
// Register 2
//

`define SLEEP_MODE                              1'b0
  // 0: Normal mode
  // 1: Sleep mode
`define PIXEL_DATA_VALID                        1'b1
  // 1: Enables the YCrCb data port
`define I2C_CONTROL                             1'b0
  // 0: Video standard set by NTSC/PAL pin (low=NTSC, high=PAL)
  // 1: Video standard set by register 0
`define SQUARE_PIXEL_MODE                       1'b0
  // 0: Normal
  // 1: Square pixel mode (requires special clocks)
`define PEDESTAL_CONTROL                        1'b0
  // 0: Pedestal off
  // 1: Pedestal on (NTSC only)
`define DAC_OUTPUT_CONTROL                      3'h0
  // 0: Composite output on DAC D, s-video on DACs E and F
  // (this is the only configuration supported by the 6.111 labkit hardware)

`define ADV7194_REGISTER_2 {`SLEEP_MODE, `PIXEL_DATA_VALID, `I2C_CONTROL, `SQUARE_PIXEL_MODE, `PEDESTAL_CONTROL, `DAC_OUTPUT_CONTROL}

//
// Register 3
//

`define CLOSED_CAPTIONING_CONTROL               2'h0
  // 0: No CC data
  // 1: Odd field only
  // 2: Even field only
  // 3: Both fields
`define TELETEXT_REQUEST_MODE                   1'b0
  // ???
`define TELETEXT_ENABLE                         1'b0
  // 0: Disabled
  // 1: Teletext data on TTX pin
`define VBI_OPEN                                1'b0
  // 0: DACs blanked during vertival blanking interval
  // 1: DACs enabled during vertival blanking interval

`define ADV7194_REGISTER_3 {1'b0, `CLOSED_CAPTIONING_CONTROL, `TELETEXT_REQUEST_MODE, `TELETEXT_ENABLE, `VBI_OPEN, 2'b00}

//
// Register 4
//

`define INTERLACE_MODE                          1'b0
  // 0: Interlaced
  // 1: Progressive
`define COLOR_BARS                              1'b0
  // 0: Normal
  // 1: Display colorbars
`define BURST_CONTROL                           1'b0
  // 0: Enable color burst on composite and chrominance channels
  // 1: Disable color burst
`define CHROMINANCE_CONTROL                     1'b0
  // 0: Enable color
  // 1: Disable color
`define ACTIVE_VIDEO_LINE_DURATION              1'b0
  // 0: CCIR Rec. 601 standard: 720 pixels
  // 1: ITU-R BT.470 standard: 710 pixels (NTSC) / 702 pixels (PAL)
`define GENLOCK_CONTROL                         2'h0
  // 0: Disable genlock
  // 1: Enable subcarrier reset pin
  // 2: Timing reset
  // 3: Enable RTC pin
`define THREE_LINE_VSYNC                        1'b0
  // 0: Disabled
  // 1: Enabled

`define ADV7194_REGISTER_4 {`INTERLACE_MODE, `COLOR_BARS, `BURST_CONTROL, `CHROMINANCE_CONTROL, `ACTIVE_VIDEO_LINE_DURATION, `GENLOCK_CONTROL, `THREE_LINE_VSYNC}

//
// Register 5
//

`define CLAMP_POSITION                          1'b0
  // 0: Front porch
  // 1: Back porch
`define CLAMP_DELAY_DIRECTION                   1'b0
  // 0: Positive
  // 1: Negative
`define CLAMP_DELAY                             2'h0
  // 0-3: Clamp delay, in clock cycles
`define RGB_SYNC                                1'b1
  // 0: Disabled
  // 1: Enabled
`define UV_LEVEL                                2'h0
  // 0: Default levels (934mV NTSC, 700mV PAL)
  // 1: 700mV
  // 2: 1000mV
  // 3: [Not valid]
`define Y_LEVEL                                 1'b1
  // 0: Betacam levels
  // 1: SMPTE levels

`define ADV7194_REGISTER_5 {`CLAMP_POSITION, `CLAMP_DELAY_DIRECTION, `CLAMP_DELAY, `RGB_SYNC, `UV_LEVEL, `Y_LEVEL}

//
// Register 6
//

`define PLL_ENABLE                              1'b0
  // 0: Enabled
  // 1: Disabled
`define POWER_UP_SLEEP_MODE                     1'b1
  // ??

`define ADV7194_REGISTER_6 {3'b000, 3'b000, `PLL_ENABLE, `POWER_UP_SLEEP_MODE}

//
// Register 7
//

`define PIN_62_MODE                             2'b0
  // 0: Teletext input
  // 1: ~VSO output
  // 2: Teletext input
  // 3: CLAMP output
`define CSO_HSO_CONTROL                         1'b0
  // 0: ~HSO output
  // 1: ~CSO output
`define SHARPNESS_FILTER                        1'b0
  // 0: Disable
  // 1: Enable
`define BRIGHTNESS_ADJUST                       1'b0
  // 0: Disable
  // 1: Enable
`define HUE_ADJUST                              1'b0
  // 0: Disable
  // 1: Enable
`define LUMA_SATURATION_CONTROL                 1'b0
  // 0: Disable
  // 1: Enable
`define COLOR_CONTROL                           1'b0
  // 0: Disable
  // 1: Enable

`define ADV7194_REGISTER_7 {`PIN_62_MODE, `CSO_HSO_CONTROL, `SHARPNESS_FILTER, `BRIGHTNESS_ADJUST, `HUE_ADJUST, `LUMA_SATURATION_CONTROL, `COLOR_CONTROL}

//
// Register 8
//


module adv7194init (clock_27mhz, reset, initializing, tv_out_reset_b, 
		    tv_out_sclk, tv_out_data);
   
   input clock_27mhz;
   input reset; // Active high input to initiate a reset and reconfiguring of the ADV7194
   output initializing; // Active high output indicating that the ADV7194 is either in reset or is not yet configured
   output tv_out_reset_b; // Reset signal to ADV7194
   output tv_out_sclk; // I2C clock output to ADV7194
   inout tv_out_data; // I2C data line to ADV7194
   

   initial begin
      $display("ADV7194 Initialization values:");
      $display("  Register 0: 0x%X", `ADV7194_REGISTER_0);
      $display("  Register 1: 0x%X", `ADV7194_REGISTER_1);
      $display("  Register 2: 0x%X", `ADV7194_REGISTER_2);
      $display("  Register 3: 0x%X", `ADV7194_REGISTER_3);
      $display("  Register 4: 0x%X", `ADV7194_REGISTER_4);
      $display("  Register 5: 0x%X", `ADV7194_REGISTER_5);
      $display("  Register 6: 0x%X", `ADV7194_REGISTER_6);
      $display("  Register 7: 0x%X", `ADV7194_REGISTER_7);
   end
   
   //
   // Generate a 1MHz for the I2C driver (resulting I2C clock rate is 250kHz)
   //
   
   reg [7:0] clk_div_count;
   reg clock_slow;
   
   initial begin
      clk_div_count = 8'h00;
      // synthesis attribute init of clk_div_count is "00";
      clock_slow = 1'b0;
      // synthesis attribute init of clock_slow is "0";
   end
   
   always @(posedge clock_27mhz) begin
      if (clk_div_count == 26)
	begin
	   clock_slow = ~clock_slow;
	   clk_div_count = 0;
	end
      else
	clk_div_count = clk_div_count+1;
   end

   //
   // I2C driver
   //
   
   reg load;
   reg [7:0] data;
   wire ack, idle;
   
   i2c i2c(.clock4x(clock_slow), .data(data), .load(load), .ack(ack),
	   .idle(idle), .scl(tv_out_sclk), .sda(tv_out_data));   
   
   //
   // State machine
   //
   
   reg [7:0] state;
   reg tv_out_reset_b;
   reg initializing;
          
   initial begin
      state = 8'h00;
      // synthesis attribute init of state is "00";
      data = 8'h00;
      // synthesis attribute init of data is "00";
      load = 1'b0;
      // synthesis attribute init of load is "0";
      tv_out_reset_b = 1'b0;
      // synthesis attribute init of tv_out_reset_b is "0";
   end

   always @(posedge clock_slow) begin
      case (state)
	8'h00: begin
	   // Assert reset
	   load = 1'b0;
	   tv_out_reset_b = 1'b0;
	   initializing = 1'b1;
	   if (!ack) state = state+1;
	end
	8'h01: begin
	   state = state+1;
	end
	8'h02: begin
	   // Release reset
	   tv_out_reset_b = 1'b1;
	   state = state+1;
	end
	8'h03: begin
	   // Send ADV7194 address
	   data = 8'h56;
	   load = 1'b1;
	   if (ack) state = state+1;
	end
	8'h04: begin
	   // Send subaddress of first register
	   data = 8'h00;
	   if (ack) state = state+1;
	end
	8'h05: begin
	   // Write to register 0
	   data = `ADV7194_REGISTER_0;
	   if (ack) state = state+1;
	end
	8'h06: begin
	   // Write to register 1
	   data = `ADV7194_REGISTER_1;
	   if (ack) state = state+1;
	  end
	8'h07: begin
	   // Write to register 2
	   data = `ADV7194_REGISTER_2;
	   if (ack) state = state+1;
	end
	8'h08: begin
	   // Write to register 3
	   data = `ADV7194_REGISTER_3;
	   if (ack) state = state+1;
	end
	8'h09: begin
	   // Write to register 4
	   data = `ADV7194_REGISTER_4;
	   if (ack) state = state+1;
	end
	8'h0A: begin
	   // Write to register 5
	   data = `ADV7194_REGISTER_5;
	   if (ack) state = state+1;
	end
	8'h0B: begin
	   // Write to register 6
	   data = `ADV7194_REGISTER_6;
	   if (ack) state = state+1;
	end
	8'h0C: begin
	   // Write to register 7
	   data = `ADV7194_REGISTER_7;
	   if (ack) state = state+1;
	end
	8'h0D: begin
	   // Wait for I2C transmitter to finish
	   load = 1'b0;
	   if (idle) state = state+1;
	end
	8'h0E: begin
	   // Idle
	   initializing = 1'b0;
	end
      endcase

      if (reset)
	state = 0;
   end

endmodule