6.111 Software Tools Guide
MAX+plusII for Altera FPGA
Creating and Simulating RAM
Cypress WARP is a tool for generating PAL programming data. WARP
takes a design in Verilog and produces a JEDEC (.jed) programming file to be used
by the PAL burners.
To use WARP on the Lab PC, launch the application by clicking on the Galaxy
desktop icon. To use WARP on any Athena Sun machine, first run 'setup
6.111' to setup the environment. Then run 'galaxy &' from the desired project directory.
Galaxy is the graphical front end to WARP.
WARP Tutorial (pdf)
Once a .jed file is created, it needs to be transferred to the PAL programming station to be burned into the PAL. For instructions on using the PAL programmer, view the PAL Programmer Guide. You will need a floppy disk to transfer the file.
Altera FPGA Programming
The two phases for generating a programming file for the Altera FPGA's
can be split between simulation/verification of the Verilog hardware description
followed by synthesis/optimization. Modelsim will be used for simulating the
Verilog description of the system to be built. Altera's MAX+plusII
tool performs the final phase of mapping the Verilog description to the device. MAX+plusII also has a builtin simulator.
On the Lab PC under Windows XP, launch ModelSim from the Desktop icon
(or Start -> All Programs -> ModelSim SE -> ModelSim)
On an Athena Sun workstation, you must first run 'setup 6.111' to configure
your environment correctly. Then run 'vsim &' to start the application.
Create a new project with: File->New->Project and a wizard walks you through project creation.
A Modelsim tutorial (PDF) provides an example of using Modelsim for Verilog simulation.
The PDF for the user's manual: https://web.mit.edu/6.111/www/s2004/restricted/se_man.pdf (MIT certificates required)
On the Lab PCs under Windows XP, launch MAX+plus II from the Desktop icon
(or Start-> All Programs -> Altera -> MAX+plus II 10.2)
On Athena, the software is only available on a Sun workstation running
Solaris 8. It will not work directly on an Athena machine since Athena
9.2 uses Solaris 9 which is not currently supported by Altera. Therefore you will need to login remotely if you
wish to use MAX+plusII outside of the Digital Lab. There are 2 Sun machines running Solaris 8 in
the lab that can be used remotely: athpal04, athpal05 [.mit.edu].
After logging in (use ssh -X) and setting the remote X display, you will need to
run 'setup 6.111' to configure your environment correctly. Then run 'max2win
&' from the desired project directory to start the application. For example:
athena > ssh -X athpal04
athpal04 > setup 6.111
athpal04 > max2win &
For more information and a tutorial: A Beginner's Guide to MAX+plusII
Altera also provides a version for the PC for free from their website
Creating and Simulating RAM in ModelSim
For a guide to generating memories in MAX+plusII and simulating in Modelsim, click here.
Generating ROM Data for MAX+plusII
When generating an internal ROM in an Altera FPGA, the memory contents can be specified in a Memory Initialization File (.mif). The format is shown here and also available (rom8x8.mif) as a starting point.
This file is used with the Megawizard Plug-in Manager to create a ROM module to instantiate in a design.
-- MEMORY INITIALIZATION FILE
-- EXAMPLE DATA FOR AN 8x8 ROM
WIDTH = 8; % WIDTH OF OUTPUT IS REQUIRED, ENTER A DECIMAL VALUE %
DEPTH = 8; % DEPTH OF MEMORY IS REQUIRED, ENTER A DECIMAL VALUE %
ADDRESS_RADIX = HEX; % Address and data radixes are optional, default is hex %
DATA_RADIX = HEX; % Valid radixes = BIN,DEC,HEX or OCT %
0 : 07; % ADDRESS : VALUE %
1 : 06;
2 : 05;
3 : 04;
4 : 03;
5 : 02;
6 : 01;
7 : 00;
-- SHORTCUTS FOR SPECIFYING CONTENTS
-- [0..FF] : 0; % Range--Every address from 0 to FF = 0%
-- D : 7; % Single address--Address D = 7 %
-- 6 : 9 C 8; % Range starting from specific address--%
-- If there are multiple values for the same address only the last value is used
To generate a ROM module using this example in MAX+plusII:
File->MegaWizard Plug-In Manager
Select "Create a new custom megafunction variation"
Select Verilog HDL
Select storage-> LPM_ROM
Enter an output name such as "rom8x8"
Select '3' for width of q output for this example
Uncheck 'address input port' under "Which ports should be registered?"
Browse to the rom8x8.mif file that was created or downloaded from above
A summary page shows the files to be created
Generating PROM Data
There are a suite of command line tools available on Athena for generating data to be stored in PROM chips. These tools are currently not available on the Lab PCs and are only needed for final projects which, for example, may use PROMs for storing character or image data. A promtools guide provides further details.
dat2ntl is a command line routine for generating a .hex (.ntl) file whish is also suitable for MAX+plusII ROM initialization. dat2ntl is available on Athena for most platforms by first running 'setup 6.111'. It is not available on the Lab PCs.
Create a .dat file following the example in impulses.dat. Convert to the Intel Hex Format: 'dat2ntl impulses.dat impulses.ntl'
An online dat2ntl manpage provides further details. This page can also be viewed by typing 'man dat2ntl'.
If you have trouble running any of the tools, send an email to email@example.com.
Last modified: 2004-03-16 Frank Honoré