The gate arrays are SRAM based which means they need to be configured
each time power is applied.
Happily, this is done automatically as the gate arrays are wired to
a flash prom (EPC2).
However, one does have to program the EPC2.
This is done by the Max+plus II software using information in a
<project_name>.pof file and communicating with the EPC2 via a JTAG
interface.
You must generate the appropriate <project_name>.pof file by
selecting the appropriate device (EPF10K10LC84-3 or EPF10K70RC240-2
and the configuration device option of EPC2LC20). See the beginner's
guide for details on how to do this.
There is no simple (quick) way to erase the EPC2s.
Instead one must ``erase'' them by programming them with a VHDL file
which tri-states all of the I/O pins connected to either the NuBus
interface or the 50-pin connector (should you ever use it).
This should be done whenever you use a new (to you) FPGA Module.
Then all you need do is to program your FPGAs.
Of course you want to make sure that the two FPGAs never drive the
same pin on the NuBus interface, e.g., AD13.