NuBus Interface

There are thirty I/O pins from each FLEX 10K PLD connected to the NuBus interface, as well as to each other.

Two clock pins are on the NuBus proto strip. Each gate array has two clocks. Which one(s) are used is specified by your VHDL code. In addition one of the clocks is connected to an I/O pin on each gate array so that the I/O pin can be used if only one clock is used. Note that A31 is used for supplying the clock to the CPLD module if one is also used. The clock pins are denoted in Table 1 as CLK.

 

Table: Correlation between NuBus Pins and FLEX 10K Pins

NuBus	FLEX 10K10	FLEX 10K70
Address	Pin Number	Pin Number
A0	1 ( CLK)	91 ( CLK)
A1	NONE	NONE
A2	17	7
A3	18	8
A4	19	9
A5	21	12
A6	22	13
A7	23	14
A8	24	15
A9	25	17
A10	27	18
A11	28	19
A12	29	20
A13	30	21
A14	35	24
A15	36	25
A16	37	28
A17	38	29
A18	39	30
A19	47	31
A20	48	33
A21	49	34
A22	50	35
A23	51	36
A24	52	38
A25	53	39
A26	54	40
A27	58	41
A28	59	43
A29	60	44
A30	61	45
A31	62	46