6.173 Fall 2010

Week of Tue Thu Lab

Sep 06 Registration Day L01: Intro to parallel systems hardware and software. Why multicore is important, multicore directions, challenges. Overview of Beehive system used in the lab (hw, sw, programming using messages).

Sep 13 L02: Parallel architectures: broad overview. Message passing, programming in a message passing style. Intro to Verilog. L03: Parallel applications; two major approaches -- data parallel (stripe), data pipeline (stream). Jacobi (stripe), TSP overview (strip), FIR filter (stream). More Verilog with review of Beehive source tree. Lab 1: Implement TSP on a single core using branch-and-bound algorithm.
Due Friday, 9/17

Sep 20 L04: Parallel programmingconcepts using Jacobi relaxation as example. Partitioning (granularity) and communication, load balancing, parallelism versus locality, placement. L05: Parallel programming concepts, cont'd. Message passing. Interrupts polling. Lab 2: Implement broadcast primitive in both software and hardware. Compare performance.
Due Friday, 9/24

Sep 27 L06: Guest lecture on transactional memories. L07: Parallel programming: shared memory architectures and shared memory programming (no caches); intro to synchronization. Lab 3: Revise Lab 1 to run TSP on multiple cores using message passing.
Due Friday, 10/1

Oct 04 L08: Parallel programming: shared memory programming with caches; explicit software cache control; intro to memory consistency and coherence; hardware support for coherence. L09: Parallel programming: coordination, locks, barriers, condition variables, HW support. Lab 4: Implement barrier synchronization in both software and hardware. Compare performance.
Due Friday, 10/15

Oct 11 L10: Caches and coherence I L11: Caches and coherence II

Oct 18 L12: Final project: scope, expectations, potential project ideas. Quiz 1 (during class time)
Coverage: through L10, Lab 5 Lab 5: Parallelize TSP using software shared memory (explicit cache invalidations) and Beehive's lock primitive.
Due Friday, 10/22

Oct 25 L13: Caches and Coherence III L14: Interconnect I Lab 6: Modify Beehive to provide reclaimable locks. Modify Lab 5 to use new locks and compare performance.
Due Wed, 11/4

Nov 01 L15: Scalable synchronization L16: Interconnect II Final project: submit project team and project abstract.
Due Friday, 11/5

Nov 08 L17: Interconnect III Veteran's Day Final project: submit detailed proposal.
Due Friday, 11/12

Nov 15 L18: Case study I L19: Case study II Final project.
Report due Friday, 12/3

Nov 22 No lecture Thanksgiving

Nov 29 No lecture No lecture

Dec 06 In-class project presentations In-class project presentations

Dec 13 Quiz 2 (Thu, 12/16, 9a in 36-156)

Week of	Tue	Thu	Lab
Sep 06	Registration Day	L01: Intro to parallel systems hardware and software. Why multicore is important, multicore directions, challenges. Overview of Beehive system used in the lab (hw, sw, programming using messages).
Sep 13	L02: Parallel architectures: broad overview. Message passing, programming in a message passing style. Intro to Verilog.	L03: Parallel applications; two major approaches -- data parallel (stripe), data pipeline (stream). Jacobi (stripe), TSP overview (strip), FIR filter (stream). More Verilog with review of Beehive source tree.	Lab 1: Implement TSP on a single core using branch-and-bound algorithm. Due Friday, 9/17
Sep 20	L04: Parallel programmingconcepts using Jacobi relaxation as example. Partitioning (granularity) and communication, load balancing, parallelism versus locality, placement.	L05: Parallel programming concepts, cont'd. Message passing. Interrupts polling.	Lab 2: Implement broadcast primitive in both software and hardware. Compare performance. Due Friday, 9/24
Sep 27	L06: Guest lecture on transactional memories.	L07: Parallel programming: shared memory architectures and shared memory programming (no caches); intro to synchronization.	Lab 3: Revise Lab 1 to run TSP on multiple cores using message passing. Due Friday, 10/1
Oct 04	L08: Parallel programming: shared memory programming with caches; explicit software cache control; intro to memory consistency and coherence; hardware support for coherence.	L09: Parallel programming: coordination, locks, barriers, condition variables, HW support.	Lab 4: Implement barrier synchronization in both software and hardware. Compare performance. Due Friday, 10/15
Oct 11	L10: Caches and coherence I	L11: Caches and coherence II
Oct 18	L12: Final project: scope, expectations, potential project ideas.	Quiz 1 (during class time) Coverage: through L10, Lab 5	Lab 5: Parallelize TSP using software shared memory (explicit cache invalidations) and Beehive's lock primitive. Due Friday, 10/22
Oct 25	L13: Caches and Coherence III	L14: Interconnect I	Lab 6: Modify Beehive to provide reclaimable locks. Modify Lab 5 to use new locks and compare performance. Due Wed, 11/4
Nov 01	L15: Scalable synchronization	L16: Interconnect II	Final project: submit project team and project abstract. Due Friday, 11/5
Nov 08	L17: Interconnect III	Veteran's Day	Final project: submit detailed proposal. Due Friday, 11/12
Nov 15	L18: Case study I	L19: Case study II	Final project. Report due Friday, 12/3
Nov 22	No lecture	Thanksgiving
Nov 29	No lecture	No lecture
Dec 06	In-class project presentations	In-class project presentations
Dec 13	Quiz 2 (Thu, 12/16, 9a in 36-156)

Last modified on 9/6/2010