module toplevel (FPGA_CLK, P_D, P_INIT_IN, P_STB_N_IN, P_AUTO_N_IN, FPGA_HDC, LED_B, LED_R, LED_G, D, A, OE_N, UK) ; input FPGA_CLK ; inout [7:0] P_D ; input P_INIT_IN ; input P_STB_N_IN ; //avoid input P_AUTO_N_IN ; // input P_SEL_N_IN ; // output P_SEL_OUT ; // output P_ERR_OUT ; // output P_BUSY_N_OUT ; // output P_END_OUT ; // output P_ACK_OUT ; output FPGA_HDC ; output LED_B ; output LED_R ; output LED_G ; inout [7:0] D; output [16:0] A; output OE_N; output [4:0] UK; // add your declarations here wire [31:0] countout; wire dir; wire regclk; wire ads; wire [7:0] pdata_out; wire [7:0] pdata_in; // reg [7:0] regdata_out; reg [7:0] regadr; // reg [7:0] regdata_in; // reg [7:0] anatak_d_to_write; reg [7:0] anatak_d_to_read; reg [7:0] anatak_a_a; reg [7:0] anatak_a_b; reg [7:0] anatak_a_c; reg [7:0] anatak_a_d; wire [23:0] anatak_a; // add your code here // assign OE_N = 1'b0; assign regclk = !P_STB_N_IN; // invert to make protocol sane assign dir = P_INIT_IN; assign ads = !P_AUTO_N_IN; // invert assign anatak_a[7:0] = anatak_a_a[7:0]; assign anatak_a[15:8] = anatak_a_b[7:0]; assign anatak_a[23:16] = anatak_a_c[7:0]; assign A[16:0] = anatak_a[16:0]; assign UK[4:0] = anatak_a[21:17]; assign OE_N = anatak_a[23]; // protocol: // if ads, load in a new address to the address register // if dir == 0, then drive data at adr contents to output // if regclk, then latch in data to register at current address // constantly update data to read // address map: // 0: LSB rom address (W) // 1: byte 1 rom address (W) // 2: byte 2 rom address (W) // 3: MSB rom address (W) // 4: rom data to write (W) // 5: rom data to read (R) (actually, in this implementation, this is the only read data at all addresses) // if dir == 1, then Hi-Z, if dir == 0, then drive data assign P_D = dir ? 8'bZ : pdata_out; assign pdata_in = P_D; assign pdata_out = anatak_d_to_read; always @ (posedge FPGA_CLK) begin anatak_d_to_read = D; if( ads ) regadr = pdata_in; if( regclk & (regadr == 8'b0)) anatak_a_a = pdata_in; else anatak_a_a = anatak_a_a; if( regclk & (regadr == 8'b1)) anatak_a_b = pdata_in; else anatak_a_b = anatak_a_b; if( regclk & (regadr == 8'b10)) anatak_a_c = pdata_in; else anatak_a_c = anatak_a_c; if( regclk & (regadr == 8'b11)) anatak_a_d = pdata_in; else anatak_a_d = anatak_a_d; end // some counters to indicate the working status of the device cnt32 counter( .CLK(FPGA_CLK), .Q(countout), .CLR( 1'b0 ) ); assign FPGA_HDC = countout[23]; assign LED_B = D[1]; assign LED_G = D[2]; assign LED_R = D[0]; endmodule