unsigned int value0 = 0;
unsigned int value1 = 0;
unsigned int value2 = 0;
unsigned int value3 = 0;
unsigned int value4 = 0;
unsigned int value5 = 0;
byte x = 0;
volatile unsigned int longtimer = 0;
unsigned int k = 10;
byte freq = 0xfa;

#define LFO 180 // hertz
#define MFO 800 // hertz
#define HFO 4000 // hertz
#define LFO_DUTY 80 // percent duty cycle
#define MFO_DUTY 20 // percent duty cycle
#define HFO_DUTY 14 // percent duty cycle
#define BLACH ((1000000/MFO)*MFO_DUTY)/1600
#define BLAC ((1000000/MFO)*(100 - MFO_DUTY))/1600

void setup() {
  // set cpu clock to 1MHz to simulate ATtiny
  CLKPR = (1<<CLKPCE); // enable clock change
  CLKPR = (1<<CLKPS2); // set to /16
  // setup ADC
  ADMUX = 0x40; // start with ADC0 - internal VCC for Vref
  ADCSRA = 0xdb; // ADC enable, ck/8 = 125kHz
  ADCSRB = 0x00; // free running mode
  DIDR0 = 0x3f; // turn off digital inputs for ADC channels
  // setup PORTB
  DDRB = 0x3f; // set PORTB to output
  PORTB = 0x00; // set PORTB to low
  // setup T1 to simulate an 8b timer
  TCCR1A = (1<<COM1A1)|(0<<COM1A0)|(1<<WGM11)|(0<<WGM10);
  TCCR1B = (1<<WGM13)|(1<<WGM12)|(0<<CS11)|(1<<CS10);
  ICR1H = 0x00; // set to 6kHz
  ICR1L = 1000000/HFO;
  OCR1AH = 0x00; // set to 14% duty cycle
  OCR1AL = (1000000/HFO)*HFO_DUTY/100;
  // setup watchdog timer for slow counting
  cli(); // make sure it doesnt get interrupted
  WDTCSR = (1<<WDCE)|(1<<WDE); // initiate change enable
  WDTCSR = (1<<WDIE)|(1<<WDP2)|(1<<WDP1); // 1s interrupt time
  sei(); // reset interrupts
//  PORTB |= (1<<PORTB2)|(PORTB1);
}

void loop() {
  //LFO on section
  freq = 0x74;
  ICR1L = 0x74;
  unsigned int j = value1>>4;//(1000*LFO_DUTY*MFO/LFO)/100000;
  unsigned int k = 100 + value2>>2;//BLACH;
  unsigned int l = 100 + value3>>1;//BLAC;
  while (freq < 0xfe) {
    DDRB |= (1<<DDB2);
    delayMicroseconds(k);
    DDRB &= ~(1<<DDB2);
    delayMicroseconds(l);
    ++freq;
    ++freq;
    ICR1L = freq;
    //if (freq < 0xa4) freq = 0xfa;
  }
  
  // LFO off section
  j = value0;//(100 - LFO_DUTY)*10000/LFO/1000;
  while (j > 0) {
    delayMicroseconds(60); // approximately 1ms
    --j;
  }
 
//  ICR1H = 0x0a;
  
//  OCR1AH = (value5 >> 8);
  OCR1AL = (value5 >> 2) & 0x00ff;
  
//  if (k > 0) --k;
//  else {
//    OCR1AL = 5 + random(5);
//    k = 10;
//  }
}

ISR(ADC_vect) {
  byte temp0 = ADCL; // fetch ADCL first to freeze sample
  byte temp1 = ADCH; // add to temp register
  ++x;
  if (x == 1) value0 = (temp1 << 8) | temp0;
  else if (x == 2) value1 = (temp1 << 8) | temp0;
  else if (x == 3) value2 = (temp1 << 8) | temp0;
  else if (x == 4) value3 = (temp1 << 8) | temp0;
  else if (x == 5) value4 = (temp1 << 8) | temp0;
  else { 
    value5 = (temp1 << 8) | temp0;
    x = 0;
  }
  ADMUX = 0x40 | x;
  ADCSRA = 0xdf;
}

ISR(WDT_vect) { 
  ++longtimer;
}