.include "tn26def.inc"

.org 0
rjmp start

start: ; configure registers

ldi r16,high(RAMEND)
out SP,r16 ; Set Stack Pointer to top of RAM
ldi r16,1 ; enable pb0 as output
out ddrb,r16
ldi r16,207 ; enable pullups for portb except xtl and set pb0 high
out portb,r16
ldi r16,248 ; enable pullups for porta except adc0-2
out porta,r16
ldi r16,133
out adcsra,r16 ; enable adc and set its clock rate to /32

waitloop: ; initialization waiting period

clr r21
clr r22
ldi r23,128

loop23:

dec r22
brne loop23
dec r21
brne loop23
dec r23
brne loop23

adcloop: ; loop for getting adc data

ldi r16,32 ; select adc0
out admux,r16
sbi adcsra,6 ; turn on adc
ldi r21,20 ; delay 1ms
clr r22

loop1: ; delay 1ms

inc r22
brne loop1
dec r21
brne loop1
in r0,adch ; fetch data from adc0 and send it to r0
ldi r16,33 ; select adc1
out admux,r16
sbi adcsra,6 ; turn on adc
ldi r21,20 ; delay 1ms
clr r22

loop2: ; delay 1ms

inc r22
brne loop2
dec r21
brne loop2
in r1,adch ; fetch data from adc1 and send it to r1
ldi r16,34 ; select adc2
out admux,r16
sbi adcsra,6 ; turn on adc
ldi r21,20 ; delay 1ms
clr r22

loop3: ; delay 1ms

inc r22
brne loop3
dec r21
brne loop3
in r2,adch ; fetch data from adc2 and send it to r2

dataloop: ; send data out

ldi r19,64 ; set up for 64 packets
cbi portb,0 ; packet start
ldi r21,140 ; delay for 100us

loop4: ; delay 100us

dec r21
brne loop4
sbi portb,0
ldi r21,25 ; delay 18us

loop5: ; delay 18us

dec r21
brne loop5
cbi portb,0
ldi r21,47 ; delay 36us

loop6: ; delay 36us

dec r21
brne loop6
nop
sbi portb,0
ldi r21,10 ; delay 8us

loop7: ; delay 8us

dec r21
brne loop7

databyte0: ; start data packet0

cbi portb,0
ldi r21,2 ; delay 4us

loop20: ; delay 4us

dec r21
brne loop20
nop
ldi r18,9

loop9: ; fetch data

mov r3,r0

loop10: ; shift data out pb0

dec r18
breq stopbit0
ror r3 ; put next bit in carry register
brcs bitbang0
nop
cbi portb,0 ; write a 0
nop ; delay 4us
nop
nop
nop
nop
nop
nop
rjmp loop10

bitbang0:

sbi portb,0 ; write a 1
nop ; delay 4us
nop
nop
nop
nop
nop
nop
rjmp loop10

stopbit0: ; stopbit delay

nop
nop
sbi portb,0
ldi r21,9 ; delay 8us

loop11: ; delay 8us

dec r21
brne loop11
nop
nop
nop

databyte1: ;  start data packet1

cbi portb,0
ldi r21,2 ; delay 4us

loop21: ; delay 4us

dec r21
brne loop21
nop
ldi r18,9

loop12: ; fetch data

mov r3,r1

loop13: ; shift data out pb0

dec r18
breq stopbit1
ror r3 ; put next bit in carry register
brcs bitbang1
nop
cbi portb,0 ; write a 0
nop ; delay 4us
nop
nop
nop
nop
nop
nop
rjmp loop13

bitbang1:

sbi portb,0 ; write a 1
nop ; delay 4us
nop
nop
nop
nop
nop
nop
rjmp loop13

stopbit1: ; stopbit delay

nop
nop
sbi portb,0
ldi r21,9 ; delay 8us

loop14: ; delay 8us

dec r21
brne loop14
nop
nop
nop

databyte2: ; start data packet2

cbi portb,0
ldi r21,2 ; delay 4us

loop22: ; delay 4us

dec r21
brne loop22
nop
ldi r18,9

loop15: ; fetch data

mov r3,r2

loop16: ; shift data out pb0

dec r18
breq stopbit2
ror r3 ; put next bit in carry register
brcs bitbang2
nop
cbi portb,0 ; write a 0
nop ; delay 4us
nop
nop
nop
nop
nop
nop
rjmp loop16

bitbang2:

sbi portb,0 ; write a 1
nop ; delay 4us
nop
nop
nop
nop
nop
nop
rjmp loop16

stopbit2: ; stopbit delay

nop
nop
sbi portb,0
ldi r21,9 ; delay 8us

loop18: ; delay 8us

dec r21
brne loop18
dec r19 ; send out 64 packets
brne jumploop
rjmp adcloop ; fetch more adc info and repeat

jumploop: ; go back to top

rjmp databyte0

