// DMX reciever for atmega328p
// it consumes the USART, so serial transfers cant be used

#define BREAK 100 // break time in us (must be less than 127us)
#define MAB 12 // mark-after-break in us (8 < MAB < 127)
// MAB and BREAK times are not exact
#define SIZE 512 // max frame size, if you want to do it this way
volatile byte dmx_buffer_rx[SIZE]; // allocate buffer space
volatile byte dmx_buffer_tx[SIZE]; // allocate buffer space
unsigned int dmx_ptr_tx = 0; // pointer for tx interrupt
unsigned int dmx_ptr_rx = 0; // pointer for rx interrupt
byte dmx_state_rx = 0; // rx state tracker
volatile byte dmx_state_tx = 0; // tx state tracker

// test variables
byte red = 84;
byte blue = 167;
byte green = 0;
byte r_toggle = 0;
byte g_toggle = 0;
byte b_toggle = 0;

void setup() {
  // initialize uart for data transfer
  cli(); // in case data arrives and triggers an interrupt
  UBRR0H = ((F_CPU/250000/16) - 1) >> 8;
  UBRR0L = ((F_CPU/250000/16) - 1);
  UCSR0A = (1<<RXC0)|(1<<TXC0)|(1<<UDRE0); // clear all interrupt flags
  UCSR0C = (1<<USBS0)|(1<<UCSZ01)|(1<<UCSZ00); // 2 stop bits,8 data bitss
  UCSR0B = (1<<RXCIE0)|(1<<RXEN0); // turn it on, set RX complete intrrupt on
  DDRD |= (1<<DDD1); // set tx pin to output
  PORTD |= (1<<PORTD1); // pull tx pin high
  
  // setup timer2 for break transfer
  TCCR2A = 0; // set to normal mode
  TCCR2B = 0; // shut it off
  TIMSK2 = 0; // turn off interrupts for now
  sei(); // re-enable interrupts
  
  DDRD |= (1<<DDD2); // set tx pin to output
}

void loop() {
 delay(100);
  if (r_toggle) {
    red++;
    if (red == 255) r_toggle = 0;
  }
  else {
    red--;
    if (red == 0) r_toggle = 1;
  }
  if (g_toggle) {
    green++;
    if (green == 255) g_toggle = 0;
  }
  else {
    green--;
    if (green == 0) g_toggle = 1;
  }
  if (b_toggle) {
    blue++;
    if (blue == 255) b_toggle = 0;
  }
  else {
    blue--;
    if (blue == 0) b_toggle = 1;
  }
  int i = 0;
  while (i < (SIZE - 0)) {
    dmx_buffer_tx[i++] = red;
    dmx_buffer_tx[i++] = green;
    dmx_buffer_tx[i++] = blue;
//    dmx_buffer_tx[i] = dmx_buffer_rx[i];
//    i++;
  }
  // send out dmx data - whole frame
  dmx_send();
}

ISR(TIMER2_COMPA_vect) {
  // handles transmitter break frame
  if (dmx_state_tx == 1) {
    // BREAK just finished
    PORTD |= (1<<PORTD1); // pull tx pin high
    OCR2A = ((MAB << 1) - 7); // set up break time
    TCNT2 = 0; // clear timer2 counter
    dmx_state_tx = 2; // set to MAB transfer
  }
  else if (dmx_state_tx == 2) {
    // MAB just finished
    TCCR2B = 0; // shut it off
    TIMSK2 = 0; // turn off interrupt
    UCSR0B = (1<<RXCIE0)|(1<<UDRIE0)|(1<<TXEN0)|(1<<RXEN0); // enable tx and interrupt
    dmx_state_tx = 3; // set to slot0 transmit mode
    while (!( UCSR0A & (1<<UDRE0))); // make sure its ready
    UDR0 = 0; // send slot0 blank space 
  }
  else {
    // error
    TCCR2B = 0; // shut off timer
    TIMSK2 = 0; // turn off interrupt
    UCSR0B = (1<<RXCIE0)|(1<<RXEN0); // disable tx and interrupt
    dmx_state_tx = 0; // set to done 
  }
}

ISR(USART_UDRE_vect) {
  // handle data transfers
  // check for state 4 first as its most probable
  if (dmx_state_tx == 4) {
    UDR0 = dmx_buffer_tx[dmx_ptr_tx];
    dmx_ptr_tx++;
    if (dmx_ptr_tx >= SIZE) {
      UCSR0A |= (1<<TXC0); // clear txc flag
      UCSR0B = (1<<RXCIE0)|(1<<RXEN0)|(1<<TXCIE0)|(1<<TXEN0); //  enable txc and clear udr
      dmx_state_tx = 5; // last byte sent
    }
  }
  else if (dmx_state_tx == 3) {
    UDR0 = dmx_buffer_tx[0]; // send first data byte
    dmx_ptr_tx = 1; // set pointer to next data byte
    dmx_state_tx = 4; // set to data transfer mode
  }
  else {
    UCSR0B = (1<<RXCIE0)|(1<<RXEN0); // turn off tx and interrupts
    dmx_state_tx = 0; // reset - bad condition or done
  }
}

ISR(USART_TX_vect) {
  if (dmx_state_tx == 5) { // last byte sent
    UCSR0B = (1<<RXCIE0)|(1<<RXEN0); // disable tx and interrupts
    dmx_state_tx = 0; // set to waiting
  }
  // else data transfer in progress, but data is delayed
}

void dmx_send() {
  while (dmx_state_tx); // wait for last transmission to complete
  // can only get to this state if tx is off, and interrupts cleared
  PORTD &= ~(1<<PORTD1); // pull tx pin low
  OCR2A = BREAK << 1; // set up break time
  TCNT2 = 0; // clear timer2 counter
  TIFR2 |= (1<<OCF2A); // clear any interrupts
  TIMSK2 = (1<<OCIE2A); // turn on timer2 compare match interrupt
  TCCR2B = (2<<CS20); // Fcpu/8
  dmx_state_tx = 1; // set to BREAK transfer
}

ISR(USART_RX_vect) {
  // check if BREAK byte
  if (UCSR0A & (1<<FE0)) {
    byte temp = UDR0; // get data to clear buffer
    dmx_state_rx = 1; // set to slot0 byte waiting
  }
  // check for state 2 first as its most probable
  else if (dmx_state_rx == 2) {
    dmx_buffer_rx[dmx_ptr_rx] = UDR0; // store data
    dmx_ptr_rx++;
    if (dmx_ptr_rx >= SIZE) {
      dmx_state_rx = 0; // last byte recieved or error
    }
  }
  else if (dmx_state_rx == 1) {
    // check if slot0 = 0
    if (UDR0) {
      dmx_state_rx = 0; // error - reset reciever
    }
    else {
      dmx_ptr_rx = 0; // reset buffer pointer to beginning
      dmx_state_rx = 2; // set to data waiting
    }
  }
  else {
    byte temp = UDR0; // get data to flush buffer
    dmx_state_rx = 0; // reset - bad condition or done
  }
}