/*
 * GccApplication1.c
 *
 * Created: 1/25/2016 9:43:53 PM
 * Author : user
 */ 


#include "sam.h"
#define BUFF_SIZE 12288

uint32_t buffer1a[8]; // codec PDC buffers
uint32_t buffer2a[8];
uint32_t buffer1b[8];
uint32_t buffer2b[8];
uint16_t buffer3[BUFF_SIZE]; // codec write/sd read buffer
uint16_t buffer4[BUFF_SIZE]; // codec read/sd write buffer
volatile uint8_t pdcstate = 0; // PDC state indicator
volatile uint16_t int_ptr = 0; // interrupt pointer
uint16_t write_ptr = 0; // write pointer
uint16_t read_ptr = 0; // read pointer
uint8_t xfrstate = 0; // sd transfer state

int main(void) {
    /* Initialize the SAM system */
    SystemInit();
	WDT->WDT_MR = 1<<15; // disable the watchdog timer
	RTT->RTT_MR = 0x00108000; // disable the RTT
	EFC0->EEFC_FMR = (EFC0->EEFC_FMR & 0xfffff0ff)|0x00000100; // set flash to 1 wait state (datasheet gives cutoff of 21MHz, but IDE says 29MHz)
	PIOA->PIO_OER = 1<<21; // turn on pa20 as output for debug
	
	// setup crystal oscillator (11MHz)
	PMC->CKGR_MOR = (PMC->CKGR_MOR & 0x0300007d)|0x0037ff00; // set startup time to slow, bypass off
	PMC->CKGR_MOR = (PMC->CKGR_MOR & 0x0300ff7c)|0x00370001; // turn on crystal
	while ((PMC->PMC_SR & (1<<0)) == 0); // wait for crystal to stabilize
	PMC->CKGR_MOR = (PMC->CKGR_MOR & 0x0000ff7f)|0x01370000; // switch to crystal, failure detection off
	while ((PMC->PMC_SR & (1<<16)) == 0); // wait for switch to occur
	// there should be more here to verify that the clock is running, but i dont care
	PMC->CKGR_MOR = (PMC->CKGR_MOR & 0x0300ff77)|0x00370000; // disable the RC oscillator
	
	// setup the PLL (crystal x 2)
	PMC->CKGR_PLLAR = 0x20033f02; // turn on PLLA,/2,x4,longest settling time
	while ((PMC->PMC_SR & (1<<1)) == 0); // wait for PLL to stabilize
	PMC->PMC_MCKR = 0x00000002; // MCK and processor clock are PLLA/1
	while ((PMC->PMC_SR & (1<<3)) == 0); // wait for MCK to stabilize
	
	// setup io for codec/SD lines
	PIOC->PIO_CODR = 1<<6; // set pc6 (reset) to low
	PIOC->PIO_OER = 1<<6; // turn on pc6 as output for reset line
	PIOC->PIO_PPDDR = 1<<6; // make sure pulldown is disabled for reset
	PIOC->PIO_PUDR = 1<<6; // disable pullup for reset
	PIOA->PIO_PPDDR = (1<<12)|(1<<26)|(1<<27)|(1<<28)|(1<<29)|(1<<30)|(1<<31); // make sure pulldown is disabled for MISO, and all SD lines
	PIOA->PIO_PUER = (1<<12)||(1<<26)|(1<<27)|(1<<28)|(1<<29)|(1<<30)|(1<<31); // enable pullup for MISO, and all SD lines
	PIOA->PIO_ABCDSR[0] &= ~((1<<11)|(1<<12)|(1<<13)|(1<<14)|(1<<15)|(1<<16)|(1<<17)|(1<<18)|(1<<26)|(1<<27)|(1<<28)|(1<<29)|(1<<30)|(1<<31)); // set to peripheral A
	PIOA->PIO_ABCDSR[1] &= ~((1<<11)|(1<<12)|(1<<13)|(1<<14)|(1<<15)|(1<<16)|(1<<17)|(1<<18)); // set to peripheral A for codec
	PIOA->PIO_ABCDSR[1] |= (1<<26)|(1<<27)|(1<<28)|(1<<29)|(1<<30)|(1<<31); // set to peripheral C for HSMCI
	PIOA->PIO_PDR = (1<<11)|(1<<12)|(1<<13)|(1<<14)|(1<<15)|(1<<16)|(1<<17)|(1<<18)|(1<<26)|(1<<27)|(1<<28)|(1<<29)|(1<<30)|(1<<31); // turn off pio controller for these pins
	
	PMC->PMC_PCER0 = (1<<11); // turn on PIOA clock for debug
	
	// setup SPI
	PMC->PMC_PCER0 = (1<<21); // turn on SPI clock
	SPI->SPI_MR = 0x00000011; // master mode, CS0
	SPI->SPI_CSR[0] = 0x00000402; // CPOL=0,PHA=1,8b,CK/4
	SPI->SPI_CR = 1<<0; // enable SPI
	
	for (int32_t i = 0; i < 100000; i++) ; // delay for a bit
	
	//setup codec
	PIOC->PIO_SODR = 1<<6; // set reset high
	for (int32_t i = 0; i < 10000; i++) ; // delay for a bit
	while ((SPI->SPI_SR & (1<<1)) == 0) ; // wait for buffer to be empty
	SPI->SPI_TDR = 0x9e; // send address
	while ((SPI->SPI_SR & (1<<1)) == 0) ; // wait for buffer to be empty
	SPI->SPI_TDR = 0x02; // send MAP - PDN register
	while ((SPI->SPI_SR & (1<<1)) == 0) ; // wait for buffer to be empty
	SPI->SPI_TDR = 0x00; // send data - power down
	for (int32_t i = 0; i < 10000; i++) ; // delay for a bit
	while ((SPI->SPI_SR & (1<<1)) == 0) ; // wait for buffer to be empty
	SPI->SPI_TDR = 0x9e; // send address
	while ((SPI->SPI_SR & (1<<1)) == 0) ; // wait for buffer to be empty
	SPI->SPI_TDR = 0x02; // send MAP - PDN register
	while ((SPI->SPI_SR & (1<<1)) == 0) ; // wait for buffer to be empty
	SPI->SPI_TDR = 0x00; // send data - power up
	
	
	// setup SSC
	PMC->PMC_PCER0 = (1<<22); // turn on SSC clock
	SSC->SSC_CMR = 1; // SSC clock = MCK/2
	SSC->SSC_RCMR = 0x00000121; // RX clocked from TK, continuous mode, no delays, start on TXEN, sample in rising edge
	SSC->SSC_RFMR = 0x0000079f; // RX msb first, 32b data, 8 data per frame
	SSC->SSC_TCMR = 0x7f000404; // TX clocked from MCK, continuous, no delays, frame every 32x8 clocks
	SSC->SSC_TFMR = 0x00a0079f; //TX msb first, 32b data, 8 data per frame, output TF
	SSC->SSC_RPR = (uint32_t)buffer1b; // setup PDC channels RX and TX buffer pointers
	SSC->SSC_TPR = (uint32_t)buffer1a;
	SSC->SSC_RNPR = (uint32_t)buffer2b;
	SSC->SSC_TNPR = (uint32_t)buffer2a;
	SSC->SSC_RCR = 8; // setup RX and TX buffer sizes
	SSC->SSC_TCR = 8;
	SSC->SSC_RNCR = 8;
	SSC->SSC_TNCR = 8;
	//SSC->SSC_CR = (1<<0)|(1<<8); // enable TX and RX
	//SSC->SSC_PTCR = (1<<8)|(1<<0); // enable PDC channels
	
	// turn off pullups for codec lines
	PIOA->PIO_PPDDR = (1<<11)|(1<<13)|(1<<14)|(1<<15)|(1<<16)|(1<<17); // make sure pulldown is disabled for output lines
	PIOA->PIO_PUDR = (1<<11)|(1<<13)|(1<<14)|(1<<15)|(1<<16)|(1<<17); // disable pullup for output lines
	

	// setup HSMCI
	PMC->PMC_PCER0 = (1<<18); // turn on HSMCI clock
	HSMCI->HSMCI_MR = (27<<0); // ck/2*(27+1) = 400khz (slowest speed for initialization)
	HSMCI->HSMCI_DTOR = (7<<4)|(15<<0); // data transfer timeout = 16x10 clock cycles
	HSMCI->HSMCI_CSTOR = (7<<4)|(15<<0); // completion time out register
	HSMCI->HSMCI_CR = (1<<0); // turn on the HSMCI
	// send 74 clocks to initialize
	HSMCI->HSMCI_ARGR = 0xffffffff; // keep line high
	HSMCI->HSMCI_CMDR = (1<<11)|(1<<8); // send init command, no response, open drain
	// send CMD0 to set idle state
	HSMCI->HSMCI_ARGR = 0; // stuff bits
	HSMCI->HSMCI_CMDR = 0; // no response
	while (!(HSMCI->HSMCI_SR & (1<<0))) ; // wait till command transfer is complete
	// send CMD8 to set voltage level for old cards
	HSMCI->HSMCI_ARGR = 0x000001aa; // 2.7-3.6v, check sequence aa
	HSMCI->HSMCI_CMDR = (1<<12)|(1<<6)|(8<<0); // 48b response, 64 cycle latency
	while (!(HSMCI->HSMCI_SR & (1<<0))) ; // wait till command transfer is complete
	while (!(HSMCI->HSMCI_RSPR[0] & (0x000001aa))) ; // see if you get the right response
	// send ACMD41 to initialize the card - keep sending until initialization bit is set
	do {
		HSMCI->HSMCI_ARGR = 0; // RCA = 0, rest stuff bits
		HSMCI->HSMCI_CMDR = (1<<12)|(1<<6)|(55<<0); // 48b response, 64 cycle latency
		while (!(HSMCI->HSMCI_SR & (1<<0))) ; // wait till command transfer is complete
		while (!(HSMCI->HSMCI_RSPR[0] & (0x00000020))) ; // see if you get the right response (ACMD, could do mode checking here as well)
		HSMCI->HSMCI_ARGR = 0x50300000; // 3.2-3.4v, HC/XC supported, powersave off
		HSMCI->HSMCI_CMDR = (1<<12)|(1<<6)|(41<<0); // 48b response, 64 cycle latency
		while (!(HSMCI->HSMCI_SR & (1<<0))) ; // wait till command transfer is complete
	}
	while (!(HSMCI->HSMCI_RSPR[0] & (0x80000000))) ; // check for initialization bit
	while (!(HSMCI->HSMCI_RSPR[0] & (0x00300000))) ; // check that it accepts the voltage (can add more here later)
	PIOA->PIO_CODR = 1<<21; // debug pin low
	// send CMD2 to get CID - not sure if required
	HSMCI->HSMCI_ARGR = 0; // stuff bits
	HSMCI->HSMCI_CMDR = (0<<12)|(2<<6)|(2<<0); // 136b response, 64 cycle latency
	while (!(HSMCI->HSMCI_SR & (1<<0))) ; // wait till command transfer is complete
//	test1 = HSMCI->HSMCI_RSPR[1];
//	test2 = HSMCI->HSMCI_RSPR[0];
//	test3 = HSMCI->HSMCI_RSPR[2];
//	test4 = HSMCI->HSMCI_RSPR[3];
	// send CMD3 to get RCA
	uint32_t sd_rca = 0;
	do {
		HSMCI->HSMCI_ARGR = 0; // stuff bits
		HSMCI->HSMCI_CMDR = (1<<12)|(1<<6)|(3<<0); // 48b response, 64 cycle latency
		while (!(HSMCI->HSMCI_SR & (1<<0))) ; // wait till command transfer is complete
		while (!(HSMCI->HSMCI_RSPR[0] & (0x00000520))) ; // do error checking here if wanted
		sd_rca = (HSMCI->HSMCI_RSPR[0] & 0xffff0000); // create RCA
	}
	while (!sd_rca) ; // make sure you get a non-zero RCA
	// send CMD9 to get CSD - not sure if required
	HSMCI->HSMCI_ARGR = sd_rca; // RCA + stuff bits
	HSMCI->HSMCI_CMDR = (1<<12)|(2<<6)|(9<<0); // 136b response, 64 cycle latency
	while (!(HSMCI->HSMCI_SR & (1<<0))) ; // wait till command transfer is complete
//	test1 = HSMCI->HSMCI_RSPR[1];
//	test2 = HSMCI->HSMCI_RSPR[0];
//	test3 = HSMCI->HSMCI_RSPR[2];
//	test4 = HSMCI->HSMCI_RSPR[3];
	// send CMD4 if you want to set driver strength - probably not required
	// send CMD7 to set to transfer state
	HSMCI->HSMCI_ARGR = sd_rca; // RCA + stuff bits
	HSMCI->HSMCI_CMDR = (1<<12)|(3<<6)|(7<<0); // R1b response, 64 cycle latency
	while (!(HSMCI->HSMCI_SR & (1<<0))) ; // wait till command transfer is complete
	while (!(HSMCI->HSMCI_SR & (1<<5))) ; // wait till busy bit clears
	while (!(HSMCI->HSMCI_RSPR[0] == (0x00000700))) ; // check that it is in the right state
	// ACMD13 - get SD status
	static uint32_t datacheck[128];
	HSMCI->HSMCI_MR &= ~(1<<15); // clear PDCMODE - probably already cleared
	HSMCI->HSMCI_BLKR = (64<<16)|(1<<0); // set block length and number of blocks
	HSMCI->HSMCI_ARGR = sd_rca; // RCA, rest stuff bits
	HSMCI->HSMCI_CMDR = (1<<12)|(1<<6)|(55<<0); // 48b response, 64 cycle latency
	while (!(HSMCI->HSMCI_SR & (1<<0))) ; // wait till command transfer is complete
	while (!(HSMCI->HSMCI_RSPR[0] & (0x00000020))) ; // see if you get the right response (ACMD, could do mode checking here as well)
	HSMCI->HSMCI_ARGR = 0; // stuff bits
	HSMCI->HSMCI_CMDR = (1<<18)|(1<<16)|(1<<12)|(1<<6)|(13<<0); // 48b response, 64 cycle latency, start data transfer, read, single block
	while (!(HSMCI->HSMCI_SR & (1<<0))) ; // wait till command transfer is complete
	for (uint32_t m = 0; m < 16; m++) {
		while (!(HSMCI->HSMCI_SR & (1<<1))) ; // see if its ready for data
		datacheck[m] = HSMCI->HSMCI_RDR;
	}
	// ACMD51 - get SCR
//	static uint32_t datacheck[128];
	HSMCI->HSMCI_MR &= ~(1<<15); // clear PDCMODE - probably already cleared
	HSMCI->HSMCI_BLKR = (8<<16)|(1<<0); // set block length and number of blocks
	HSMCI->HSMCI_ARGR = sd_rca; // RCA, rest stuff bits
	HSMCI->HSMCI_CMDR = (1<<12)|(1<<6)|(55<<0); // 48b response, 64 cycle latency
	while (!(HSMCI->HSMCI_SR & (1<<0))) ; // wait till command transfer is complete
	while (!(HSMCI->HSMCI_RSPR[0] & (0x00000020))) ; // see if you get the right response (ACMD, could do mode checking here as well)
	HSMCI->HSMCI_ARGR = 0; // stuff bits
	HSMCI->HSMCI_CMDR = (1<<18)|(1<<16)|(1<<12)|(1<<6)|(51<<0); // 48b response, 64 cycle latency, start data transfer, read, single block
	while (!(HSMCI->HSMCI_SR & (1<<0))) ; // wait till command transfer is complete
	for (uint32_t m = 0; m < 2; m++) {
		while (!(HSMCI->HSMCI_SR & (1<<1))) ; // see if its ready for data
		datacheck[m] = HSMCI->HSMCI_RDR;
	}
	// send ACMD6 to set bus width
	HSMCI->HSMCI_ARGR = sd_rca; // RCA + stuff bits
	HSMCI->HSMCI_CMDR = (1<<12)|(1<<6)|(55<<0); // 48b response, 64 cycle latency
	while (!(HSMCI->HSMCI_SR & (1<<0))) ; // wait till command transfer is complete
	while (!(HSMCI->HSMCI_RSPR[0] & (0x00000020))) ; // see if you get the right response (ACMD, could do mode checking here as well)
	HSMCI->HSMCI_ARGR = 2; // 4b bus
	HSMCI->HSMCI_CMDR = (1<<12)|(1<<6)|(6<<0); // R1 response, 64 cycle latency
	while (!(HSMCI->HSMCI_SR & (1<<0))) ; // wait till command transfer is complete
	while (!(HSMCI->HSMCI_RSPR[0] & (0x00000700))) ; // check that it is in the right state
	// set HSMCI to 4bit bus
	HSMCI->HSMCI_SDCR = (2<<6);
	// send ACMD42 to turn off pullup on CD line
	HSMCI->HSMCI_ARGR = sd_rca; // RCA + stuff bits
	HSMCI->HSMCI_CMDR = (1<<12)|(1<<6)|(55<<0); // 48b response, 64 cycle latency
	while (!(HSMCI->HSMCI_SR & (1<<0))) ; // wait till command transfer is complete
	while (!(HSMCI->HSMCI_RSPR[0] & (0x00000020))) ; // see if you get the right response (ACMD, could do mode checking here as well)
	HSMCI->HSMCI_ARGR = 0; // pullup off
	HSMCI->HSMCI_CMDR = (1<<12)|(1<<6)|(42<<0); // R1 response, 64 cycle latency
	while (!(HSMCI->HSMCI_SR & (1<<0))) ; // wait till command transfer is complete
	while (!(HSMCI->HSMCI_RSPR[0] & (0x00000700))) ; // see if you get the right response
	// increase speed
	HSMCI->HSMCI_MR = HSMCI->HSMCI_MR & 0xffffff00; // set to masterclock/2

	// fill read buffer to begin with
	static uint32_t sdread = 0x00001000;
	HSMCI->HSMCI_BLKR = (512<<16)|(48<<0); // set block length and number of blocks - 0 for infinite
	HSMCI->HSMCI_MR |= (1<<15); // set PDCMODE
	
	// CMD18 - read multiple blocks from sd
	HSMCI->HSMCI_RPR = (uint32_t)buffer4; // set memory location to read to
	HSMCI->HSMCI_RCR = (BUFF_SIZE/2); // set number of words to transfer - half the number of ints
	HSMCI->HSMCI_PTCR = (1<<0); // enable the PDC channel
	HSMCI->HSMCI_ARGR = sdread; // address in bytes for SD, in blocks for HC/XC
	HSMCI->HSMCI_CMDR = (1<<19)|(1<<18)|(1<<16)|(1<<12)|(1<<6)|(18<<0); // 48b response, 64 cycle latency, start data transfer, read, multiple block
	while (!(HSMCI->HSMCI_SR & (1<<0))) ; // wait till command transfer is complete
	while (!(HSMCI->HSMCI_RSPR[0] & (0x00000900))) ; // see if you get the right response
	sdread += (2*BUFF_SIZE); // read address by number of bytes read - 2x the number of ints
	while (!(HSMCI->HSMCI_SR & (1<<6))) ; // wait for transfer to complete
	HSMCI->HSMCI_PTCR = (1<<1); // turn off PDC
	
	// CMD12 - stop transmission
	HSMCI->HSMCI_ARGR = 0; // stuff bits
	HSMCI->HSMCI_CMDR = (1<<12)|(3<<6)|(12<<0); // R1b response, 64 cycle latency
	while (!(HSMCI->HSMCI_SR & (1<<0))) ; // wait till command transfer is complete
	while (!(HSMCI->HSMCI_SR & (1<<5))) ; // wait till busy bit clears
	
	//turn on SSC
	SSC->SSC_CR = (1<<0)|(1<<8); // enable TX and RX
	SSC->SSC_PTCR = (1<<8)|(1<<0); // enable PDC channels
	SSC->SSC_IER = (1<<2); // enable TXbuff empty interrupt
	static uint32_t sdwrite = 0x00008000;
	NVIC->ISER[0]=(1<<22); // enable SSC interrupt
	
	while (1) { // all subsequent data transfers
		static int32_t test1 = 0;
		int32_t test2 = 0;	
		do {
			test1 = int_ptr - write_ptr;
			if (test1 < 0) test1 += BUFF_SIZE;
			if (test1 < 256) test1 = 0;
			test2 = int_ptr - read_ptr;
			if (test2 < 0) test2 += BUFF_SIZE;
			if (test2 < BUFF_SIZE/2) test2 = 0;
		}
		//PIOA->PIO_SODR = 1<<21; // debug pin high
		while ((test1 < 1)&&(test2 < 1)) ; // wait for at least 512 bytes to load into the buffer
		//PIOA->PIO_SODR = 1<<21; // debug pin high
		if (test2) { // check if read buffer needs filling
			if (xfrstate) { // check if currently in write mode
				PIOA->PIO_SODR = 1<<21; // debug pin high
				// CMD12 - stop transmission
				HSMCI->HSMCI_PTCR = (1<<9); // turn off PDC
				HSMCI->HSMCI_ARGR = 0; // stuff bits
				HSMCI->HSMCI_CMDR = (2<<16)|(1<<12)|(3<<6)|(12<<0); // R1b response, 64 cycle latency
				while (!(HSMCI->HSMCI_SR & (1<<0))) ; // wait till command transfer is complete
				xfrstate = 0; // reset transfer state
				while (!(HSMCI->HSMCI_SR & (1<<5))) ; // wait till busy bit clears
				PIOA->PIO_CODR = 1<<21; // debug pin low
				//PIOA->PIO_CODR = 1<<21; // debug pin high
				//while (!(PIOA->PIO_PDSR & (1<<30))) ; // wait till busy clears	
			}
			// CMD18 - read multiple blocks from sd
			HSMCI->HSMCI_BLKR = (512<<16)|(24<<0); // set block length and number of blocks - 0 for infinite
			HSMCI->HSMCI_RPR = (uint32_t)(&buffer4[read_ptr]); // set memory location to read to
			HSMCI->HSMCI_RCR = (BUFF_SIZE/4); // set number of words to transfer - half the number of ints
			HSMCI->HSMCI_PTCR = (1<<0); // enable the PDC channel
			HSMCI->HSMCI_ARGR = sdread; // address in bytes for SD, in blocks for HC/XC
			HSMCI->HSMCI_CMDR = (1<<19)|(1<<18)|(1<<16)|(1<<12)|(1<<6)|(18<<0); // 48b response, 64 cycle latency, start data transfer, read, multiple block
			while (!(HSMCI->HSMCI_SR & (1<<0))) ; // wait till command transfer is complete
			while (!(HSMCI->HSMCI_RSPR[0] & (0x00000900))) ; // see if you get the right response
			sdread += (BUFF_SIZE); // read address by number of bytes read - 2x the number of ints
			read_ptr += BUFF_SIZE/2;
			if (read_ptr >= BUFF_SIZE) read_ptr = 0; // deal with rollover
			while (!(HSMCI->HSMCI_SR & (1<<6))) ; // wait for transfer to complete
			HSMCI->HSMCI_PTCR = (1<<1); // turn off PDC
			
			// CMD12 - stop transmission
			HSMCI->HSMCI_ARGR = 0; // stuff bits
			HSMCI->HSMCI_CMDR = (1<<12)|(3<<6)|(12<<0); // R1b response, 64 cycle latency
			while (!(HSMCI->HSMCI_SR & (1<<0))) ; // wait till command transfer is complete
			while (!(HSMCI->HSMCI_SR & (1<<5))) ; // wait till busy bit clears
		
		}
		else {
			if (xfrstate) { // mid-write - dont need to send the command again
				// CMD25 - write multiple blocks to sd
				HSMCI->HSMCI_TPR = (uint32_t)(&buffer3[write_ptr]); // set memory location to take from
				HSMCI->HSMCI_TCR = 128; // set number of words (512 bytes = 128 words) to transfer
				sdwrite += 512; // increment write block
				write_ptr += 256; // increment write pointer
				if (write_ptr >= BUFF_SIZE) write_ptr = 0; // deal with rollover
				while (!(HSMCI->HSMCI_SR & (1<<3))) ; // wait for transfer to complete
			}
			else { // first write - send command
				//PIOA->PIO_SODR = 1<<21; // debug pin high
				// CMD25 - write multiple blocks to sd
				HSMCI->HSMCI_BLKR = (512<<16)|(0<<0); // set block length and number of blocks - 0 for infinite
				HSMCI->HSMCI_TPR = (uint32_t)(&buffer3[write_ptr]); // set memory location to take from
				HSMCI->HSMCI_TCR = 128; // set number of words (512 bytes = 128 words) to transfer
				HSMCI->HSMCI_ARGR = sdwrite; // address in bytes for SD, in blocks for HC/XC
				HSMCI->HSMCI_CMDR = (1<<19)|(1<<16)|(1<<12)|(1<<6)|(25<<0); // 48b response, 64 cycle latency, start data transfer, write, multiple block
				while (!(HSMCI->HSMCI_SR & (1<<0))) ; // wait till command transfer is complete
				while (!(HSMCI->HSMCI_RSPR[0] & (0x00000900))) ; // see if you get the right response
				HSMCI->HSMCI_PTCR = (1<<8); // enable the PDC channel
				sdwrite += 512; // increment write block
				write_ptr += 256; // increment write pointer
				if (write_ptr >= BUFF_SIZE) write_ptr = 0; // deal with rollover
				xfrstate = 1; // set transfer state to mid-write
				while (!(HSMCI->HSMCI_SR & (1<<3))) ; // wait for transfer to complete
			}	
		}
		//PIOA->PIO_CODR = 1<<21; // debug pin low
	}
}

inline void SSC_Handler (void) {
	//PIOA->PIO_SODR = 1<<21; // debug pin high
	if (!pdcstate) {
		SSC->SSC_TNPR = buffer1a; // setup next buffers
		SSC->SSC_RNPR = buffer1b;
		SSC->SSC_TNCR = 8; // setup next buffer size
		SSC->SSC_RNCR = 8;
		pdcstate = 1; // flip state
		for (uint8_t i = 0; i < 8; i++) {
			buffer3[int_ptr + i] = (uint16_t)(buffer1b[i] >> 16); // store data - reduce to 16b
			//buffer1a[i] = buffer1b[i]; // passthrough
			buffer1a[i] = (uint32_t)(buffer4[int_ptr + i] << 16); // read data - increase to 32b
		}
		buffer1a[0] = buffer1b[0]; // test
	}
	else {
		SSC->SSC_TNPR = buffer2a; // setup next buffers
		SSC->SSC_RNPR = buffer2b;
		SSC->SSC_TNCR = 8; // setup next buffer size
		SSC->SSC_RNCR = 8;
		pdcstate = 0; // flip state
		for (uint8_t i = 0; i < 8; i++) {
			buffer3[int_ptr + i] = (uint16_t)(buffer2b[i] >> 16); // store data - reduce to 16b
			//buffer2a[i] = buffer2b[i]; // passthrough
			buffer2a[i] = (uint32_t)(buffer4[int_ptr + i] << 16); // read data - increase to 32b
		}
		buffer2a[0] = buffer2b[0]; // test
	}
	int_ptr += 8; // increment pointer
	if (int_ptr >= BUFF_SIZE) {
		int_ptr = 0; // do buffer pointer rollover
		
	}
	//PIOA->PIO_CODR = 1<<21; // debug pin low
}