Detailed Backannotation Procedure

This procedure assumes you have a board layout open in Pads. For the purposes of illustration, assume your schematic is split into two pages in the files pg1.sch and pg2.sch.

1. Create an up to date Pads netlist by running ``gnetlist -g pads -o mynet.asc pg1.sch pg2.sch''. This will create the netlist file ``mynet.asc''.

2. From within Pads, choose the ``Tools$\rightarrow$Compare Netlist'' menu item and choose the following options in the form.
   
   

   original design to compare:	mynet.asc
   new design with changes:	use current PCB design
   $\surd$	generate differences report
   $\surd$	generate eco file
   comparison options
   $\surd$	compare only ECO registered parts
   attribute comparison level
   $\surd$	ignore all attributes

   
   Click the OK button to create the ECO file.

3. Examine the ECO file to make sure it looks ok (the ECO file is a text file which can be viewed with any text editor).

4. Make a backup copy of your gEDA schematic files in case things fail in a destructive way.

5. Run ``pads_backannotate file.eco pg1.sch pg2.sch | tee backanno.log'' where file.eco is the name of the ECO file created previously and pg1.sch and pg2.sch are all of your schematic pages. This will apply the reference designator change portion of the ECO file and also generate a list of pin and slot swapping which must be performed by hand. The file backanno.log will contain a log of the session that can be refered to when performing the pin and slot swapping.