Department of Chemical Engineering
Room 66-217
Massachusetts Institute of Technology
77 Massachusetts Avenue
Cambridge, MA 02139-4307 USA

Telephone (617) 253-6586
Email: hkawai@mit.edu

Figure 1

Hiroyo Kawai

Graduate Research Assistant

Research Interests

Modeling and Feature Scale Profile Simulation of Polysilicon Etching and Roughening 

Modern integrated circuits (IC) are composed of metal-oxide semiconductor (MOS) transistors, and it is necessary to make the device density as high as possible in order to achieve fast speeds. Technology improvements over the past years have made it possible to decrease the minimum feature size to about 0.13 micro-m in 2002. However, as the feature size continues to shrink, many steps in manufacturing process become challenging. One of these steps is the etching process of poly-silicon used in gate electrodes in MOS devices. As the line width of the feature shrinks, sidewall roughness or line edge roughening (LER) becomes a significant issue because the size of variation of width due to LER becomes comparable to the size of line width itself.

The goal of my project is to model and simulate the roughness on the sidewall by incorporating experimental etching yields as a function of various parameters such as ion incident angle, ion energy and ion/neutral flux. The simulated roughness will then be compared with the experimentally observed roughness to gain a fundamental understanding of causes of surface roughness formation to help develop a process that prevents surface roughening or smoothes the surface. Since surface roughness is a property that is inherently 3-D, we must develop a 3-D simulator instead of 2-D simulator. The simulation domain is discretized into a cellular array of cells as shown in Figure 1, and the Monte Carlo method is used to sample stochastic variables from certain probability distributions. Figure 2 shows the sample feature without any sidewall roughness.

Figure 2