Department
of Chemical Engineering
Room 66-217
Massachusetts Institute of Technology
77 Massachusetts Avenue
Cambridge, MA 02139-4307 USA
Telephone (617) 253-6586
Email: yinyp@mit.edu
Yunpeng Yin
Graduate Research Assistant
B.S., Chem. Engr., Tsinghua University, PRC, 1999M.S., Chem. Engr.Practice, M.I.T., 2004
Research Interests
Polysilicon Surface/sidewall Roughness during Plasma Etching
For the patterning of sub 100 nm features, a clear understanding of the origin and control of line edge roughness (LER) is extremely desirable, both from a fundamental as well as a manufacturing perspective. At such small dimensions, resist sidewall roughness during the development will play a significant role in the critical dimension of error budget for lithography. Also, the photoresist sidewall roughness has recently been shown to transfer with the subsequent processing such as reactive ions etching. In addition, plasma etching processes often roughen the feature sidewalls, leading to the formation of anisotropic striations. It is this post-etch sidewall roughness that will ultimately effect device performance.
My project focuses on the mechanism of surface/sidewall roughness during plasma etching. A newly designed beam chamber has been built, in which the ion energy and the ion flux can be controlled independently. The off-normal angle of the wafer can also be manipulated easily in this chamber. As a result, a sidewall can be simulated by rotating the sample to a glancing angle. The surface roughness evolution of polysilicon with various parameters during plasma etching will be explored and explained by combining the knowledge of surface kinetics during plasma etching and the 3-D simulation model developed by Hiroyo Kawai and Weidong Jin.