Design and Exploration of Computer Architecture Using the Heracles Multicore System
Michel Kinsy
Tue Jan 17, Wed Jan 18, Thu Jan 19, Tue Jan 24, Wed Jan 25, 11am-12:30pm, 4-149
Enrollment limited: advance sign up required (see contact below)
Signup by: 15-Jan-2012
Limited to 12 participants.
Participants requested to attend all sessions (non-series)
Prereq: programming in C and C++; familiar with Verilog
The goal of this IAP class is to perform multi-core and many-core architectures design space exploration using the Heracles Multicore System infrastructure. Heracles is an open-source complete multicore system written in Verilog. It is fully parameterized and can be reconfigured and synthesized into different topologies and sizes. It comes with a C toolchain for software development. During the class we will examine different implementation choices: core microarchitecture, levels of caches, cache sizes, routing algorithm, router micro-architecture, distributed or shared memory, or network interface, and evaluate their impact on the overall system performance.
Please bring a charged laptop with windows installed
Contact: Michel Kinsy, mkinsy@mit.edu
Sponsor: Electrical Engineering and Computer Science
Latest update: 20-Dec-2011
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