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Course Summary Learning Objectives Who Should Attend Program Outline Schedule About the Lecturers Apply

High-Speed I/O Design Techniques [6.22s]

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Date: June 23-25, 2008 | Tuition: $2,000 | Continuing Education Units (CEUs): 2.0

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* Course schedule and registration times

Please note that laptops are required for this course.

Course Summary

This course covers the circuit and system design of equalized high-speed I/Os. Today's high-speed interfaces are limited by the bandwidth of the communication channel, tight power constraints, and noise sources that differ from those in standard communication systems. The wire bandwidth limitations make straight circuit solutions inefficient and the power and area constraints make standard digital communication approaches infeasible. Efficient solutions require bridging the fields of digital communications, optimization, statistical, and dynamic system modeling with system architecture, mixed-signal, and digital circuit design. This course will lay the groundwork for this type of system-driven I/O design by covering each of the required layers in link system hierarchy.

Basics of channel properties are introduced first followed by modeling, measurements, and communications techniques. The course then focuses on different link equalization techniques, comparing them both from system perspective and from the performance of resulting circuit implementations. Some examples will cover trade-offs between transmit pre-emphasis and decision-feedback equalization, linear analog receiver equalization, as well as joint modulation/equalization and equalization/coding techniques (like PAM4, duobinary and multitone signaling). Implementations of transmitter FIR equalizers, several DFE receiver topologies, and peaking amplifiers will be discussed in detail. Several adaptive techniques for equalizer tuning and link monitoring will also be presented.

Learning Objectives

The participants of this course will be able to:

1. Understand the components of a typical high-speed link channel and relate them to link performance and overall channel response.
2. Construct an open-loop and adaptive equalizer to correct for the channel frequency selectivity.
3. Apply different inter-symbol and noise models and run statistical simulation of link performance.
4. Understand basic concepts in link transmitter and receiver circuit design.
5. Describe trade-offs and design of advanced transmit and receiver equalization circuits.
6. Extract key trade-offs between inter-symbol interference and circuit induced noise for different modulation and equalization techniques.
7. Analyze state-of-the-art methods for link data and clock recovery.
8. Apply adaptive equalization algorithms.
9. Construct a real-time behavioral simulation of critical link blocks (adaptive equalizer, clock and data recovery).
10. Analyze circuit behavior of critical link circuits through circuit simulation.

Who Should Attend

This course is targeted towards integrated circuit, system, and signal-integrity engineers and students who wish to gain better understanding of all the layers involved in design of high-speed interconnects. It can serve both as an entry point into the area and also as a review of the state-of-the-art practices in high-speed I/O design, both in industry and academia. A basic background in electrical engineering is required.

Program Outline

This course consists of 2 days of instruction and 1 day of labs in link performance simulation, system and circuit design of most critical blocks.

Day 1
Background and Motivation; Link Channel Environment; Equalization and Modulation

1. Introduction

2. Background and Motivation

1. I/O link applications
2. Channel properties
3. Transmitter and receiver overview
4. Circuit limitations

3. Link Channel Environment

1. Description of link channel environment (transmission lines, connectors, packages)
2. Basic transmission line theory
3. Lossy transmission lines (skin-effect, dielectric loss, edge-roughness)
4. Understanding impedance discontinuities and reflections
5. Impact of packages and on-chip terminations
6. Channel component design examples
7. Putting it all together

4. Equalization and Modulation

1. Understanding the inter-symbol interference and cross-talk
2. Linear equalization algorithms
3. Decision feedback equalization algorithms
4. Adaptive equalization
5. Multi-level modulation on bandlimited channels
6. Partial-response signaling
   

Day 2
Link Modeling; Lab 1

1. Link Modeling

1. Overview of current models (worst-case, standard statistical)
2. Accurate statistical modeling of intersymbol-interference and cross-talk
3. Timing noise modeling
4. Bit-error rate modeling

2. Lab 1

1. Design of linear and decision-feedback equalizers (Matlab simulations)
2. Multi-level signaling
3. Statistical link modeling simulations (Matlab)
4. Adaptive equalization (Matlab/CppSim)

Course Participant Dinner at a Local Restaurant

Day 3
Link System Implementations (Equalization, Clock Recovery); Lab 2

1. Link System Implementations

1. Link system design (equalizer type trade-offs, adaptive equalization, back-channel)
2. Transmitter implementations (driver design, transmit pre-emphasis)
3. Receiver implementations (pre-amplifier, decision circuits, decision-feedback)
4. Clock and data recovery
5. Link monitoring and adaptation circuits

2. Lab 2

1. Link behavioral simulations (decision-feedback equalizer and data-recovery)
2. Circuit simulations – filtering and sampling receiver implementations (pre-amplifier, decision circuits, loop-unrolled decision-feedback)
   
   

Course schedule, registration times, special events

Class runs 9:00 am - 5:00 pm each day.

Registration is on Monday morning from 8:00 - 8:45 am.

Please note that laptops are required for this course.

Daily Schedule:

9:00am - 10:00am - First Session
10:00am - 10:30am - Break
10:30am - 12:30pm - Second Session
12:30pm - 1:30pm - Lunch
1:30pm - 3:00pm - Third Session
3:00pm - 3:30pm - Break
3:30pm - 5:00pm - Fourth Session

About The Lecturers

Vladimir Stojanovic
Professor Vladimir Stojanovic is an Assistant Professor of Electrical Engineering and Computer Science at MIT and a principal investigator in the Research Laboratory of Electronics (RLE) and Microsystems Technology Laboratories (MTL). He received the Dipl. Ing. from the University of Belgrade in 1998, the M.S.E.E. and Ph.D. from Stanford University in 2000 and 2005 respectively. From 1999 to 2004, he was Principal Engineer in the Logic Interface Division of Rambus, Inc.

His current research interests include design, modeling, and optimization of integrated systems, from standard VLSI blocks to CMOS-based electrical and optical interfaces. He is also interested in design and implementation of digital communication techniques in high-speed interfaces and high-speed mixed-signal IC design. He leads the Integrated Systems Group at MIT.

At Stanford, Prof. Stojanovic was engaged in circuit and system design of high-speed electrical links, hierarchical modeling and convex optimization of VLSI systems, and system design of modal compensation techniques in multi-mode fiber links. At Rambus, Vladimir was one of the main contributors to the development of Rambus’ next generation high-speed serial link technology (circuit and systems techniques for adaptive, equalized links, with multi-level modulation and advanced clock and data recovery). He holds 10 patents in the area of high-speed circuits and serial links.

For more information on Prof. Stojanovic’s research and teaching activities you may visit http://www.rle.mit.edu/isg.