* Simple Beta

.include "/mit/6.004/jsim/nominal.jsim"
.include "/mit/6.004/jsim/stdcell.jsim"
.include "/mit/6.004/jsim/proj3checkoff.jsim"

* PC register

.subckt PCreg clk D[31:0] Q[31:0]
Xregs D[31:0] clk#32 Q[31:0] dreg
.ends

* PC adder

.subckt PCadder A[31:0] S[31:0]
Xlink S[1:0] C1 A[1:0] vdd wire
Xcar C[29:1] A[30:2] tmp[30:2] nand2
Xtemp tmp[30:2] C[30:2] inverter
Xadd A[31:2] C[30:1] S[31:2] xor2
.ends

* 32-bit adder
.subckt sum32 A[31:0] C[31:0] S[31:0]
X1 a[7:0] c[7:0] 0 s[7:0] cone adder8
Xbuff cone ctwo cthree conea ctwoa cthreea inverter
Xbuff2 conea ctwoa cthreea coneb ctwob cthreeb inverter_2
Xground GND constant0
Xhigh HIGH constant1
X2s coneb#9 szero[15:8] ctwo0 sone[15:8] ctwo1 s[15:8] ctwo mux2
X20 a[15:8] c[15:8] GND szero[15:8] ctwo0 adder8
X21 a[15:8] c[15:8] HIGH sone[15:8] ctwo1 adder8
X3s ctwob#9 szero[23:16] cthree0 sone[23:16] cthree1 s[23:16] cthree mux2
X30 a[23:16] c[23:16] GND szero[23:16] cthree0 adder8
X31 a[23:16] c[23:16] HIGH sone[23:16] cthree1 adder8
X4s cthreeb#8 szero[31:24] sone[31:24] s[31:24] mux2
X40 a[31:24] c[31:24] GND szero[31:24] cfour0 adder8
X41 a[31:24] c[31:24] HIGH sone[31:24] cfour1 adder8
.ends

* CS wiring
.subckt wire A B
.connect A B
.ends

* r31 logic
.subckt r31catch addr[4:0] A[31:0] S[31:0]
Xan1 addr[4:3] tmp1 nand2
Xan2 addr[2:0] tmp0 nand3
Xan3 tmp[1:0] sel nor2  // 1 if r31, 0 ow
Xmuxes sel#32 A[31:0] 0#32 S[31:0] mux2  //buffer sel to speed up tpd
.ends

* register file
.subckt regfile A[20:16] adata[31:0] B[4:0] bdata[31:0] clk werf W[4:0] wdata[31:0]
Xreggie
+ vdd 0 0 A[20:16] adat[31:0]
+ vdd 0 0 B[4:0] bdat[31:0]
+ 0 clk werf W[4:0] wdata[31:0]
+ $memory width=32 nlocations=31
XcatchA A[20:16] adat[31:0] adata[31:0] r31catch
XcatchB B[4:0] bdat[31:0] bdata[31:0] r31catch
.ends

* sign-extender
.subckt SEXT in[15:0] out[31:0]
Xlink in[14:0] out[14:0] wire
.connect out[31:15] in15     //buffer in15 for speed
.ends

* 32-bit mux, same syntax order as mux2
.subckt 32bitmux sel A[31:0] B[31:0] S[31:0]    //buffer sel for speed
Xmuxes sel#32 A[31:0] B[31:0] S[31:0] mux2
.ends

* 32-bit 4-way mux
.subckt 32bit4mux sel[1:0] three[31:0] two[31:0] one[31:0] zero[31:0] S[31:0]  //buffer sel
Xmuxes sel0#32 sel1#32 zero[31:0] one[31:0] two[31:0] three[31:0] S[31:0] mux4
.ends

* 1-bit adder, outputs inverted g and p, expects inverted c
.subckt adder a b c g p s
Xg a b g nand2
Xp a b p xnor2
Xs p c s xor2
.ends

* first level lookahead, expects inv, outputs non-inv (except sc0)
.subckt first g[0:1] p[0:1] c sg sp sc[0:1]
Xinv g0 c p[0:1] ng0 sc0 np[0:1] inverter
Xpout p0 p1 sp nor2
Xg0 ng0 np1 a nand2
Xg1 g1 a sg nand2
Xcout np0 c ng0 sc1 aoi21
.ends

* second level, non-inv. in, inv g and p out
.subckt second g[0:1] p[0:1] c sg sp sc[0:1]
Xinv g0 ng0 inverter
Xpout p0 p1 sp nand2
Xg1 g0 p1 g1 sg aoi21
.connect c sc0
Xcouttmp p0 c b nand2
Xcout b ng0 sc1 nand2
.ends

* last one
.subckt third g[0:1] p[0:1] ci sc[0:1] co
.connect ci sc0
Xinv g0 p[0:1] sg ng0 np[0:1] nsg inverter
Xtmp np0 ci b nand2
Xcout1 b g0 sc1 nand2
Xpout p0 p1 sp nor2
Xg0 ng0 np1 a nand2
Xg1 g1 a sg nand2
Xtmp2 sp ci c nand2
Xcout2 c nsg co nand2
.ends

* 8-bits
.subckt adder8 a[7:0] b[7:0] ci s[7:0] co
Xin a[7:0] b[7:0] c[7:0] g[7:0] p[7:0] s[7:0] adder
Xfour g0 g2 g4 g6 g1 g3 g5 g7 p0 p2 p4 p6 p1 p3 p5 p7 ca[0:3] ga[0:3] pa[0:3] c0 c2 c4 c6 c1 c3 c5 c7 first
Xtwo ga0 ga2 ga1 ga3 pa0 pa2 pa1 pa3 cb[0:1] gb[0:1] pb[0:1] ca0 ca2 ca1 ca3 second
Xlast gb[0:1] pb[0:1] ci cb[0:1] co third
.ends

* detects overflow: checks if sign bit differs from input
* (signs of two inputs must be same as well)
.subckt over a b s z
Xinva a na inverter
Xinvb b nb inverter
Xinvs s ns inverter
X1  a  b ns 1 nand3
X2  na nb s 2 nand3
Xout 1  2 z nand2
.ends

* 32-bit zero checker
.subckt zcheck s[31:0] z
Xza s[31:0] sa[15:0] nor2
Xzb sa[15:0] sb[7:0] nand2
Xzc sb[7:0] sc[3:0] nor2
Xzd sc[3:0] sd[1:0] nand2
Xze sd[1:0] z nor2
.ends

* adder, op0=0 for add, =1 for subtract
.subckt adder32 op0 A[31:0] B[31:0] S[31:0] z v n 
XBin B[31:0] op0#32 C[31:0] xor2
X1 a[7:0] c[7:0] op0 s[7:0] cone adder8
Xbuff cone ctwo cthree conea ctwoa cthreea inverter
Xbuff2 conea ctwoa cthreea coneb ctwob cthreeb inverter_2
Xground GND constant0
Xhigh HIGH constant1
X2s coneb#9 szero[15:8] ctwo0 sone[15:8] ctwo1 s[15:8] ctwo mux2
X20 a[15:8] c[15:8] GND szero[15:8] ctwo0 adder8
X21 a[15:8] c[15:8] HIGH sone[15:8] ctwo1 adder8
X3s ctwob#9 szero[23:16] cthree0 sone[23:16] cthree1 s[23:16] cthree mux2
X30 a[23:16] c[23:16] GND szero[23:16] cthree0 adder8
X31 a[23:16] c[23:16] HIGH sone[23:16] cthree1 adder8
X4s cthreeb#8 szero[31:24] sone[31:24] s[31:24] mux2
X40 a[31:24] c[31:24] GND szero[31:24] cfour0 adder8
X41 a[31:24] c[31:24] HIGH sone[31:24] cfour1 adder8
Xover A31 C31 S31 v over
Xza1 s[12:23] sa[5:10] nor2
Xza2 s[0:11] sa[1:4] nor3
Xzb1 sa[5:10] sb[2:3] nand3
Xzb2 sa[1:4] sb1 nand4
Xzc1 s[24:31] sc[2:5] nor2
Xzc2 sb[1:3] sc1 nor3
Xzd1 sc[4:5] sd2 nand2
Xzd2 sc[1:3] sd1 nand3
Xze  sd[1:2] z nor2
.connect n S31
.ends

   * 32-bit comparator

.subckt fastor2 a b z
Xa a 1 inverter
Xb b 2 inverter
Xz 1 2 z nand2
.ends

.subckt fastand2 a b z
Xa a 1 inverter
Xb b 2 inverter
Xz 1 2 z nor2
.ends

.subckt compare32 op2 op1 z v n cmp[31:0]
.connect 0 cmp[31:1]
X1 n v 1 xor2
X2 z 1 2 fastor2
Xctrl op1 op2 0 z 1 2 cmp0 mux4
.ends

   * 32-bit Boolean unit for Beta ALU, using 4-way multiplexors

.subckt ALUbool op[3:0] A[31:0] B[31:0] Z[31:0]
Xmx4 A[31:0] B[31:0] op0#32 op1#32 op2#32 op3#32 Z[31:0] mux4
.ends

   * 32-bit shifter unit for ALU

.subckt ALUshift A[31:0] op[1:0] B[4:0] S[31:0]
* left shift: cascade of many many muxes, bitwise by B
.connect 0 GND
XLfour B4#32 A[31:0] A[15:0] GND#16 W[31:0] mux2
XLthre B3#32 W[31:0] W[23:0] GND#8 X[31:0] mux2
XLtwo  B2#32 X[31:0] X[27:0] GND#4 Y[31:0] mux2
XLone  B1#32 Y[31:0] Y[29:0] GND#2 Z[31:0] mux2
XLdone B0#32 Z[31:0] Z[30:0] GND SL[31:0] mux2

*right shift: if op1=1 sign extend
Xsign op1 A31 f and2
XRfour B4#32 A[31:0] f#16 A[31:16] Q[31:0] mux2
XRthre B3#32 Q[31:0] f#8 Q[31:8] R[31:0] mux2
XRtwo  B2#32 R[31:0] f#4 R[31:4] L[31:0] mux2
XRone  B1#32 L[31:0] f#2 L[31:2] T[31:0] mux2
XRdone B0#32 T[31:0] f T[31:1] SR[31:0] mux2

*use op0 to choose, 0=left
Xmx2 op0#32 SL[31:0] SR[31:0] S[31:0] mux2
.ends

   * put it all together

.subckt alu op[5:0] A[31:0] B[31:0] alu[31:0]
Xbool op[3:0] A[31:0] B[31:0] Zb[31:0] ALUbool
Xshift A[31:0] op[1:0] B[4:0] Zs[31:0] ALUshift
Xadd op0 A[31:0] B[31:0] Za[31:0] z v n adder32
Xcmp op[2:1] z v n Zc[31:0] compare32
Xsel op5#32 op4#32 Za[31:0] Zs[31:0] Zb[31:0] Zc[31:0] alu[31:0] mux4
.ends

* PCcont->PCsel control box, for BEQ, BNE, and ILLOP
.subckt PCBEQBNE PCcont[1:0] z IRQ alufn5 PCsel[2:0]
Xonea alufn5 1 inverter
Xoneb 1 z 2 nand2
Xonec PCcont0 PCcont1 0 z 0 2 PCsel0 mux4
Xtwoa PCcont0 PCcont1 3 nand2
Xtwob 3 alufn5 PCcont1 PCsel1 mux2
Xinterr IRQ PCsel2 wire
.ends

* wdsel control logic for interrupts
.subckt wdintsel IRQ win wout
Xinv win 1 inverter
Xgate IRQ 1 wout nor2
.ends

* wasel control for exceptions and interrupts
.subckt wacont IR PCsel[1:0] wasel
Xone PCsel1 PCsel0 1 nand2
Xtwo IR 2 inverter
Xthree 1 2 wasel nand2
.ends  

* Actual circuits follow:

.subckt beta clk RESET IRQ ia[31:0] id[31:0] ma[31:0] moe mrd[31:0] wr mwd[31:0]
XPCcontrol PCcont[1:0] z IR alufn5 pcsel[2:0] PCBEQBNE
XPCselect1 pcsel[1:0] ILLOP[31:0] JThigh JT[30:0] ia31 broff[30:0] ia31 nextPC[30:0] PCtmp[31:0] 32bit4mux //PCsel
XPCselect2 RESET pcsel2 HIGH 0#31 HIGH 0#31 XAdr[31:0] PCtmp[31:0] PCin[31:0] 32bit4mux // more PC select
XPC clk PCin[31:0] ia[31:0] PCreg  //PC register  might save ~5ns replacing RESET mux w/ logic?
XPCadd ia[31:0] nextPC[31:0] PCadder  //PC adder
Xbroffset 0 nextPC[30:0] id15#15 id[14:0] 0#2 broff[31:0] sum32
Xra2select ra2sel#5 id[15:11] id[25:21] ra2mux[4:0] mux2
Xwaselect wasel#5 id[25:21] XP[4:0] wadata[4:0] mux2
Xreg32 id[20:16] radata[31:0] ra2mux[4:0] rbdata[31:0] clk werf wadata[4:0] wdata[31:0] regfile
Xraz radata[31:0] z zcheck        //checks if ra output = 0
Xaselect asel radata[31:0] broff[31:0] aluain[31:0] 32bitmux
Xlitextend id[15:0] litc[31:0] SEXT  //sign extends low 16 bits of instr.
XBselect bsel rbdata[31:0] litc[31:0] alubin[31:0] 32bitmux
Xaluelujah alufn[5:0] aluain[31:0] alubin[31:0] ma[31:0] alu
Xwdselect wdsel[1:0] ia31 nextPC[30:0] ia31 nextPC[30:0] ma[31:0] mrd[31:0] wdata[31:0] 32bit4mux
Xmemwrite rbdata[31:0] mwd[31:0] wire
Xwriteenable RESET xwr 0 0 vdd 0 wri mux4
Xuninterrupt ia31 IRQ 0 0 vdd 0 IR mux4


Xhigh HIGH constant1
Xill ILLOP[30:3] ILLOP[1:0] 0#30 wire
Xill32 ILLOP31 ILLOP2 HIGH#2 wire
Xirqad XAdr[30:4] XAdr[2:0] 0#30 wire
Xirqad32 XAdr31 XAdr3 HIGH#2 wire
Xsupstuff JT31 ia31 JThigh fastand2
XJTstuff JT[1:0] 0#2 wire
XJTmore radata[31:2] JT[31:2] wire
Xwaselmaker IR PCsel[1:0] wasel wacont   //exceptions
Xwriter werfi IR werf fastor2   //IRQ
Xwder IR wri wr wdintsel  //IRQ
Xwderr IR wdseli1 wdsel1 fastor2  //IRQ
Xxxpp XP[4:1] HIGH#4 wire  //XP=R30
Xxxpp5 XP0 0 wire


Xcontrol vdd 0 0 id[31:26]
+ alufn[5:0] werfi bsel wdseli1 wdsel0 xwr ra2sel moe asel PCcont[1:0]
+ $memory width=16 nlocations=64 contents=(
+ 0x82C3
+ 0x82C3
+ 0x82C3
+ 0x82C3
+ 0x82C3
+ 0x82C3
+ 0x82C3
+ 0x82C3
+ 0x82C3  // #8
+ 0x82C3
+ 0x82C3
+ 0x82C3
+ 0x82C3
+ 0x82C3
+ 0x82C3
+ 0x82C3
+ 0x82C3
+ 0x82C3
+ 0x82C3
+ 0x82C3
+ 0x82C3
+ 0x82C3
+ 0x82C3
+ 0x82C3
+ 0b0000001100001000        // opcode #24, LD
+ 0b0000000100110000	// #25, ST
+ 0x82C3			// #26
+ 0b0000001011000010	// #27, JMP
+ 0x82C3
+ 0b0000001011000001	// #29, BEQ
+ 0b0000001011000011	// #30, BNE
+ 0b0110101000001100	// #31, LDR
+ 0b0000001001000000	// #32, ADD
+ 0b0000011001000000	// #33, SUB
+ 0x82C3		// #34, MUL
+ 0x82C3		// #35, DIV
+ 0b1100111001000000	// #36, CMPEQ
+ 0b1101011001000000	// #37, CMPLT
+ 0b1111111001000000	// #38, CMPLE
+ 0x82C3		// #39
+ 0b0110001001000000	// #40 AND
+ 0b0111101001000000	// #41 OR
+ 0b0101101001000000	// #42 XOR
+ 0x82C3
+ 0b1000001001000000	// #44 SHL
+ 0b1000011001000000	// #45 SHR
+ 0b1000111001000000	// #46 SRA
+ 0x82C3
+ 0b0000001101000000	// #48 ADDC
+ 0b0000011101000000	// #49 SUBC
+ 0x82C3
+ 0x82C3
+ 0b1100111101000000	// #52 CMPEQC
+ 0b1101011101000000	// #53 CMPLTC
+ 0b1111111101000000	// #54 CMPLEC
+ 0x82C3
+ 0b0110001101000000	// #56 ANDC
+ 0b0111101101000000	// #57 ORC
+ 0b0101101101000000	// #58 XORC
+ 0x82C3
+ 0b1000001101000000	// #60 SHLC
+ 0b1000011101000000	// #61 SHRC
+ 0b1000111101000000	// #62 SRAC
+ 0x82C3)
.ends

Xbeta clk reset 0 ia[31:0] id[31:0] ma[31:0] moe mrd[31:0] wr mwd[31:0] beta

Xmem vdd 0 0 ia[11:2] id[31:0]
+ moe 0 0 ma[11:2] mrd[31:0]
+ 0 clk wr ma[11:2] mwd[31:0]
+ $memory width=32 nlocations=1024 contents=(
+ 0x77ff0002 0x77ffffff 0x77ffffff 0x7fa00006 0x779f0006 0x779f0029 0x779f008f 0x779f00a1
+ 0x679f03bc 0x77ffffff 0x3c0 0xc3bd0004 0x679dfffc 0xc01f7ff9 0xc03f0005 0x779f000a
+ 0x643f02d4 0x641f02d8 0xc01f7de3 0xc03f0025 0x779f0005 0x643f02dc 0x641f02e0 0x639dfffc
+ 0xc3bdfffc 0x6ffc0000 0xc05f0010 0xc07f0000 0xb0811000 0xc0bf0001 0xb0a51000 0xd4c00000
+ 0x7be60003 0x84002000 0x80632800 0x77ff0002 0x80002000 0x84632800 0xc4420001 0xd4c20000
+ 0x77e6fff3 0xd4c00000 0x77e60002 0x80010000 0xc4630001 0x8023f800 0x6ffc0000 0xc3bd0004
+ 0x679dfffc 0xc01f0338 0xc3bd0004 0x641dfffc 0x779f000c 0xc7bd0004 0xc3bd0004 0x641dfffc
+ 0xc01f0200 0xc3bd0004 0x641dfffc 0x779f001f 0xc7bd0008 0x641f02e4 0x639dfffc 0xc3bdfffc
+ 0x6ffc0000 0xc3bd0004 0x679dfffc 0xc3bd0004 0x677dfffc 0x837df800 0xc3bd0004 0x643dfffc
+ 0xc3bd0004 0x645dfffc 0xc01f0000 0x603bfff4 0x77e10005 0x60410004 0x64010004 0x8001f800
+ 0x8022f800 0x7be1fffb 0x605dfffc 0xc3bdfffc 0x603dfffc 0xc3bdfffc 0x637dfffc 0xc3bdfffc
+ 0x639dfffc 0xc3bdfffc 0x6ffc0000 0xc3bd0004 0x679dfffc 0xc3bd0004 0x677dfffc 0x837df800
+ 0xc3bd0004 0x643dfffc 0xc3bd0004 0x645dfffc 0xc3bd0004 0x647dfffc 0x601bfff4 0x603bfff0
+ 0x7be00001 0x77e1000a 0x77e10007 0x60400000 0x60610000 0x90421800 0x77e20003 0x60000004
+ 0x60210004 0x77fffff6 0xc01f0000 0x77ff0001 0xc01f0001 0x607dfffc 0xc3bdfffc 0x605dfffc
+ 0xc3bdfffc 0x603dfffc 0xc3bdfffc 0x637dfffc 0xc3bdfffc 0x639dfffc 0xc3bdfffc 0x6ffc0000
+ 0x1 0x248 0xa 0x250 0x3 0x238 0x9 0x208
+ 0x5 0x230 0x7 0x240 0x6 0x228 0x4 0x220
+ 0x8 0x218 0x2 0x210 0xb 0x0 0xc3bd0004 0x679dfffc
+ 0xc05f0002 0xc0ff0340 0x779f0000 0xc01f003c 0x80c7f800 0x603cfffc 0x64270000 0xc39c0004
+ 0xc0e70004 0xc4000004 0x7be0fffa 0xc4420001 0x77e20001 0x6fe60000 0x639dfffc 0xc3bdfffc
+ 0x6ffc0000 0xc01f0000 0xc03f0000 0xc05f0014 0xc0000001 0xc0210003 0x80000800 0x80200800
+ 0xc4420001 0x7be2fffa 0x80010000 0x641f03b8 0x6ffc0000 0xedededed 0xedededed 0xedededed
+ 0xedededed 0xedededed 0x1 0x0 0xa 0x300 0x3 0x330
+ 0x9 0x328 0x5 0x320 0x7 0x318 0x6 0x308
+ 0x4 0x2f8 0x8 0x310 0x2 0x2e8 0xb 0x2f0
+ 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
+ 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
+ 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
+ 0x0 0x0 0x0 0x0 0x0 0x0 0xedededed 0xedededed
+ )

Vclk clk 0 pulse(3.3,0,6.9ns,0.1ns,0.1ns,6.9ns)
Vreset reset 0 pwl(0ns 3.3v, 17ns 3.3v, 17.1ns 0v)
.tran 13104n
.plot ia[31:0]
.plot id[31:0]
.plot ma[31:0]
.plot mrd[31:0]
.plot mwd[31:0]