machine_conditions.figure.info 10/22/84 1044.5r w 09/17/80 0900.0 2970 Hello there! There is a figure on page 7-4 in AN87 that for some reason is no longer online. Originally it was sent to Waltham and reduced. WHen the book. is being revised or updated call Waltham first to see whether they still have the original, if not it will probably have to be out back on line. BYE Diane Barron 1/22/80.  s6.hsf.compin 10/22/84 1044.5r w 06/02/81 0900.2 176454 .ifi init_mpm "AN87-01" .srv section 6 .ifi l0h "Multics Environment" This section describes very broadly the environment in which Multics and the Multics user processes execute. The reader desiring more detail is .cbd referred to the entire set of Multics Program Logic Manuals (PLMs). .srv draft "MEMORY MAPS" .ifi l1h "Main Memory Maps" The following paragraphs describe the gross allocation of main memory during the three distinctly different Multics operational environments: BOS, bootstrap1, and service. .ifi l2h "BOS Environment" BOS operates in segmented, nonpaged appending mode with exactly eight defined segments. The eight pointer registers are loaded with fixed segment numbers and the segment base and bound values are manipulated according to the requirements of the code. .fif .cbn .inl 10 __________________________________________ 0 | | | Vectors and Mailboxes | |________________________________________| | | 7740 | descriptor segment | |________________________________________| 10000 | | | BOS Toehold | |________________________________________| 10700 | | | SETUP | |________________________________________| 20000 | | | 1024-Word Buffer (bf) | |________________________________________| 22000 | | | BOS Common Variable storage | |________________________________________| 27000 | | | Command Program | |________________________________________| 60000 | | | Multics memory--usually not used by BOS| .brf . .brf . .brf . .brf . .inl 0 .ifi fig "Main Memory Map for BOS" .cbf .ifi l2h "Bootstrap1 Environment" .fin The bootstrap1 program runs in fully segmented, unpaged appending mode. .spb 2 .inl 20 .fif __________________________________________ .unl 2 0 | | | Vectors and Mailboxes | |________________________________________| .unl 5 .cbn 1000 | | .cbf | BOS Toehold | |________________________________________| .unl 5 6000 | | | CONFIG deck | |________________________________________| .unl 6 .cbn 14000 | | .cbf | bootstrap1 | |________________________________________| .unl 6 14000 | | | Descriptor Segment | |________________________________________| .unl 6 16000 | | | Segment Loading Table | |________________________________________| .unl 6 22000 | | | Segment Name Table | |________________________________________| .unl 6 34000 | | | Physical Record Buffer | |________________________________________| .unl 6 42000 | | | Wired Hardcore Segments | _|_________________________________________| .brf . .brf . .brf . __________________________________________ | | | Paged, init, and temp segments | |________________________________________| End of memory .spb 2 .fin .inl 0 .ifi fig "Main Memory Map for Bootstrap1" .brp .ifi l2h "Service Environment" Multics service mode runs in fully segmented, fully paged appending mode. .spb 2 .inl 20 .fif __________________________________________ 0 | | | Vectors and Mailboxes | |________________________________________| 4000 | | | BOS Toehold | |________________________________________| 6000 | | | Free Store (Page Pool) | |________________________________________| 42000 | | | Wired Hardcore Segments | _|_________________________________________| .brf . .brf . .brf . .brf __________________________________________ | | | Free Storage (Page Pool) | |________________________________________| End of Memory .fin .inl 0 .spb 2 .ifi fig "Main Memory Map for Multics Service" .spf 2 .srv draft "INTERRUPT ASSIGNMENTS" .ifi l1h "Interrupt Assignments" .ifi tab "Interrupt Assignments" .spb 2 .inl 10 .fif F/I ADDR .brf D__e_c O__c_t _i_n_S_C_U___d_a_t_a A__s_s_i_g_n_m_e_n_t .spb .cbn 0 0 00 IOM #0 overhead (for channels > 37(8)) 1 1 02 IOM #1 overhead (for channels > 37(8)) 2 2 04 BSC #0 3 3 06 4 4 10 IOM #0 overhead (for channels <40(8)) 5 5 12 IOM #1 overhead (for channels <40(8)) 6 6 14 7 7 16 8 10 20 IOM #0 terminate (for channels > 37(8)) 9 11 22 IOM #1 terminate (for channels > 37(8)) 10 12 24 BSC #1 11 13 26 12 14 30 IOM #0 terminate (for channels < 40(8)) 13 15 32 IOM #1 terminate (for channels < 40(8)) 14 16 34 15 17 36 .brp 16 20 40 IOM #0 marker (for channels > 37(8)) 17 21 42 IOM #1 marker (for channels > 37(8)) 18 22 44 19 23 46 20 24 50 IOM #0 marker (for channels > 40(8)) 21 25 52 IOM #1 marker (for channels > 40(8)) 22 26 54 23 27 56 .spb 24 30 60 IOM #0 special (for channels > 37(8)) 25 31 62 IOM #1 special (for channels > 37(8)) 26 32 64 27 33 66 28 34 70 IOM #0 special (for channels < 40(8)) 29 35 72 IOM #1 special (for channels < 40(8)) 30 36 74 31 37 76 .inl 0 .srv draft "MACHINE CONDITIONS LAYOUT" .ifi l1h "Machine Conditions Data Layout" .inl 0 .fif 0 1 2 3 4 5 6 7 ___________________________________________________________________________ | | | | | 0 | PRO | PR1 | PR2 | PR3 | |_________________|___________________|__________________|_________________| | | | | | 10 | PR4 | PR5 | PR6 | PR7 | |_________________|___________________|__________________|_________________| | | | | | | | | | | |<(9)| | <(21)| (3)>| 20 |XO | X1 |X2 | X3 |X4 | X5 | X6 | X7 |A req| Q req| exp| | THR | RAR | |___|____ |___|_____|___|_____|_____|____|_____|______|____|__|______|_____| | |APUST| | IAL | | CPU#| SCT |TSNn| | | | | | | 30 |PPR|-----|FLT| IAC |TPR|-----|INDEX|ABC |ICT|IND|CA|CUST|CUR INST|ODD INST| | |FLTCT| |FLTCT| |DELTA| |TBIT| | | | | | | |___|_____|___|_____|___|_____|_____|____|___|___|__|____|________|________| | | | FAULT | | ||CPU |EXTEN|>54 | 40 | MEM CTLR MASK | IPS TEMP| HANDLER | FIM|FAULT ||TYPE| DED |TIME | | | | ERROR CODE |TIME|REGIS-||2 |FAULT| of | | | | | |TER || | 13 |FAULT| |___________________|_________|______________|____|______||____| REG |_____| | | | | | || |DPS8M| | |___________________|_________|______________|____|______||____|_____|_____| | | 50 | EIS POINTERS & LENGTHS DATA | |__________________________________________________________________________| .cbf .ifi fig "Machine Conditions Data Layout" .fin .srv draft "STACK LAYOUT" .inl 0 .spb S_T_A_C_K_S_ .spb .ifi l1toc "Stacks" .ifi l2h "Stack Header Layout" PL/I Declaration (stack_header.incl.pl1) .spb dcl 1 stack_header based (sb) aligned, 2 pad1 (4) fixed bin, 2 old_lot_ptr ptr, /* obsolete */ 2 pad2 (10) fixed bin, 2 null_ptr ptr, 2 stack_begin_ptr ptr, 2 stack_end_ptr ptr, 2 lot_ptr ptr, 2 signal_ptr ptr, 2 bar_mode_sp ptr, 2 pl1_operators_ptr ptr, 2 call_op_ptr ptr, .brp 2 push_op_ptr ptr, 2 return_op_ptr ptr, 2 return_no_pop_op_ptr ptr, 2 entry_op_ptr ptr, 2 trans_op_tv_ptr ptr, 2 isot_ptr ptr, 2 pad3 (2) fixed bin, 2 unwinder_ptr ptr, 2 stack_header_end fixed bin; .spb 2 .inl 5 + _________________________________________________________________ 0 | | | | | | | | | |_________|________| _ _ _ _ _ _ __|_ _ _ _ _ _ __|________|________|________|________| 10 | | | | | | | | | _|________|________|________|________|________|________|________|________| 20 | null ptr | stack begin | stack end ptr | lot ptr | _|________________|__p_t_r____________|________________|________________| 30 | signal ptr | process info | pl1_operators_| call op ptr | _|________________|__p_t_r____________|__p_t_r____________|________________| 40 | push op ptr | return op ptr | short return | entry op ptr | _|________________|________________|__o_p__p_t_r_________|________________| 50 | trans_op_tv | isot_ptr | | | unwinder ptr | _|________________|________________|________|________|________________| 60 | | | | .brf . .brf . .brf . .brf . .spb .inl 0 .ifi fig "Stack Header Layout" .brf .ifi l2h "Stack Frame Layout" PL/I Declaration (stack_frame.incl.pl1) .fif .spb 2 dcl 1 stack_frame based(sp) aligned, 2 pointer_registers(0 : 7) ptr, 2 prev_sp ptr, 2 next_sp ptr, 2 return_ptr ptr, 2 entry_ptr ptr, 2 operator_and_lp_ptr ptr, 2 arg_ptr ptr, 2 static_ptr ptr unaligned, 2 reserved bit(36), 2 on_unit_relp1 bit(18) unaligned, 2 on_unit_relp2 bit(18) unaligned, 2 translator_id bit(18) unaligned, 2 operator_return_offset bit(18) unaligned; .brp .inl 5 + _________________________________________________________________ 0 | Storage for pointer registers 0 through 3 | _|________________________________________________________________| 10 | Storage for pointer registers 4 through 7 | _|________________________________________________________________| 20 | previous stack| next stack | return ptr | entry ptr | _|__f_r_a_m_e__p_t_r______|__f_r_a_m_e__p_t_r______|________________|________________| 30 | operator/link | argument ptr |static|RESERVED|on_unit_|_t_r_a_n_s_i_d_| _|__p_t_r____________|________________|__p_t_r___|_________|________|_r_e_t_u_r_n__| 40 | | | | .brf . .brf . .brf . .brf .inl 0 .spf 2 .ifi fig "Stack Frame Layout" .spf C_A_L_L_S_ .ifi l1toc "Calls" .spf .fin .srv draft "ARG LIST/DESCRIPTOR FORM" .ifi l2h "Argument List Layout" An argument list must begin on an even word boundary. It normally resides in the caller's stack frame. The pointers in the argument list need not be ITS pairs; however, they must be indirect words. Packed pointers cannot be used. The _ith argument pointer points to the _ith argument and the _ith descriptor pointer points to the _ith descriptor. Descriptors are not always present, but if they are, there is one for each argument. .spf 2 PL/I Declaration (arg_list.incl.pl1) .spf 2 dcl 1 arg_list aligned based, 2 arg_count fixed bin(17) unsigned unal, 2 pad1 bit(1) unal, 2 call_type fixed bin(18) unsigned unal, 2 desc_count fixed bin(17) unsigned unal, 2 pad2 bit(19) unal, 2 arg_ptrs (arg_list_arg_count) ptr, 2 desc_ptrs (arg_list_arg_count) ptr; .spf 2 dcl 1 arg_list_with_envptr aligned based, 2 arg_count fixed bin(17) unsigned unal, 2 pad1 bit(1) unal, 2 call_type fixed bin(18) unsigned unal, 2 desc_count fixed bin(17) unsigned unal, 2 pad2 bit(19) unal, 2 arg_ptrs (arg_list_arg_count) ptr, 2 envptr ptr, 2 desc_ptrs (arg_list_arg_count) ptr; .spf 2 .brp .inl 0 The argument list structures are explained more fully in the MPM Subsystem Writers' Guide, Order!No. AK92. Briefly, call_type tells what kind of call is being made. The following values are defined: 0, for a quick (intra-segment) call; 4, for a non-quick call; 8, for a call made through an entry variable. In this last case, an environment pointer is also passed, and the second form of arg list is the one used. .spf 2 .inl 12 .fif 0 16 17 18 35 ------------------------- 0 | n_args | | code | ------------------------- 1 | n_desc | | | ------------------------- 2 | arg 1 pointer | ------------------------- 4 | arg 2 ptr | ------------------------- .brf .bbl . . . .bel ------------------------- 2n | arg n pointer | ------------------------- 2n+2 | desc 1 pointer | ------------------------- 2n+4 | desc 2 pointer | ------------------------- .brf .bbl . . . .bel ------------------------- 2n+2m | desc m pointer | ------------------------- .fin .ifi fig "Argument List Layout For Call Without Environment Pointer" .inl 0 .ifi l2h "Argument Descriptor" An argument descriptor is pointed to by a descriptor pointer in an argument list. (For a full discussion of descriptors, refer to the MPM Subsystem Writers' Guide, Order!No.!AK92.) Its format is given by the following structure: .spf PL/I Declaration (arg_descriptor.incl.pl1) .spf .fif dcl 1 arg_descriptor based aligned, 2 flag bit(1) unal, 2 type fixed bin(6) unsigned unal, 2 packed bit(1) unal, 2 number_dims fixed bin(4) unsigned unal, 2 size fixed bin(24) unsigned unal; .spf dcl 1 fixed_arg_descriptor based aligned, 2 flag bit(1) unal, 2 type fixed bin(6) unsigned unal, 2 packed bit(1) unal, 2 number_dims fixed bin(4) unsigned unal, 2 scale fixed bin(11) unal, 2 precision fixed bin(12) unsigned unal; .spf 2 .inl 10 0 0 0 0 0 1 1 3 0 1 6 7 8 1 2 5 ------------------------------------------------------ | | | | | | |1| TYPE |P| ND | SIZE | | | | | | | ----------------------------------------------------- 1 6 1 4 24 .fin .ifi fig "Argument Descriptor Format" .spf .inl 10 .unl 10 Legend: .spf .unl 10 TYPE (arg_descriptor.type) descriptor type for data being described. Refer to the MPM Subsystem Writers' Guide, Order!No.AK92 for a complete list of descriptor types. .spf .unl 10 P (arg_descriptor.packed) .brf 0 = unpacked. .brf 1 = packed. .spf .unl 10 ND (arg_descriptor.number_dims) number of dimensions if item is an array. .spf .unl 10 SIZE (arg_descriptor.size) length of string data, or number of members for structure data. .spf 2 .inl 10 .fif 0 0 0 0 0 1 1 2 2 3 0 1 6 7 8 1 2 3 4 5 ------------------------------------------------------- | | | | | | | |1| TYPE |P| ND | SCALE | PREC | | | | | | | | ------------------------------------------------------- 1 6 1 4 12 12 .spf 2 .ifi fig "Fixed Point Argument Descriptor" .fin .spf 2 .inl 10 .unl 10 Legend: see legend for Argument Descriptor Format .spf .unl 10 SCALE (fixed_arg_descriptor.scale) arithmetic scale factor of data. .spf .unl 10 PREC (fixed_arg_descriptor.precision) precision of data. .fif .brp .inl 0 .trf !! .fif .srv draft "ASCII CHARACTERS" .brf .ifi tab "ASCII Character Chart" .spf 2 .inl 10 ___0______1______2______3______4______5______6______7____ 000 | NUL | SOH | STX | ETX | EOT | ENQ | ACK | BEL | 010 | BS | HT | NL | VT | NP | CR | S0 | SI | 020 | DLE | DC1 | DC2 | DC3 | DC4 | NAK | SYN | ETB | 030 | C A N | E M | S U B | E S C | F S | G S | R S | U S | 040 | | ! | " | # | $ | % | & | ' | 050 | ( | ) | * | + | , | - | . | / | 060 | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 070 | 8 | 9 | : | ; | < | = | > | ? | 100 | @ | A | B | C | D | E | F | G | 110 | H | I | J | K | L | M | N | O | 120 | P | Q | R | S | T | U | V | W | 130 | X | Y | Z | [ | \ | ] | ^ | _ | 140 | ` | a | b | c | d | e | f | g | 150 | h | i | j | k | l | m | n | o | 160 | p | q | r | s | t | u | v | w | 170 _|___x___|___y___|___z___|___{___|___|___|___}___|___~___|_P_A_D___| .brp .inl 0 .fin  tp.hsf.compin 10/22/84 1044.5r w 10/22/84 1042.2 12726 ..init_mpm"" .tlh 1 |||SERIES 60 (LEVEL 68)| .tlh 2 |||MULTICS HARDWARE AND| .tlh 3 |||SOFTWARE FORMATS| .tlh 4 |||PROGRAM LOGIC MANUAL| .trf ! .spb 8 .inl 5 .unl 5 SUBJECT: .spb Changes and additions to the Multics Hardware and Software Formats .spb 2 .unl 5 SPECIAL INSTRUCTIONS: .spb This Program Logic Manual (PLM) describes certain internal modules constituting the Multics System. It is intended as a reference for only those who are thoroughly familiar with the implementation details of the Multics operating system; interfaces described herein should not be used by application programmers or subsystem writers; such programmers and writers are concerned with the external interfaces only. The external interfaces are described in the M__u_l_t_i_c_s P__r_o_g_r_a_m_mm_e_r_s'_ M__a_n_u_a_l, C__o_m_m_a_n_d_s _a_n_d A__c_t_i_v_e F__u_n_c_t_i_o_n_s (Order No. AG92), S__u_b_r_o_u_t_i_n_e_s (Order No. AG93), and S__u_b_s_y_s_t_e_m W__r_i_t_e_r_s'__ G__u_i_d_e (Order No. AK92). .spb 2 As Multics evolves, Honeywell will add, delete, and modify module descriptions in subsequent PLM updates. Honeywell does not ensure that the internal functions and internal module interfaces will remain compatible with previous versions. .spb 2 .inl 5 .unl 5 DATE: .spb September 1981 .spb 2 .unl 5 ORDER NUMBER: .spb AN87-01 .brp  s1.hsf.compin 10/22/84 1044.6r w 05/14/81 0842.1 1559538 .ifi init_mpm "AN87-01" .srv section 1 .cbn .ifi l0h "Multics Processors" .cbf .srv draft "PROCESSOR INSTRUCTIONS" .srv draft_date "" This section describes the registers and register data formats (as seen in an octal store dump) of the program-accessible registers of the .cbn Level 68 and DPS 8M .cbf Processors. Only very brief discussions of the roles of the various features in the operation of the Processor are given. See M__u_l_t_i_c_s P__r_o_c_e_s_s_o_r R__e_f_e_r_e_n_c_e M__a_n_u_a_l, Order No. AL39 for a complete description of the Processor operation. .ifi l1h "Control Unit and Operations Unit Formats" The control unit (CU) is that portion of the processor hardware that decodes instruction opcodes, loads and unloads registers, responds to internal and external hardware signals, and interfaces with the main store. The operations unit (OU) is that portion of the processor hardware that executes the binary word mode or basic instructions. .ifi l2h "Processor Instructions" The basic instruction word format is shown below in Figure 1-1. The PL/I declaration (and the name of the include file) is given below. The following pages contain the instruction opcode charts (Tables 1-1 and 1-2) and an alphabetic list of the processor instructions (Table 1-3). .fif .spb PL/I Declaration (db_inst.incl.pl1) .spb dcl 1 instr based (ilc_ptr) aligned, (2 offset fixed bin (17), 2 opcode bit(10), 2 inhibit bit(1), 2 pr_bit bit(1), 2 tag bit(6)) unaligned; .spf dcl 1 instr_pr based (ilc_ptr) aligned, (2 pr bit(3), 2 offset fixed bin (14), 2 pad bit(18)) unaligned; .spb .fif .inl 3 0 1 1 2 2 2 3 3 _0__________________________________7__8__________________7__8__9__0__________5__ | | | | | | | ADDRESS | OPCODE |I|P| TAG | _|____________________________________|____________________|__|__|____________| 18 10 1 1 6 .fin .inl 0 .ifi fig "Basic Instruction Word Format" .spb Legend: .spb 1 .inl 10 .unl 10 ADDRESS For!P=0; 18-bit procedure segment address. .brf For!P=1; 3-bit pointer register number and 15-bit signed word offset. .spb .unl 10 OPCODE Instruction operation code. .spb .unl 10 I Interrupt inhibit bit. .spb .unl 10 P Pointer register flag. .spb .unl 10 TAG Instruction address modifier. .inl 0 .ifi l2h "Explanation of Opcode Notation" The opcode field of the instruction is 10 bits long (bits 18-27). The normal notation is to express the first nine bits (bits 18-26) in octal followed by either "(1)" or "(0)" for the tenth bit (bit 27). For!example, lda is expressed as 235(0), which is 0100111010 in the opcode field, and mlr is expressed as 100(1), which is 0010000001. The two opcode charts on the following pages divide the instruction set into two groups: those with bit 27 equal to 0 and those with bit 27 equal to 1. .brp .ifi tab "Instruction Opcode Chart, Bit 27 = 0" .fla 2 |* These instructions are not present on the DPS 8M.||| .fif ___0_0_0______0_0_1______0_0_2______0_0_3______0_0_4______0_0_5______0_0_6______0_0_7____ 000 | | mme1 | drl | | mme2 | mme3 | | mme4 | 010 | | nop | puls1 | puls2 | | cioc | | | 020 | adlx0 | adlx1 | adlx2 | adlx3 | adlx4 | adlx5 | adlx6 | adlx7 | 030 _|________|________|__l_d_q_c___|__a_d_l____|__l_d_a_c___|__a_d_l_a___|__a_d_l_q___|__a_d_l_a_q__| 040 | asx0 | asx1 | asx2 | asx3 | asx4 | asx5 | asx6 | asx7 | 050 | adwp0 | adwp1 | adwp2 | adwp3 | aos | asa | asq | sscr | 060 | adx0 | adx1 | adx2 | adx3 | adx4 | adx5 | adx6 | adx7 | 070 _|________|__a_w_c_a___|__a_w_c_q___|__l_r_e_g___|________|__a_d_a____|__a_d_q____|__a_d_a_q___| 100 | cmpx0 | cmpx1 | cmpx2 | cmpx3 | cmpx4 | cmpx5 | cmpx6 | cmpx7 | 110 | | cwl | | | | cmpa | cmpq | cmpaq | 120 | sblx0 | sblx1 | sblx2 | sblx3 | sblx4 | sblx5 | sblx6 | sblx7 | 130 _|________|________|________|________|________|__s_b_l_a___|__s_b_l_q___|__s_b_l_a_q__| 140 | ssx0 | ssx1 | ssx2 | ssx3 | ssx4 | ssx5 | ssx6 | ssx7 | 150 | adwp4 | adwp5 | adwp6 | adwp7 | sdbr | ssa | ssq | | 160 | sbx0 | sbx1 | sbx2 | sbx3 | sbx4 | sbx5 | sbx6 | sbx7 | 170 _|________|__s_w_c_a___|__s_w_c_q___|__l_p_r_i___|________|__s_b_a____|__s_b_q____|__s_b_a_q___| 200 | cnax0 | cnax1 | cnax2 | cnax3 | cnax4 | cnax5 | cnax6 | cnax7 | 210 | | cmk | absa | epaq | sznc | cnaa | cnaq | cnaaq | 220 | ldx0 | ldx1 | ldx2 | ldx3 | ldx4 | ldx5 | ldx6 | ldx7 | 230 _|__l_b_a_r___|__r_s_w____|__l_d_b_r___|__r_m_c_m___|__s_z_n____|__l_d_a____|__l_d_q____|__l_d_a_q___| 240 | orsx0 | orsx1 | orsx2 | orsx3 | orsx4 | orsx5 | orsx6 | orsx7 | .cbn 250 | spri0 | spbp1 | spri2 | spbp3 | spri | orsa | orsq | lsdp* | .cbf 260 | orx0 | orx1 | orx2 | orx3 | orx4 | orx5 | orx6 | orx7 | 270 _|__t_s_p0____|__t_s_p1____|__t_s_p2____|__t_s_p3____|________|__o_r_a____|__o_r_q____|__o_r_a_q___| 300 | canx0 | canx1 | canx2 | canx3 | canx4 | canx5 | canx6 | canx7 | 310 | eawp0 | easp0 | eawp2 | easp2 | | cana | canq | canaq | 320 | lcx0 | lcx1 | lcx2 | lcx3 | lcx4 | lcx5 | lcx6 | lcx7 | 330 _|__e_a_w_p4___|__e_a_s_p4___|__e_a_w_p6___|__e_a_s_p6___|________|__l_c_a____|__l_c_q____|__l_c_a_q___| 340 | ansx0 | ansx1 | ansx2 | ansx3 | ansx4 | ansx5 | ansx6 | ansx7 | 350 | epp0 | epbp1 | epp2 | epbp3 | stac | ansa | ansq | stcd | 360 | anx0 | anx1 | anx2 | anx3 | anx4 | anx5 | anx6 | anx7 | 370 _|__e_p_p4____|__e_p_b_p5___|__e_p_p6____|__e_p_b_p7___|________|__a_n_a____|__a_n_q____|__a_n_a_q___| 400 | | mpf | mpy | | | cmg | | | 410 | | lde | | rscr | | ade | | | 420 | | ufm | | dufm | | fcmg | | dfcmg | 430 _|__f_s_z_n___|__f_l_d____|________|__d_f_l_d___|________|__u_f_a____|________|__d_u_f_a___| 440 | sxl0 | sxl1 | sxl2 | sxl3 | sxl4 | sxl5 | sxl6 | sxl7 | 450 | stz | smic | scpr | | stt | fst | ste | dfst | 460 | | fmp | | dfmp | | | | | 470 _|__f_s_t_r___|__f_r_d____|__d_f_s_t_r__|__d_f_r_d___|________|__f_a_d____|________|__d_f_a_d___| 500 | rpl | | | | | bcd | div | dvf | 510 | | | | fneg | | fcmp | | dfcmp | 520 | rpt | | | | | fdi | | dfdi | 530 _|________|__n_e_g____|__c_a_m_s___|__n_e_g_l___|________|__u_f_s____|________|__d_u_f_s___| 540 | sprp0 | sprp1 | sprp2 | sprp3 | sprp4 | sprp5 | sprp6 | sprp7 | 550 | sbar | stba | stbq | smcm | stc1 | | | ssdp | 560 | rpd | | | | | fdv | | dfdv | 570 _|________|________|________|__f_n_o____|________|__f_s_b____|________|__d_f_s_b___| 600 | tze | tnz | tnc | trc | tmi | tpl | | ttf | 610 | rtcd | | | rcu | teo | teu | dis | tov | 620 | eax0 | eax1 | eax2 | eax3 | eax4 | eax5 | eax6 | eax7 | 630 _|__r_e_t____|________|________|__r_c_c_l___|__l_d_i____|__e_a_a____|__e_a_q____|__l_d_t____| 640 | ersx0 | ersx1 | ersx2 | ersx3 | ersx4 | ersx5 | ersx6 | ersx7 | 650 | spri4 | spbp5 | spri6 | spbp7 | stacq | ersa | ersq | scu | 660 | erx0 | erx1 | erx2 | erx3 | erx4 | erx5 | erx6 | erx7 | 670 _|__t_s_p4____|__t_s_p5____|__t_s_p6____|__t_s_p7____|__l_c_p_r___|__e_r_a____|__e_r_q____|__e_r_a_q___| 700 | tsx0 | tsx1 | tsx2 | tsx3 | tsx4 | tsx5 | tsx6 | tsx7 | 710 | tra | | | call6 | | tss | xec | xed | 720 | lxl0 | lxl1 | lxl2 | lxl3 | lxl4 | lxl5 | lxl6 | lxl7 | 730 _|________|__a_r_s____|__q_r_s____|__l_r_s____|________|__a_l_s____|__q_l_s____|__l_l_s____| 740 | stx0 | stx1 | stx2 | stx3 | stx4 | stx5 | stx6 | stx7 | 750 | stc2 | stca | stcq | sreg | sti | sta | stq | staq | 760 | lprp0 | lprp1 | lprp2 | lprp3 | lprp4 | lprp5 | lprp6 | lprp7 | 770 _|________|__a_r_l____|__q_r_l____|__l_r_l____|__g_t_b____|__a_l_r____|__q_l_r____|__l_l_r____| .brp .ifi tab "Instruction Opcode Chart, Bit 27 = 1" .fla 2 |* These instructions are not present on the DPS 8M.||| ___0_0_0______0_0_1______0_0_2______0_0_3______0_0_4______0_0_5______0_0_6______0_0_7____ 000 | | | | | | | | | 010 | | | | | | | | | 020 | mve | | | | mvne | | | | 030 _|________|________|________|________|________|________|________|________| 040 | | | | | | | | | 050 | | | | | | | | | 060 | csl | csr | | | sztl | sztr | cmpb | | 070 _|________|________|________|________|________|________|________|________| 100 | mlr | mrl | | | | | cmpc | | 110 | | | | | | | | | 120 | scd | scdr | | | scm | scmr | | | 130 _|________|________|________|________|________|________|________|________| 140 | | | | | | | | | 150 | | | | | sptr | | | | 160 | mvt | | | | tct | tctr | | | .cbn 170 _|________|________|________|__l_p_t_r_*__|________|________|________|________| .cbf 200 | | | ad2d | sb2d | | | mp2d | dv2d | 210 | | | | | | | | | 220 | | | ad3d | sb3d | | | mp3d | dv3d | .cbn 230 _|________|________|__l_s_d_r_*_|________|________|________|________|________| .cbf 240 | | | | | | | | | .cbn 250 | spbp0 | spri1 | spbp2 | spri3 | ssdr | | | lptp* | .cbf 260 | | | | | | | | | 270 _|________|________|________|________|________|________|________|________| 300 | mvn | btd | | cmpn | | dtb | | | 310 | easp1 | eawp1 | easp3 | eawp3 | | | | | 320 | | | | | | | | | 330 _|__e_a_s_p5___|__e_a_w_p5___|__e_a_s_p7___|__e_a_w_p7___|________|________|________|________| 340 | | | | | | | | | 350 | epbp0 | epp1 | epbp2 | epp3 | | | | | 360 | | | | | | | | | 370 _|__e_p_b_p4___|__e_p_p5____|__e_p_b_p6___|__e_p_p7____|________|________|________|________| 400 | | | | | | | | | 410 | | | | | | | | | 420 | | | | | | | | | 430 _|________|________|________|________|________|________|________|________| 440 | | | | sareg | | | | spl | 450 | | | | | | | | | 460 | | | | lareg | | | | lpl | 470 _|________|________|________|________|________|________|________|________| 500 | a9bd | a6bd | a4bd | abd | | | | awd | 510 | | | | | | | | | 520 | s9bd | s6bd | s4bd | sbd | | | | swd | 530 _|________|________|__c_a_m_p___|________|________|________|________|________| 540 | ara0 | ara1 | ara2 | ara3 | ara4 | ara5 | ara6 | ara7 | 550 | | | | | | | | sptp | 560 | aar0 | aar1 | aar2 | aar3 | aar4 | aar5 | aar6 | aar7 | 570 _|________|________|________|________|________|________|________|________| 600 | trtn | trtf | | | tmoz | tpnz | ttn | | 610 | | | | | | | | | 620 | | | | | | | | | 630 _|________|________|________|________|________|________|________|________| 640 | arn0 | arn1 | arn2 | arn3 | arn4 | arn5 | arn6 | arn7 | 650 | spbp4 | spri5 | spbp6 | spri7 | | | | | 660 | nar0 | nar1 | nar2 | nar3 | nar4 | nar5 | nar6 | nar7 | 670 _|________|________|________|________|________|________|________|________| 700 | | | | | | | | | 710 | | | | | | | | | 720 | | | | | | | | | 730 _|________|________|________|________|________|________|________|________| 740 | sar0 | sar1 | sar2 | sar3 | sar4 | sar5 | sar6 | sar7 | 750 | | | | | sra | | | | 760 | lar0 | lar1 | lar2 | lar3 | lar4 | lar5 | lar6 | lar7 | 770 _|________|________|________|________|__l_r_a____|________|________|________| .brp .ifi tab "Alphabetic Listing of Processor Instructions" .fla 2 .inl 2 .unl 2 M__n_e_m_o_n_i_c C__o_d_e M__e_a_n_i_n_g .spb a4bd 502(1) Add 4-bit character displacement to AR a6bd 501(1) Add 6-bit character displacement to AR a9bd 500(1) Add 9-bit character displacement to AR aarN_ 56N_(1) Alphanumeric descriptor to ARN_ abd 503(1) Add bit displacement to AR .spb absa 212(0) Absolute address to A register ad2d 202(1) Add using two decimal operands ad3d 222(1) Add using three decimal operands ada 075(0) Add to A register adaq 077(0) Add to AQ register .spb ade 415(0) Add to E register adl 033(0) Add low to AQ register adla 035(0) Add logical to A register adlaq 037(0) Add logical to AQ register adlq 036(0) Add logical to Q register .spb adlxN_ 02N_(0) Add logical to index N_ adq 076(0) Add to Q register adwp0 050(0) Add to word number field of PR0 adwp1 051(0) Add to word number field of PR1 adwp2 052(0) Add to word number field of PR2 .spb adwp3 053(0) Add to word number field of PR3 adwp4 150(0) Add to word number field of PR4 adwp5 151(0) Add to word number field of PR5 adwp6 152(0) Add to word number field of PR6 adwp7 153(0) Add to word number field of PR7 .spb adxN_ 06N_(0) Add to index N_ alr 775(0) A register left rotate als 735(0) A register left shift ana 375(0) AND to A register anaq 377(0) AND to AQ register .spb anq 376(0) AND to Q register ansa 355(0) AND to storage from A register ansq 356(0) AND to storage from Q register ansxN_ 34N_(0) AND to storage from index N_ anxN_ 36N_(0) AND to index N_ .spb aos 054(0) Add one to storage araN_ 54N_(1) ARN_ to alphanumeric descriptor arl 771(0) A register right logical shift arnN_ 64N_(1) ARN_ to numeric descriptor ars 731(0) A register right shift .spb asa 055(0) Add stored to A register asq 056(0) Add stored to Q register asxN_ 04N_(0) Add stored to index N_ awca 071(0) Add with carry to A register awcq 072(0) Add with carry to Q register .spb awd 507(1) Add word displacement to AR bcd 505(0) Binary-to-BCD btd 301(1) Binary-to-Decimal call6 713(0) Call camp 532(1) Clear associative memory paged cams 532(0) Clear associative memory segmented cana 315(0) Comparative AND with A register .brp .alc Table 1-3 (cont) Alphabetic Listing of Processor Instructions .spb .alb M__n_e_m_o_n_i_c C__o_d_e M__e_a_n_i_n_g canaq 317(0) Comparative AND with AQ register canq 316(0) Comparative AND with Q register canxN_ 30N_(0) Comparative AND with index N_ .spb cioc 015(0) Connect cmg 405(0) Compare magnitude cmk 211(0) Compare masked cmpa 115(0) Compare with A register cmpaq 117(0) Compare with AQ register .spb cmpb 066(1) Compare bit strings cmpc 106(1) Compare alphanumeric character strings cmpn 303(1) Compare numeric cmpq 116(0) Compare with Q register cmpxN_ 10N_(0) Compare with index N_ .spb cnaa 215(0) Comparative NOT with A register cnaaq 217(0) Comparative NOT with AQ register cnaq 216(0) Comparative NOT with Q register cnaxN_ 20N_(0) Comparative NOT with index N_ cwl 111(0) Compare with limits .spb csl 060(1) Combine bit strings left csr 061(1) Combine bit strings right dfad 477(0) DP floating add dfcmg 427(0) DP floating compare magnitude dfcmp 517(0) DP floating compare .spb dfdi 527(0) DP floating divide inverted dfdv 567(0) DP floating divide dfld 433(0) DP floating load dfmp 463(0) DP floating multiply dfrd 473(0) DP floating round .spb dfsb 577(0) DP floating subtract dfst 457(0) DP floating store dfstr 472(0) DP floating store rounded dis 616(0) Delay until interrupt signal div 506(0) Divide integer .spb drl 002(0) Derail dtb 305(1) Decimal-to-binary convert dufa 437(0) DP unnormalized floating add dufm 423(0) DP unnormalized floating multiply dufs 537(0) DP unnormalized floating subtract .spb dv2d 207(1) Divide using two decimal operands dv3d 227(1) Divide using three decimal operands dvf 507(0) Divide fraction eaa 635(0) Effective address to A register eaq 636(0) Effective address to Q register .spb easp0 311(0) Effective address to segment number field of PR0 easp1 310(1) Effective address to segment number field of PR1 easp2 313(0) Effective address to segment number field of PR2 easp3 312(1) Effective address to segment number field of PR3 easp4 331(0) Effective address to segment number field of PR4 .spb easp5 330(1) Effective address to segment number field of PR5 easp6 333(0) Effective address to segment number field of PR6 easp7 332(1) Effective address to segment number field of PR7 eawp0 310(0) Effective address to word and bit fields of PR0 eawp1 311(1) Effective address to word and bit fields of PR1 .brp .alc Table 1-3 (cont) Alphabetic Listing of Processor Instructions .spb .alb M__n_e_m_o_n_i_c C__o_d_e M__e_a_n_i_n_g eawp2 312(0) Effective address to word and bit fields of PR2 eawp3 313(1) Effective address to word and bit fields of PR3 eawp4 330(0) Effective address to word and bit fields of PR4 eawp5 331(1) Effective address to word and bit fields of PR5 eawp6 332(0) Effective address to word and bit fields of PR6 .spb eawp7 333(1) Effective address to word number field of PR7 eaxN_ 62N_(0) Effective address to index N_ epaq 213(0) Effective pointer to AQ register epbp0 350(1) Effective pointer at base to PR0 epbp1 351(0) Effective pointer at base to PR1 .spb epbp2 352(1) Effective pointer at base to PR2 epbp3 353(0) Effective pointer at base to PR3 epbp4 370(1) Effective pointer at base to PR4 epbp5 371(0) Effective pointer at base to PR5 epbp6 372(1) Effective pointer at base to PR6 .spb epbp7 373(0) Effective pointer at base to PR7 epp0 350(0) Effective pointer to PR0 epp1 351(1) Effective pointer to PR1 epp2 352(0) Effective pointer to PR2 epp3 353(1) Effective pointer to PR3 .spb epp4 370(0) Effective pointer to PR4 epp5 371(1) Effective pointer to PR5 epp6 372(0) Effective pointer to PR6 epp7 373(1) Effective pointer to PR7 era 675(0) Exclusive OR to A register .spb ersq 677(0) Exclusive OR to AQ register erq 676(0) Exclusive OR to Q register ersa 655(0) Exclusive OR to storage with A register ersq 656(0) Exclusive OR to storage with Q register ersxN_ 64N_(0) Exclusive OR to storage with index _N .spb erxN_ 66N_(0) Exclusive OR to index N_ fad 475(0) Floating add fcmg 425(0) Floating compare magnitude fcmp 515(0) Floating compare fdi 525(0) Floating divide inverted .spb fdv 565(0) Floating divide fld 431(0) Floating load fmp 461(0) Floating multiply fneg 513(0) Floating negate fno 573(0) Floating normalize .spb frd 471(0) Floating round fsb 575(0) Floating subtract fst 455(0) Floating store fstr 470(0) Floating store rounded fszn 430(0) Floating set zero and negative indicators .spb gtb 774(0) Gray-to-binary convert larN_ 76N_N(1) Load ARN_ lareg 463(1) Load address registers lbar 230(0) Load base address register lca 335(0) Load complement into A register .spb lcaq 337(0) Load complement into AQ register lcpr 674(0) Load central processor register lcq 336(0) Load complement into Q register lcxN_ 32N_(0) Load complement into index N_ lda 235(0) Load A register .brp .alc Table 1-3 (cont) Alphabetic Listing of Processor Instructions .fla 2 |* These instructions are not present on the DPS 8M.||| .spb .alb M__n_e_m_o_n_i_c C__o_d_e M__e_a_n_i_n_g ldac 034(0) Load A register and clear ldaq 237(0) Load AQ register ldbr 232(0) Load descriptor base register lde 411(0) Load E register ldi 634(0) Load indicator register .spb ldq 236(0) Load Q register ldqc 032(0) Load Q register and clear ldt 637(0) Load timer register ldxN_ 22N_(0) Load index N_ llr 777(0) Long left rotate .spb lls 737(0) Long left shift lpl 467(1) Load pointers and lengths lpri 173(0) Load pointer registers from ITS pairs lprpN_ 76N_(0) Load pointer register N_ from packed pointer .cbn lptp* 257(1) Load page table pointers .spf lptr* 173(1) Load page table registers .cbf lra 774(1) Load ring alarm register lreg 073(0) Load registers lrl 773(0) Long right logical lrs 733(0) Long right shift .spb .cbn lsdp* 257(0) Load segment descriptor pointers lsdr* 232(1) Load segment descriptor registers .cbf lxlN_ 72N_(0) Load index N_ from lower mlr 100(1) Move alphanumeric left to right mme1 001(0) Master mode entry 1 .spb mme2 004(0) Master mode entry 2 mme3 005(0) Master mode entry 3 mme4 007(0) Master mode entry 4 mp2d 206(1) Multiply using two decimal operands mp3d 226(1) Multiply using three decimal operands .spb mpf 401(0) Multiply fraction mpy 402(0) Multiply integer mrl 101(1) Move alphanumeric right to left mve 020(1) Move alphanumeric edited mvn 300(1) Move numeric .spb mvne 024(1) Move numeric edited mvt 160(1) Move alphanumeric with translation narN_ 66N_(1) Numeric descriptor to ARN_ neg 531(0) Negate (A register) negl 533(0) Negate long (AQ register) .spb nop 011(0) No operation ora 275(0) OR to A register oraq 277(0) OR to AQ register orq 276(0) OR to Q register orsa 255(0) OR to storage from A register .brp .alc Table 1-3 (cont) Alphabetic Listing of Processor Instructions .alb .fla 2 |* These instructions are not present on the DPS 8M.||| .spb M__n_e_m_o_n_i_c C__o_d_e M__e_a_n_i_n_g .spb orsq 256(0) OR to storage from Q register orsxN_ 24N_(0) OR to storage from index N_ orxN_ 26N_(0) OR to index N_ puls1 012(0) Pulse location 1 puls2 013(0) Pulse location 2 .spb qlr 776(0) Q register left rotate qls 736(0) Q register left shift qrl 772(0) Q register right logical shift qrs 732(0) Q register right shift rccl 633(0) Read calendar clock .spb rcu 613(0) Restore control unit ret 630(0) Return rmcm 233(0) Read memory controller mask rpd 560(0) Repeat double rpl 500(0) Repeat link rpt 520(0) Repeat rscr 413(0) Read system controller register rsw 231(0) Read switches rtcd 610(0) Return control double s4bd 522(1) Subtract 4-bit displacement from AR .spb s6bd 521(1) Subtract 6-bit displacement from AR s9bd 520(1) Subtract 9-bit displacement from AR sarN_ 74N_(1) Store ARN_ sareg 443(1) Store address registers sb2d 203(1) Subtract using two decimal operands .spb sb3d 223(1) Subtract using three decimal operands sba 175(0) Subtract from A register sbar 550(0) Store base address register sbaq 177(0) Subtract from AQ register sbd 523(1) Subtract bit displacement from AR .spb sbla 135(0) Subtract logical from A register sblaq 137(0) Subtract logical from AQ register sblq 136(0) Subtract logical from Q register sblxN_ 12N_(0) Subtract logical from index N_ sbq 176(0) Subtract from Q register .spb sbxN_ 16N_(0) Subtract from index N_ scd 120(1) Scan character double scdr 121(1) Scan character double reverse scm 124(1) Scan with mask scmr 125(1) Scan with mask reverse .spb .fla 2 scpr 452(0) Store central processor register scu 657(0) Store control unit sdbr 154(0) Store descriptor base register smcm 553(0) Set memory controller mask smic 451(0) Set memory interrupt cells .spb spbp0 250(1) Store segment base pointer of PR0 spbp1 251(0) Store segment base pointer of PR1 spbp2 252(1) Store segment base pointer of PR2 spbp3 253(0) Store segment base pointer of PR3 spbp4 650(1) Store segment base pointer of PR4 .spb spbp5 651(0) Store segment base pointer of PR5 spbp6 652(1) Store segment base pointer of PR6 spbp7 653(0) Store segment base pointer of PR7 spl 447(1) Store pointers and lengths spri 254(0) Store pointer registers as ITS pairs .brp .alc Table 1-3 (cont) Alphabetic Listing of Processor Instructions .spb .alb M__n_e_m_o_n_i_c C__o_d_e M__e_a_n_i_n_g spri0 250(0) Store PR0 as an ITS pair spri1 251(1) Store PR1 as an ITS pair spri2 252(0) Store PR2 as an ITS pair spri3 253(1) Store PR3 as an ITS pair spri4 650(0) Store PR4 as an ITS pair .spb spri5 651(1) Store PR5 as an ITS pair spri6 652(0) Store PR6 as an ITS pair spri7 653(1) Store PR7 as an ITS pair sprpN_ 54N_(0) Store pointer register N_ packed sptp 557(1) Store page table pointers .spb sptr 154(1) Store page table registers sra 754(1) Store ring alarm register sreg 753(0) Store registers ssa 155(0) Subtract stored from A register sscr 057(0) Set system controller register ssdp 557(0) Store segment descriptor pointers ssdr 254(1) Store segment descriptor registers ssq 156(0) Subtract stored from Q register ssxN_ 14N_(0) Subtract stored from index N_ sta 755(0) Store A register .spb stac 354(0) Store A register conditional stacq 654(0) Store A register conditional on Q register staq 757(0) Store AQ register stba 551(0) Store 9-bit characters of A register stbq 552(0) Store 9-bit characters of Q register .spb stc1 554(0) Store instruction counter + 1 stc2 750(0) Store instruction counter + 2 stca 751(0) Store 6-bit characters of A register stcd 357(0) Store control double stcq 752(0) Store 6-bit characters of Q register .spb ste 456(0) Store E register sti 754(0) Store indicator register stq 756(0) Store Q register stt 454(0) Store timer register stxN_ 74N_(0) Store index N_ .spb stz 450(0) Store zero swca 171(0) Subtract with carry from A register swcq 172(0) Subtract with carry from Q register swd 527(1) Subtract word displacement from AR sxlN_ 44N_(0) Store index N_ in lower .spb szn 234(0) Set zero and negative indicators sznc 214(0) Set zero and negative indicators and clear sztl 064(1) Set zero and truncation indicators with bit string left sztr 065(1) Set zero and truncation indicators with bit string right tct 164(1) Test character and translate .spb tctr 165(1) Test character and translate reverse teo 614(0) Transfer on exponent overflow teu 615(0) Transfer on exponent underflow tmi 604(0) Transfer on minus tmoz 604(1) Transfer on minus or zero .spb tnc 602(0) Transfer on no carry tnz 601(0) Transfer on nonzero tov 617(0) Transfer on overflow tpl 605(0) Transfer on plus .brp .alc Table 1-3 (cont) Alphabetic Listing of Processor Instructions .spb .alb M__n_e_m_o_n_i_c C__o_d_e M__e_a_n_i_n_g tpnz 605(1) Transfer on plus and nonzero .spb tra 710(0) Transfer trc 603(0) Transfer on carry trtf 601(1) Transfer on truncation indicator off trtn 600(1) Transfer on truncation indicator on tsp0 270(0) Transfer and set PR0 .spb tsp1 271(0) Transfer and set PR1 tsp2 272(0) Transfer and set PR2 tsp3 273(0) Transfer and set PR3 tsp4 670(0) Transfer and set PR4 tsp5 671(0) Transfer and set PR5 .spb tsp6 672(0) Transfer and set PR6 tsp7 673(0) Transfer and set PR7 tss 715(0) Transfer and set slave tsxN_ 70N_(0) Transfer and set index N_ ttf 607(0) Transfer on tally indicator off .spb ttn 606(1) Transfer on tally indicator on tze 600(0) Transfer on zero ufa 435(0) Unnormalized floating add ufm 421(0) Unnormalized floating multiply ufs 535(0) Unnormalized floating subtract .spb xec 716(0) Execute xed 717(0) Execute double .fin .inl 0 .brp .ifi l2h "Instruction Address Modifiers" Instruction address modifiers are divided into four groups, as shown in Table 1-4. These are: .spb .inl 5 .fif R Register RI Register then indirect IR Indirect then register IT Indirect then tally .inl .fin .spb 2 Standard Modifiers: .ifi tab "Standard Instruction Modifier Chart" .spb 2 .fif ___0_0______0_1______0_2______0_3______0_4______0_5______0_6______0_7____ Type 00 | none | au | qu | du | ic | al | ql | dl | R 10 | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | R 20 | n* | au* | qu* | IPR | ic* | al* | ql* | IPR | RI  30 |_ _0_*_ _ _ _|_ _1_*_ _ _ _|_ _2_*_ _ _ _|_ _3_*_ _ _ _|_ _4_*_ _ _ _|_ _5_*_ _ _ _|_ _6_*_ _ _ _|_ _7_*_ _ _ _|_ RI 40 | f1 | itp | IPR | its | sd | scr | f2 | f3 | IT 50 | ci | i | sc | ad | di | dic | id | idc | IT 60 | *n | *au | *qu | *du | *ic | *al | *ql | *dl | IR  70 |_ _*_0_ _ _ _|_ _*_1_ _ _ _|_ _*_2_ _ _ _|_ _*_3_ _ _ _|_ _*_4_ _ _ _|_ _*_5_ _ _ _|_ _*_6_ _ _ _|_ _*_7_ _ _ _|_ IR .spb .alc (where IPR means IPR fault if detected) .alb .fin .spb 2 Special Modifiers: .spb _i_n_s_t _t_a_g _m_e_a_n_i_n_g .spb scpr 00 Store APU history register 01 Store fault register 06 Store mode register and cache mode register 20 Store CU history register 40 Store OU history register 60 Store DU history register .spb lcpr 02 Load cache mode register 03 Load 0's into all history registers 04 Load mode register 07 Load 1's into all history registers .fin .alb .brp .ifi l2h "Multics Indirect Words" .cbn Multics processors have .cbf two special indirect words that are active in Multics mode; the indirect-to-segment (ITS) pointer pair and the indirect-to-pointer (ITP) pointer pair. These words are recognized only when an RI or IR address modification references an even location. .ifi l3h "ITS Pair Format" .srv draft "ITS/IPT FORMAT" The indirect-to-segment (ITS) word pair is an indirect pointer to a segment in a Multics process. Segment offset and additional address modification are permitted. .spb 2 PL/I Declaration (its.incl.pl1) .spb .fif declare 1 its based aligned, /* Even word */ (2 pad1 bit(3), 2 segno bit(15), 2 ringno bit(3), 2 pad2 bit(9), 2 its_mod bit(6), 2 offset bit(18), /* Odd word */ 2 pad3 bit(3), 2 bit_offset bit(6), 2 pad4 bit(3), 2 mod bit(6)) unaligned; .spb 2 Even Word: .spb .inl 3 0 0 0 1 1 2 2 2 3 3 _0____2__3____________________________7__8____0__1________________9__0__________5__ | | | | | | |0 0 0| SEGNO | RN |0 0 0 0 0 0 0 0 0| (43)8 | _|______|______________________________|______|__________________|____________| 3 15 3 9 6 .spb 2 .unl 3 Odd Word: .spb 0 1 1 2 2 2 2 2 3 3 _0__________________________________7__8____0__1__________6__7____9__0__________5__ | | | | | | | WORDNO |0 0 0| BITNO |0 0 0| MOD | _|____________________________________|______|____________|______|____________| 18 3 6 3 6 .ifi fig "ITS Pair Format" .spb .alb .fin .unl 3 Legend: .spb .inl 10 .unl 10 SEGNO (its.segno) 15-bit segment number. .spb .unl 10 RN (its.ringno) a lower bound for the value of TPR.TRR (temporary ring register) for the address preparation involving this ITS pair. .spb .unl 10 (43)8 (its.its_mod) ITS modifier. .spb .unl 10 WORDNO (its.offset) word offset to be used in calculating the computed address within the segment. .spb .unl 10 BITNO (its.bit_offset) bit offset to be used in calculating the computed address within the segment. .spb .unl 10 MOD (its.mod) any valid instruction modifier. .inl 0 .fin .alb .ifi l3h "ITP Pair Format" The indirect-to-pointer (ITP) word pair is similar to the ITS pair except that it specifies the number of a pointer register (PRNUM) that already contains a valid pointer to the segment to which access is desired. .spb 2 .fif PL/I Declaration (its.incl.pl1) .spb declare 1 itp based aligned, /* Even word */ (2 pr_no bit(3), 2 pad1 bit(27), 2 itp_mod bit(6), 2 offset bit(18), /* Odd word */ 2 pad2 bit(3), 2 bit_offset bit(6), 2 pad3 bit(3), 2 mod bit(6)) unaligned; .spb 2 Even Word: .spb .inl 3 0 0 0 2 3 3 _0____2__3____________________________________________________9__0__________5__ | | | | |PRNUM|0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| (41)8 | _|______|______________________________________________________|____________| 3 27 6 .spb 2 .unl 3 Odd Word: .spb 0 1 1 2 2 2 2 2 3 3 _0__________________________________7__8____0__1__________6__7____9__0__________5__ | | | | | | | WORDNO |0 0 0| BITNO |0 0 0| MOD | _|____________________________________|______|____________|______|____________| 18 3 6 3 6 .inl 0 .ifi fig "ITP Pair Format" .spb Legend: .spb .inl 10 .fin .alb .unl 10 PRNUM (itp.pr_no) the number (0-7) of the pointer register to be used in the indirect reference. .spb .unl 10 (41)8 (itp.itp_mod) ITP modifier. .spb .unl 10 WORDNO (itp.offset) word offset as for ITS. .spb .unl 10 BITNO (itp.bit_offset) bit offset as for ITS. .spb .unl 10 MOD (itp.mod) any valid instruction modifier. .inl 0 .brp .ifi l1h "Appending Unit Formats" After the CU has completed its address modifications, the processor appending unit (APU) converts the final virtual address (segment, page, and offset) to a 24-bit absolute store address, as required for the store access, when a store access is required. .ifi l2h "Segment Descriptor Word Format" .srv draft "SDW FORMAT" .alb .fin The segment descriptor word (SDW) pair contains information necessary to control the access to a segment by a process. The SDW for a segment is constructed from data in the directory entry for the segment and in the system segment table (SST) when the segment is faulted upon by the process. The SDW for segment N_ (unique within the process) is placed at offset 2_N_ in the descriptor segment (dseg) of the process. .spb 2 PL/I Declaration (sdw.incl.pl1) .spb .fif dcl 1 sdw based (sdwp) aligned, /* Even word */ (2 add bit(24), 2 (r1, r2, r3) bit(3), 2 df bit(1), 2 df_no bit(2), 2 pad1 bit(1), /* Odd word */ 2 bound bit(14), 2 read bit(1), 2 execute bit(1), 2 write bit(1), 2 privileged bit(1), 2 unpaged bit(1), 2 entry_bound_sw bit(1), 2 cache bit(1), 2 entry_bound bit(14)) unaligned; .spb 2 Even Word: .spb .inl 3 0 2 2 2 2 2 3 3 3 3 3 _0______________________________________________3__4____6__7____9__0____2__3__4__5__ | | | | | | | | ADDR | R1 | R2 | R3 |F| FC| _|________________________________________________|______|______|______|__|____| 24 3 3 3 1 2 .spb 2 .unl 3 Odd Word: .spb 0 0 1 1 1 1 1 1 2 2 2 3 _0__1__________________________4__5__6__7__8__9__0__1__2__________________________5__ | | | | | | | | | | | |0| BOUND |R|E|W|P|U|G|C| CL | _|__|____________________________|__|__|__|__|__|__|__|____________________________| 1 14 1 1 1 1 1 1 1 14 .inl 0 .ifi fig "Segment Descriptor Word (SDW) Format" .brp Legend: .spb .alb .fin .inl 20 .unl 20 M__a_s_k F__i_e_l_d M__e_a_n_i_n_g .spb .unl 20 777777 U ADDR (sdw.add) base address of segment (U=1) or .unl 20 770000 L segment page table (U=0). .spb .unl 20 007000 R1 (sdw.r1) highest effective read/write ring. .spb .unl 20 000700 R2 (sdw.r2) highest effective read/execute ring. .spb .unl 20 000070 R3 (sdw.r3) highest effective call ring. .spb .unl 20 000004 F (sdw.df) directed fault indicator. .inl +4 .unl 4 1 = the necessary unpaged segment or segment page table is in memory. .unl 4 0 = execute the directed fault specified in FC. .inl -4 .spb .unl 20 000003 FC (sdw.df_no) the number of the directed fault (DF0-DF3) to be executed if F=0. .spb .unl 20 377770 BOUND (sdw.bound) highest modulo 16 computed address (offset) that may be used in referencing the segment without causing an out_of_segment_bounds fault (ACV-OOSB). .spb .unl 20 000004 R (sdw.read) read permission bit. .spb .unl 20 000002 E (sdw.execute) execute permission bit (xec and xed excluded). .spb .unl 20 000001 W (sdw.write) write permission bit. .spb .inl 20 .unl 20 400000 P (sdw.privileged) privileged mode bit. .inl +4 .unl 4 0 = privileged instructions cannot be executed in this segment. .unl 4 1 = privileged instructions can be executed in this segment if it runs in ring 0. .inl -4 .spb .unl 20 200000 U (sdw.unpaged) paged/unpaged bit. .inl +4 .unl 4 0 = segment is paged and ADDR is the address of the page table. .unl 4 1 = segment is unpaged and ADDR is the base address of the segment. .inl -4 .spb .unl 20 100000 G (sdw.entry_bound_sw) gate indicator bit. .inl +4 .unl 4 0 = any call from an external segment must be to an offset less than the value of CL. .unl 4 1 = any valid segment offset may be called. .inl -4 .spb .unl 20 040000 C (sdw.cache) cache control bit. .inl +4 .unl 4 0 = words (operands or instructions) from this segment cannot be placed in the cache. .unl 4 1 = words from this segment can be placed in the cache. .inl -4 .spb .unl 20 037777 CL (sdw.entry_bound) call limiter. .brf Any external call to this segment must be to an offset less than CL if G=0. .inl 0 .srv draft "PTW FORMAT" .ifi l2h "Page Table Word Format" The page table word (PTW) contains location and state information for a page of a paged segment. The PTWs for a paged segment are created in a free entry in the active segment table (AST) area of the SST when the segment is first referenced by some process. Subsequent segment faults by other processes reference the existing page table. .brp .fif PL/I Declaration (ptw.incl.pl1) .spb dcl 1 ptw based (ptp) aligned, 2 add bit(18) unaligned, 2 did bit(4) unaligned, 2 first bit(1) unaligned, 2 processed bit(1) unaligned, 2 unusable1 bit(2) unaligned, 2 phu bit(1) unaligned, 2 unusable2 bit(1) unaligned, 2 nypd bit(1) unaligned, 2 phm bit(1) unaligned, 2 phu1 bit(1) unaligned, 2 wired bit(1) unaligned, 2 os bit(1) unaligned, 2 df bit(1) unaligned, 2 df_no bit(2) unaligned; .spb .inl 3 0 1 1 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 _0__________________________________7__8______1__2__3__4__5__6__7__8__9__0__11__2__3__4__5__ | | | | | | | | | | | | | | | | ADDR | DID |D|P|0 0|U|0|Y|M|Q|W|S|F| FC| _|____________________________________|________|__|__|____|__|__|__|__|__|__|__|__|____| 18 4 1 1 2 1 2 1 1 1 1 1 2 .inl 0 .ifi fig "Page Table Word (PTW) Format" .spb .inl 0 Legend: .spb .fin .inl 20 .unl 20 M__a_s_k F__i_e_l_d M__e_a_n_i_n_g .spb .unl 20 777777 ADDR (ptw.add) modulo 64 page address if page is in store, or record number of page if page is not in store. .spb For!a 1024-word page size, the hardware ignores the four LSB of the in-main-memory page address. .spb .fin .unl 20 740000 DID (ptw.did) device identifier for device containing the page (used only by software). .spb .unl 20 020000 D (ptw.first) paging device update delay bit (used only by software). .inl +4 .unl 4 1 = page must not be written to paging device. .unl 4 0 = page can be written to paging device. .inl -4 .spb .unl 20 010000 P (ptw.processed) temporary bit used in post_purging (used only by software). .spb .unl 20 001000 U (ptw.phu) used (referenced) bit (set by hardware). .inl +4 .unl 4 1 = page has been used. .unl 4 0 = page has not been used. .inl -4 .spb .unl 20 000200 Y (ptw.nypd) not yet on paging device bit (used only by hardware). .inl +4 .unl 4 1 = page has not been updated to paging device. .unl 4 0 = page has been updated to paging device. .inl -4 .spb .unl 20 000100 M (ptw.phm) modified bit (set by hardware). .inl +4 .unl 4 1 = page has been modified. .unl 4 0 = page has not been modified. .inl -4 .spb .unl 20 000040 Q (ptw.phu1) quantum bit (used only by software). .inl +4 .unl 4 1 = page has been used during the quantum. .unl 4 0 = page has not been used during the quantum. .inl -4 .spb .unl 20 000020 W (ptw.wired) wired bit (used only by software). .inl +4 .unl 4 1 = page is wired. .unl 4 0 = page is not wired. .inl -4 .spb .unl 20 000010 S (ptw.os) out of service bit (used only by software). .inl +4 .unl 4 1 = page is out of service (I/O in progress). .unl 4 0 = page is in service. .inl -4 .spb .unl 20 000004 F (ptw.df) main memory bit (checked by hardware). .inl +4 .unl 4 1 = page is in main memory. .unl 4 0 = page is not in main memory. Execute directed fault FC. .inl -4 .spb .unl 20 000003 FC (ptw.df_no) directed fault number for page fault (checked by hardware). .inl 0 .ifi l2h "Descriptor Base Register Format" .srv draft "DBR FORMAT" The descriptor base register (DBR) specifies the descriptor segment for the process. Because of the high degree of similarity between the SDW and the DBR data, the declaration for the SDW is used for the equivalent fields of the DBR data. .spb 2 .inl 0 Even Word: .spb .fif .inl 3 0 2 2 3 _0______________________________________________3__4______________________5__ | | | | ADDR |0 0 0 0 0 0 0 0 0 0 0 0| _|________________________________________________|________________________| 24 12 .spb 2 .unl 3 Odd Word: .spb 0 0 1 1 1 1 2 2 2 3 _0__1__________________________4__5______8__9__0______3__4______________________5__ | | | | | | | |0| BOUND |0 0 0 0|U|0 0 0 0| STACK | _|__|____________________________|________|__|________|________________________| 1 14 4 1 4 12 .inl 0 .ifi fig "Descriptor Base Register (DBR) Format" .spb .fin Legend: .spb .inl 10 .unl 10 ADDR (sdw.add) base address of descriptor segment (U=1) or descriptor segment page table (U=0). .spb .unl 10 BOUND (sdw.bound) highest modulo 16 offset within the descriptor segment that will not cause an out-of-segment-bounds fault (ACV-OOSB). (This is twice the first out-of-bounds segment number.) .spb .unl 10 U (sdw.unpaged) paged/unpaged bit. .brf 1 = descriptor segment is unpaged. .brf 0 = descriptor segment is paged. .spb .unl 10 STACK (sdw.entry_bound) 12 MSB of the 15-bit stack segment number for the process. This field is referenced only by the "call6" instruction. .inl 0 .brf .ifi l2h "Associative Memory Formats" .cbn Multics processors contain .cbf two associative memories that greatly reduce the number of main store accesses required for the address preparation function. The degree of store access reduction depends on the degree of locality of reference of the procedure executing in the processor. .ifi l3h "SDW Associative Memory" .srv draft "SDWAM FORMAT" The segment descriptor word associative memory (SDWAM) contains the SDWs and segment numbers for the .cbd most recently used segments for the process currently using the processor. .cbn For the L68 and DPS Processors, the SDW associative memory will hold the 16 most recently used (MRU) SDWS and has a full associative organization with least recently used (LRU) replacement. For the DPS 8M Processor, the SDW associative memory will hold the 4 (MRU) SDWS and has a 4 way set associative organiztion with (LRU) replacement. .cbf When a given segment is accessed, the SDWAM is queried with the segment number before a main memory access to the descriptor segment is made. If a match is found, the SDWAM returns the SDW and the need for the main memory access is obviated. .spb 2 Because the SDWAM register holds an SDW with the directed-fault fields cleared, the data in main memory is described by the declaration for the SDW. Because the SDWAM match logic register is not used by Multics, there is no software declaration for the data in main memory. .spb 2 The ssdr instruction stores the SDWAM registers in the following format: .inl 0 .spb 2 SDWAM Register Upper Half: .spb 2 .fif .inl 3 0 2 2 2 2 2 3 3 3 3 _0______________________________________________3__4____6__7____9__0____2__3____5__ | | | | | | | ADDR | R1 | R2 | R3 |0 0 0| _|________________________________________________|______|______|______|______| 24 3 3 3 3 .spb 2 .unl 3 SDWAM Register Lower Half: .spb 2 3 3 5 5 5 5 5 5 5 5 5 7 _6__7__________________________0__1__2__3__4__5__6__7__8__________________________1__ | | | | | | | | | | | |0| BOUND |R|E|W|P|U|G|C| CL | _|__|____________________________|__|__|__|__|__|__|__|____________________________| 1 14 1 1 1 1 1 1 1 14 .inl 0 .ifi fig "SDW Associative Memory (SDWAM) Register Format" .spb Legend: .spb .inl 10 .unl 10 ADDR (sdw.add) segment address as in SDW format (see Figure 1-4 above). .spb .unl 10 R1 (sdw.r1) read/write ring bracket as in SDW format. .spb .unl 10 R2 (sdw.r2) read/execute ring bracket as in SDW format. .spb .unl 10 R3 (sdw.r3) call ring bracket as in SDW format. .spb .unl 10 BOUND (sdw.bound) segment bound as in SDW format. .spb .unl 10 R,E,W,P, access control bits as in SDW format. .brf .unl 10 U,G,C .spb .unl 10 CL (sdw.entry_bound) call limiter as in SDW format. .spb 2 .inl 0 The ssdp instruction stores the SDWAM match logic registers in the following format: .spb 2 .inl 3 .fif .cbn 0 1 1 2 2 2 2 3 3 0 4 5 6 7 8 9 0 5 ----------------------------------------------------------------------- | | | | |0 0|USE (L68) | | POINTER |0 0 0 0 0 0 0 0 0 0 0 0|F|0 0|--------------| | | | | | USE (DPS 8M) | ---------------------------------------------------------------------- 15 12 1 2 6 .cbf .fin .ifi fig "SDW Associative Memory (SDWAM) Match Logic Register Format" .spb .inl 0 .fin Legend: .spb .inl 10 .unl 10 POINTER 15-bit effective segment number generated when this SDW was fetched from main memory. .spb .unl 10 F full/empty bit. .brf 1 = this AM register contains a valid SDW. .brf 0 = this AM register is empty. .spb .unl 10 USE usage count. .brf .cbn The "oldest" SDWAM entry has a count of 00 and the "newest" has a count of 17 (octal) on L68 and DPS Processors, and a count of 77 (octal) on DPS!8M Processors. .cbf .inl 0 .ifi l3h "PTW Associative Memory" .srv draft "PTWAM FORMAT" The .cbd page table word associative memory (PTWAM) contains the in-main-memory addresses and the segment and page numbers of the .cbd most recently used pages for the process currently using the processor. .cbn For the L68 and DPS Processors, the PTW associative memory will hold the 16 most recently used (MRU) PTWS and has a full associative organization with least recently used (LRU) replacement. For the DPS 8M processor, the PTW associative memory will hold the 4 (MRU) PTWS and has a 4 way set associative organiztion with (LRU) replacement. .cbf When a paged segment is accessed, the PTWAM is first queried with the segment and page number. If a match is found, the PTWAM returns the in-main-memory page address and the main memory access to the PTW is obviated. .spb 2 Because the PTWAM register holds a PTW with some control bits cleared, the data in main memory is described by the declaration for the PTW. Because the PTWAM match logic register is not used by Multics, there is no software declaration for the data in main memory. .spb 2 The sptr instruction stores the PTWAM registers in the following format: .spb 2 .inl 0 PTWAM Register: .fif .spb 2 .inl 3 0 1 1 2 2 3 3 0 7 8 8 9 0 5 _________________________________________________________________________ | | | | | | ADDR |0 0 0 0 0 0 0 0 0 0 0|M|0 0 0 0 0 0| |___________________________________|_____________________|_|___________| 18 11 1 6 .inl 0 .ifi fig "PTW Associative Memory (PTWAM) Register Format" .spb Legend: .spb .inl 10 .unl 10 .fin ADDR (ptw.add) modulo 64 page address as in PTW format (see Figure 1-5 above). .spb .unl 10 M (ptw.phm) modified bit. .inl +4 .unl 4 1 = page has been modified. .unl 4 0 = page has not been modified. .inl 0 .spb 2 PTWAM Match Logic Register: .spb 2 The sptp instruction stores the PTWAM pointers in the following format: .spb 2 .inl 3 .fif .cbn 0 1 1 2 2 2 2 3 3 0 4 5 6 7 8 9 0 5 ------------------------------------------------------------------------------ | | | | | 0 0 |USE (L68)| | POINTER | PAPGENO |F| 0 0|---------------| | | | | | USE (DPS 8M) | |_____________________________________________________|_|____|_______________| 15 12 1 2 6 .cbf .inl 0 .ifi fig "PTW Associative Memory (PTWAM) Match Logic Register Format" .spb .fin Legend: .spb .inl 10 .spb .unl 10 POINTER effective segment number as in SDWAM format (see Figure 1-8 above). .spb .unl 10 PAGENO page number to which this PTW refers. .spb For!a 1024-word page size, the four LSB are forced to zero by the hardware. .spb .unl 10 F full/empty bit as in SDWAM format. .spb .unl 10 USE usage count as in SDWAM format. .inl 0 .ifi l1h "Decimal Unit Formats" .srv draft "EIS FORMATS" The decimal unit (DU) is that portion of the processor hardware that executes the extended instruction set (EIS) instructions for bit- and character-string processing and for decimal arithmetic. .ifi l2h "EIS Multiword Instruction Format" The EIS processor instructions occupy one, three or four words in memory depending upon the number of EIS data descriptors required for their execution. Single word EIS instructions have the same format as the basic instructions already described. .spb (There is no include file for the declaration of this data.) .spb 2 .inl 3 .fif 0 1 1 2 2 2 3 _0__________________________________7__8__________________7__8__9____________5__ | | | | | | VARIABLE | OPCODE |I| MF1 | _|____________________________________|____________________|__|______________| | 18 10 1 7| | Data Descriptor or Indirect Data Descriptor Pointer for Operand 1 | _|________________________________________________________________________| | | | Data Descriptor or Indirect Data Descriptor Pointer for Operand 2 | _|________________________________________________________________________| | | | Data Descriptor or Indirect Data Descriptor Pointer for Operand 3 | _|________________________________________________________________________| 36 .inl 0 .ifi fig "EIS Multiword Instruction Format" .fin .spb Legend: .spb .inl 10 .unl 10 VARIABLE Interpreted according to the requirements of the individual EIS instructions; contains MF2 and MF3 for the second and third data descriptors if needed. .spb .unl 10 OPCODE Instruction operation code. .spb .unl 10 I Interrupt inhibit bit. .spb .unl 10 MF1 Modification field for data descriptor 1. .inl 0 .ifi l2h "EIS Data Descriptor Modification Field Format" Many of the EIS data descriptors required by EIS instructions will have a modification field (MF) in the first word of the multiword instruction. The MF fields contain additional address preparation information that cannot be contained in the data descriptor. .spb 2 PL/I Declaration (derived from eis_bits.incl.alm) .spb dcl 1 mf based unaligned, 2 ar bit(1), 2 rl bit(1), 2 id bit(1), 2 reg bit(4); .spf 2 .brp .fif .inl 31 0 0 0 0 0 _0__1__2__3________7__ | | | | | |a|b|c| REG | _|__|__|__|__________| 1 1 1 4 .inl 0 .ifi fig "EIS Data Descriptor Modification Field (MF) Format" .spb Legend: .spb .fin K__e_y F__i_e_l_d M__e_a_n_i_n_g .inl 20 .unl 20 .spb a AR (mf.ar) pointer register control in preparing addresses from this descriptor. .inl +4 .unl 4 0 = pointer register not to be used. .unl 4 1 = pointer register is used. .spb .inl -4 .unl 20 b RL (mf.rl) register length control. .inl +4 .unl 4 0 = N field of the descriptor is operand length. .unl 4 1 = N field of the descriptor is number of register containing operand length. .spb .inl -4 .unl 20 c ID (mf.id) indirect descriptor control. .inl +4 .unl 4 0 = operand descriptor follows instruction word in its sequential location. .unl 4 1 = operand descriptor location contains an indirect pointer to the descriptor. .spb .inl -4 .unl 20 REG (mf.reg) register number for R-type modification of ADDRESS of the descriptor. (see "EIS Instruction Address Modification Codes" below.) .inl 0 .ifi l2h "EIS Data Descriptor Formats" The words occupying the data descriptor locations following an EIS instruction are either an indirect data descriptor pointers or any of the three EIS data descriptors. .ifi l3h "Indirect Data Descriptor Pointer Format" .fif (There is no include file for the declaration of this data.) .spb 2 .inl 3 0 1 1 2 2 3 3 3 3 _0__________________________________7__8____________________8__9__0__1__2______5__ | | | | | | | ADDRESS |0 0 0 0 0 0 0 0 0 0 0|A|0 0| REG | _|____________________________________|______________________|__|____|________| 18 11 1 2 4 .inl 0 .ifi fig "EIS Indirect Data Descriptor Pointer Format" .spb Legend: .spb .fin .inl 10 .unl 10 ADDRESS For!A=0; 18-bit procedure segment address. .brf For!A=1; 3-bit pointer register number and 15-bit signed word offset. .spb .unl 10 A Pointer register flag. .spb .unl 10 REG Address modification code. (see "EIS Instruction Address Modification Codes" below.) .fif .inl 0 .brf .ifi l3h "Bit String Data Descriptor Format" .fif (There is no include file for the declaration of this data.) .spb 2 .inl 3 0 1 1 1 2 2 2 3 _0__________________________________7__8__9__0______3__4______________________5__ | | | | | | ADDRESS | C | B | N | _|____________________________________|____|________|________________________| 18 2 4 12 .inl 0 .ifi fig "EIS Bit String Data Descriptor Format" .fin .spb Legend: .spb Given that this is descriptor _n: .spb .inl 10 .unl 10 ADDRESS For!MF_n.AR=0; 18-bit procedure segment address. .brf For!MF_n.AR=1; 3-bit pointer register number and 15-bit signed word offset. .spb .unl 10 C Character position offset within the word determined by ADDRESS. This count is in units of 9-bit characters. .spb .unl 10 B Bit position offset within the character determined by C. .spb .unl 10 N For!MF_n.RL=0; 12-bit bit count. .brf For!MF_n.RL=1; eight "0" bits and 4-bit number of register containing bit count. .fif .inl 0 .ifi l3h "Alphanumeric Data Descriptor Format" .fif (There is no include file for the declaration of this data.) .spb .inl 3 0 1 1 2 2 2 2 2 3 _0__________________________________7__8____0__1__2__3__4______________________5__ | | | | | | | ADDRESS | CN |TA |0| N | _|____________________________________|______|____|__|________________________| 18 3 2 1 12 .inl 0 .ifi fig "EIS Alphanumeric Data Descriptor Format" .spb Legend: .spb .fin Given that this is descriptor _n: .spb .inl 10 .unl 10 ADDRESS For!MF_n.AR=0; 18-bit procedure segment address. .brf For!MF_n.AR=1; 3-bit pointer register number and 15-bit signed word offset. .spb .unl 10 CN Character position offset within the word determined by ADDRESS. This count depends on the character size (TA) specified by the descriptor. .inl +8 .unl 8 .spb .trf !! 9-bit: character positions 0 to 3 are designated by CN = 000,010,100,110 respectively. Other codes are invalid. .unl 8 6-bit: character positions 0 to 5 are designated by CN = 000 through 101. 110 and 111 are invalid. .unl 8 4-bit: character positions 0 to 7 are designated by CN = 000 through 111. .spb .inl 10 .trf ! .unl 10 TA Alphanumeric character type code .fif .spb 00 = 9-bit character 01 = 6-bit character 10 = 4-bit character 11 = illegal (IPR fault) .fin .unl 10 .spb N For!MF_n.RL=0; 12-bit character count. .brf For!MF_n.RL=1; eight "0" bits and 4-bit number of register containing character count. .fif .inl 0 .ifi l3h "Numeric Data Descriptor Format" .trf ! (There is no include file for the declaration of this data.) .spb .inl 3 .fif 0 1 1 2 2 2 2 2 2 3 3 _0__________________________________7__8____0__1__2__3__4__________9__0__________5__ | | | | | | | | ADDRESS | CN |T| S | SF | N | _|____________________________________|______|__|____|____________|____________| 18 3 1 2 6 6 .inl 0 .ifi fig "EIS Numeric Data Descriptor Format" .spb Legend: .spb .fin Given that this is descriptor _n: .spb .inl 10 .unl 10 ADDRESS For!MF_n.AR=0; 18-bit procedure segment address. .brf For!MF_n.AR=1; 3-bit pointer register number and 15-bit signed word offset. .spb .unl 10 CN Character position offset within the word determined by ADDRESS. This count is in units of the character size specified by the descriptor. .spb .unl 10 T Numeric character type code. .brf 0 = 9-bit character .brf 1 = 4-bit character .spb .unl 10 S Sign and decimal type code. .brf 00 = Leading sign, floating point .brf 01 = Leading sign, scaled .brf 10 = Trailing sign, scaled .brf 11 = No sign, scaled .spb .unl 10 SF Scaling factor. .spb .unl 10 N For!MF_n.RL=0; 6-bit character count. .brf For!MF_n.RL=1; two "0" bits and 4-bit number of register containing character count. .inl 0 .ifi l3h "EIS Instruction Address Modification Codes" The address modification codes used in the "REG" field of the EIS data descriptor modification field and the indirect data descriptor pointer and in the "N" field of the data descriptors are slightly different from those used in the basic instructions. .spb .fif Octal Basic "N" Type Code "R" Type "REG" Type (1) MF_n.RL=1 (2) .spb 00 None None Invalid (3) 01 au au au 02 qu qu qu 03 du du Invalid 04 ic ic Invalid 05 al a a 06 ql q q 07 dl Invalid Invalid 10 x0 x0 x0 11 x1 x1 x1 12 x2 x2 x2 13 x3 x3 x3 14 x4 x4 x4 15 x5 x5 x5 16 x6 x6 x6 17 x7 x7 x7 .spb .inl 10 .alb .fin .unl 10 (a) When the "REG" field of an indirect data descriptor pointer contains a register code, the specified register contents are interpreted as a word index value. .spb When the "REG" field of the EIS data descriptor modification field contains a register code, the specified register contents are interpreted as a character index value. The size of the character is specified by the data type given in the data descriptor. .spb When the descriptor word does not have an associated MF field in the instruction word, its format is identical to an indirect data descriptor. .spb The A and Q registers provide for indexing by values greater than the range of an 18-bit field. For!address modification codes 05 and 06, low-order bits of the specified register are used as follows: .spb Bit strings lowest 24 bits .brf 4- and 6-bit characters lowest 21 bits .brf 9-bit characters lowest 20 bits .spb All index values are taken as unsigned, positive integers. .spb .unl 10 (b) Except in the cases of address modification codes 05 and 06, the full 18-bit extent of the specified register is used for the value of string length. For!codes 05 and 06, the bit extents given in (a) above apply. .spb .unl 10 (c) Invalid address modification codes cause an IPR fault. .inl 0 .ifi l2h "EIS Data Formats" There are six valid formats for data intended for use by the DU: bit string data, three modes of alphanumeric data, and two modes of numeric data. .ifi l3h "Bit String Data Format" The data is a string of contiguous bits starting anywhere in a word and having extent without regard to word or character boundaries. .spb 2 (There is no include file for the declaration of this data.) .spb .inl 3 .fif 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 _0__1__2__3__4__5__6__7__8__9__0__1__2__3__4__5__6__7__8__9__0__1__2__3__4__5__6__7__8__9__0__1__2__3__4__5__ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |B|B|B|B|B|B|B|B|B|B|B|B|B|B|B|B|B|B|B|B|B|B|B|B|B|B|B|B|B|B|B|B|B|B|B|B| _|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__| 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 .inl 0 .ifi fig "EIS Bit String Data Format" .spb .fin .ifi l3h "Alphanumeric Data Format" The data is a string of 4, 6, or 9-bit characters starting at any character boundary and having extent without regard to word boundaries. In 4-bit mode, the "0" bits are _n_o_t part of the data. The DU skips over them in input data and inserts them in output data. .spb 2 (There is no include file for the declaration of this data.) .spb 2 .inl 3 .fif 0 0 0 0 0 0 1 1 1 1 1 1 2 2 2 2 2 3 3 3 _0__1______4__5______8__9__0______3__4______7__8__9______2__3______6__7__8______1__2______5__ | | | | | | | | | | | | | |0| C | C |0| C | C |0| C | C |0| C | C | _|__|________|________|__|________|________|__|________|________|__|________|________| 1 4 4 1 4 4 1 4 4 1 4 4 .inl 0 .ifi fig "EIS Alphanumeric Data Format, 4-bit Mode" .spb .fif .inl 3 .spb 0 0 0 1 1 1 1 2 2 2 3 3 _0__________5__6__________1__2__________7__8__________3__4__________9__0__________5__ | | | | | | | | C | C | C | C | C | C | _|____________|____________|____________|____________|____________|____________| 6 6 6 6 6 6 .inl 0 .ifi fig "EIS Alphanumeric Data Format, 6-bit Mode" .fif .spb .inl 3 0 0 0 1 1 2 2 3 _0________________8__9________________7__8________________6__7________________5__ | | | | | | C | C | C | C | |__________________|__________________|__________________|__________________| 9 9 9 9 .inl 0 .ifi fig "EIS Alphanumeric Data Format, 9-bit Mode" .spb .fin .ifi l3h "Numeric Data Format" The data is a string of numeric digits starting at any digit boundary and having extent without regard to word boundaries. In 4-bit mode, the "0" bits are _n_o_t part of the data. The DU skips over them in input data and inserts them in output data. .spb 2 (There is no include file for the declaration of this data.) .spb 2 .inl 3 .fif 0 0 0 0 0 0 1 1 1 1 1 1 2 2 2 2 2 3 3 3 _0__1______4__5______8__9__0______3__4______7__8__9______2__3______6__7__8______1__2______5__ | | | | | | | | | | | | | |0| D | D |0| D | D |0| D | D |0| D | D | _|__|________|________|__|________|________|__|________|________|__|________|________| 1 4 4 1 4 4 1 4 4 1 4 4 .inl 0 .ifi fig "EIS Numeric Data Format, 4-Bit Mode" .spb .fin Legend: .spb .inl 10 Each D represents a digit, a sign, or an exponent, depending on the descriptor. The digits 0 through 9 are represented by a D of 0000 through 1001. A D of 1010 through 1111 where a digit is expected will cause an IPR fault; D's of 1010, 1011, 1100, 1110, and 1111 are interpreted as "+"; 1101 is interpreted as "-". The hardware always generates 1100 or 1011 for "+". If the descriptor indicates floating point, the last two D's form an 8-bit twos-complement exponent. .fif .spb 2 .inl 3 0 0 0 1 1 2 2 3 _0________________8__9________________7__8________________6__7________________5__ | | | | | | D | D | D | D | _|__________________|__________________|__________________|__________________| 9 9 9 9 .inl 0 .ifi fig "EIS Numeric Data Format, 9-Bit Mode" Legend: .spb .inl 10 Each D represents a digit, a sign, or an exponent. For!digits and signs, the low-order 4 bits are interpreted as in 4-bit mode. The hardware always generates octal 060 through 071 for digits, 053 for "+", and 055 for "-". If the descriptor indicates floating point, the low-order 8 bits of the last D is the twos-complement exponent. .fin .brf .ifi l2h "DU Pointers and Lengths Format" The following is the format of the eight words of data stored by the spl instruction. The data reflects the exact state of execution of an EIS instruction by the DU. This same data is reloaded into the DU by the lpl instruction. .spb 2 (There is no include file for the declaration of this data.) .spb 2 .inl 3 .fif 0 0 0 1 1 1 3 _0________________8__9__0__1__2______________________________________________5__ | | | | | | |0 0 0 0 0 0 0 0 0|Z|/O|0| CH TALLY | 1___________________|__|__|__|________________________________________________| 9 1 1 1 24 .fin .inl 0 .ifi fig "DU Pointers and Lengths Format, Word 0" .spb Legend: .spb .inl 10 .fin .unl 10 Z All bit string instruction results are zero. .spb .unl 10 /O Negative overpunch found in 6-4 expanded move. .spb .unl 10 CH TALLY The number of characters examined by the SCAN, TCT, or TCTR instruction (up to the interrupt or match). .inl 0 .fif .spb 2 .inl 3 0 3 _0_______________________________________________________________________5_ | | |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| _|________________________________________________________________________| 36 .inl 0 .ifi fig "DU Pointers and Lengths Format, Word 1" .spb .inl 3 .fif 0 2 2 2 2 2 2 3 3 3 3 3 _0______________________________________________3__4__5__6__7____9__0__1__2__3____5__ | | | | | | | | | | D1 PTR |0|TA |0 0 0|I|F|A|0 0 0| _|________________________________________________|__|____|______|__|__|__|______| 24 1 2 3 1 1 1 3 .fin .inl 0 .ifi fig "DU Pointers and Lengths Format, Word 2" Legend: .spb .inl 10 .unl 10 .fin D1 PTR Address of last double word accessed by descriptor 1. Bits 17-23 (bit address) valid only for initial access. .spb .unl 10 TA Alphanumeric type (bits 21-22) of descriptor 1. .spb .unl 10 I DU interrupted flag; a copy of the MIF fault indicator. This bit is _n_o_t reloaded by lpl. .spb .unl 10 F First time. Data in descriptor 1 is valid. .spb .unl 10 A Descriptor 1 is active. .spb 2 .fif .inl 3 0 0 1 1 1 3 _0__________________9__0__1__2______________________________________________5__ | | | | | LEVEL |0 0| D1 RES | _|____________________|____|________________________________________________| 10 2 24 .inl 0 .ifi fig "DU Pointers and Lengths Format, Word 3" .spb Legend: .spb .inl 10 .unl 10 .fin LEVEL The difference in the count of characters loaded into the CPU and characters stored back from the CPU. .spb .unl 10 D1 RES The count of characters remaining in descriptor 1. .spb 3 .inl 0 .fif .inl 3 0 2 2 2 2 2 2 3 3 3 3 3 0______________________________________________3__4__5__6___7____9__0__1__2__3____5__ | | | | | | | | | | 02 PTR |0|TA |0 0 0|R|F|A|0 0 0| _|________________________________________________|__|____|______|__|__|__|______| 24 1 2 3 1 1 1 3 .inl 0 .ifi fig "DU Pointers and Lengths Format, Word 4" .spb Legend: .spb .inl 10 .fin .unl 10 D2 PTR Address of the last double word accessed by descriptor 2. Bits 17-23 (bit address) valid only for initial access. .spb .unl 10 TA Alphanumeric type (bits 21-22) of descriptor 2. .spb .unl 10 R The last cycle performed must be repeated. This bit is _n_o_t reloaded by lpl. .spb .unl 10 F First time. Data in descriptor 2 is valid. .spb .unl 10 A Descriptor 2 is active. .inl 0 .fif .spb 3 .inl 3 0 1 1 3 _0______________________1__2______________________________________________5__ | | | |0 0 0 0 0 0 0 0 0 0 0 0| D2 RES | _|________________________|________________________________________________| 12 24 .inl 0 .ifi fig "DU Pointers and Lengths Format, Word 5" .fif .spb Legend: .spb D2 RES The count of characters remaining in descriptor 2. .spb 3 .inl 3 0 2 2 2 2 2 2 3 3 3 3 3 _0______________________________________________3__4__5__6__7____9__0__1__2__3____5__ | | | | | | | | | | D3 PTR |0|TA |0 0 0|R|F|A| JMP | _|________________________________________________|__|____|______|__|__|__|______| 24 1 2 3 1 1 1 3 .inl 0 .ifi fig "DU Pointers and Lengths Format, Word 6" Legend: .spb .fin .inl 10 .unl 10 D3 PTR Address of the last double word accessed by descriptor 3. Bits 17-23 (bit address) valid only for initial access. .spb .unl 10 TA Alphanumeric type (bits 21-22) of descriptor 3. .spb .unl 10 R The last cycle performed must be repeated. This bit is _n_o_t reloaded by lpl. .spb .unl 10 F First time. Data in descriptor 3 is valid. .spb .unl 10 A Descriptor 3 is active. .spb .unl 10 JMP Number of words to skip to find the next instruction following this multiword instruction. .inl 0 .fif .spb 3 .inl 3 0 1 1 3 _0______________________1__2______________________________________________5__ | | | |0 0 0 0 0 0 0 0 0 0 0 0| D3 RES | _|________________________|________________________________________________| 12 24 .inl 0 .ifi fig "DU Pointers and Lengths Format, Word 7" .spb Legend: .spb D3 RES The count of characters remaining in descriptor 3. .ifi l1h "Processor History Register Formats" .fin .cbn Each of the major units of the processor has a set of history registers to store fields and flags from the most recent execution cycles from that unit. These registers are stored using the scpr instruction. The L68 and DPS Processors have 4 sets of 16 history registers. There is one for each major unit which are: The Control Unit (CU), the Operations Unit (OU), the Decimal Unit (DU) and the Appending Unit (APU). The DPS 8M Processor has 3 sets of 64 history registers. There is one set for the CU, one set for the APU and one set which combines history of OU and DU. .spf 2 Because the history registers for the L68 (and DPS) and the DPS 8M are different in number and contents, they are described separately. The following section describes the L68 (and DPS) history registers first followed by a description of the DPS 8M history registers. .cbn .ifi l2h "L68 CU History Register Format" .cbf The control unit history registers (CU-HR) show the conditions in the CPU .cbf control unit for the last 16 CU cycles. Data is entered into the CU history registers at the end of each CU cycle. The last entry shown in a dump of the history registers is the last entry made. True multicycle instructions (such as lpri, lreg, rcu, etc.) will have an entry for each of their cycles. .spb 2 .srv draft "L68 CU HISTORY REG FORMAT" .fif PL/I Declaration (history_regs.incl.pl1) .spb dcl 1 cuhr based(cuhrp) aligned, /* Even word */ (2 pia bit(1), 2 poa bit(1), 2 riw bit(1), 2 siw bit(1), 2 pot bit(1), 2 pon bit(1), 2 raw bit(1), 2 saw bit(1), 2 trgo bit(1), .cbn ___ 2 xde bit(1), .cbf 2 xdo bit(1), 2 ic bit(1), 2 rpts bit(1), 2 wi bit(1), .cbn __ 2 ar bit(1), ____ 2 nxip bit(1), ___ 2 nflt bit(1), __ 2 np bit(1), .cbf 2 inst bit(18), 2 addr bit(18), /* Odd word */ 2 pcmd bit(5), 2 psl bit(4), 2 xec_int bit(1), 2 ins_fetch bit(1), 2 cus bit(1), 2 ous bit(1), 2 cul bit(1), 2 oul bit(1), 2 dir bit(1), 2 npcb bit(1), 2 pib bit(1)) unaligned; .spb 2 Even Word: .inl 3 .spb 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 2 2 3 3 _0__1__2__3__4__5__6__7__8__9__0__1__2__3__4__5__6__7__8____________________8__9__0__________5__ | | | | | | | | | | | | | | | | | | | | | | | |a|b|c|d|e|f|g|h|i|j|k|l|m|n|o|p|q|r| OPCODE |I|P| TAG | _|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|____________________|__|__|____________| 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 10 1 1 6 .spb 2 .unl 3 Odd Word: .spb 0 1 1 2 2 2 2 3 3 3 _0__________________________________7__8________2__3______6__7____________3__4__5__ | | | | | | | | | | | | | | ADDRESS | CMD | SEL |s|t|u|v|w|x|y|z|*| _|____________________________________|__________|________|__|__|__|__|__|__|__|__|__| 18 5 4 1 1 1 1 1 1 1 1 1 .inl 0 .cbn .ifi fig "L68 CU History Register Format" .cbf .spf Legend: .spb M__a_s_k K__e_y F__i_e_l_d M__e_a_n_i_n_g .spb .inl 30 .unl 30 400000 a PIA (cuhr.pia) preparing instruction address. .unl 30 200000 b POA (cuhr.poa) preparing operand address. .unl 30 100000 c RIW (cuhr.riw) requesting indirect word. .unl 30 040000 d SIW (cuhr.siw) restoring indirect word. .unl 30 020000 e POT (cuhr.pot) preparing operand tally. .spb .inl 30 .unl 30 010000 f PON (cuhr.pon) preparing operand no tally. .unl 30 004000 g RAW (cuhr.raw) requesting read-alter-rewrite word. .unl 30 002000 h SAW (cuhr.saw) restoring read-alter-rewrite word. .unl 30 001000 i TRGO (cuhr.trgo) transfer GO (conditions met). .unl 30 000400 j XDE (cuhr.xde) executing xed from even ICT. .spb .unl 30 000200 k XDO (cuhr.xdo) executing xed from odd ICT. .unl 30 000100 l IC (cuhr.ic) executing odd instruction of the pair. .unl 30 000040 m RPTS (cuhr.rpts) executing a repeat operation. .unl 30 000020 n WI (cuhr.wi) waiting for instruction fetch. .unl 30 000010 o AR F/E (cuhr.ar) 1 = Address register has valid data. .spb .unl 10 ___ .unl 30 000004 p XIP (cuhr.nxip) NOT preparing XIP address. .unl 10 ___ .unl 30 000002 q FLT (cuhr.nflt) NOT preparing fault address. .unl 10 ____ .unl 30 000001 r BASE (cuhr.np) NOT slave (BAR) mode. .unl 30 777400 OPCODE (cuhr.inst, bits 1-10) current operation code. .unl 30 .fin 000200 I (cuhr.inst, bit 11) interrupt inhibit bit as in Figure 1-41. .spb .unl 30 000100 P (cuhr.inst, bit 12) pointer register flag as in Figure 1-41. .unl 30 000077 TAG (cuhr.inst, bits 13-16) current address modifier as in Figure 1-41. This modifier is replaced by the contents of the TAG fields of indirect words as they are fetched during indirect chains. .unl 30 777777 ADDRESS (cuhr.addr) value of the current computed address. .unl 30 760000 CMD (cuhr.pcmd) modulo 2 SCU command. .unl 30 017000 SEL (cuhr.psl) port select bits. (Invalid for CP6090 and CP6100 unless ports A through D are selected.) .spb .unl 30 000400 s XEC-INT (cuhr.xec_int) an interrupt is present. .unl 30 000200 t INS-FETCH (cuhr.inst_fetch) performing an instruction fetch. .unl 30 000100 u CU-STORE (cuhr.cus) CU store cycle. .unl 30 000040 v OU-STORE (cuhr.ous) OU store cycle. .unl 30 000020 w CU-LOAD (cuhr.cul) CU load cycle. .spb .unl 30 000010 x OU-LOAD (cuhr.oul) OU load cycle. .unl 30 000004 y DIRECT (cuhr.dir) direct cycle. .unl 10 _______ .unl 30 000002 z PC-BUSY (cuhr.npcb) port control logic not busy. .unl 30 000001 * BUSY (cuhr.pib) port interface busy. .inl 0 .srv draft "L68 OU HISTORY REG FORMAT" .cbn .ifi l2h "L68 OU History Register Format" .cbf The operations unit history registers (OU-HR) show the conditions in the CPU operations unit for the last 16 OU cycles. Data is entered at the end of each OU operation or at the occurrence of a fault. The last entry shown in a dump of the OU history registers is the last entry made. The OU and CU history registers run asynchronously. .spb 2 .fif PL/I Declaration (history_regs.incl.pl1) .spb dcl 1 ouhr based(ouhrp) aligned, /* Even word */ (2 nopc bit(9), 2 itw bit(1), 2 ntg bit(3), 2 cmod bit(1), 2 dir bit(1), 2 efad bit(2), 2 pad0 bit(1), 2 rp bit(9), 2 opbf bit(1), 2 frpf bit(1), 2 srf bit(1), 2 fgin bit(1), 2 fgos bit(1), 2 fgd1 bit(1), 2 fgd2 bit(1), 2 fgoe bit(1), 2 fgoa bit(1), 2 fgom bit(1), /* Odd word */ 2 fgon bit(1), 2 fgof bit(1), 2 fstr bit(1), 2 dn bit(1), 2 an bit(1), 2 qn bit(1), 2 x0n bit(1), 2 x1n bit(1), 2 x2n bit(1), 2 x3n bit(1), 2 x4n bit(1), 2 x5n bit(1), 2 x6n bit(1), 2 x7n bit(1), 2 pad1 bit(3), 2 ict bit(18)) unaligned; .spb 2 Even Word: .inl 3 .spb 0 0 0 1 1 1 1 1 1 1 1 1 2 2 3 _0________________8__9__0__1__2__3__4__5__6__7__8________________6__7________________5__ | RP REG | | | | | | | | | | | | |---------------------------------|0| RS REG |g|h|i|j|k|l|m|n|o| _|_____O_P__C_O_D_E_______|_a_|_b_|_c_|_d_|_e_|_f_|E_A_C__|__|__________________|__|__|__|__|__|__|__|__|__| 9 1 1 1 1 1 1 2 1 9 1 1 1 1 1 1 1 1 1 .spb 2 .unl 3 Odd Word: .spb 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 3 _0__1__2__3__4__5__6__7__8__9__0__1__2__3__4__5____7__8__________________________________5__ | | | | | |_|_|_|_|_|_|_|_|_|_| | | |p|q|r|s|t|A|Q|0|1|2|3|4|5|6|7|0 0 0| ICT TRACKER | _|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|______|____________________________________| 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3 18 .inl 0 .cbn .ifi fig "L68 OU History Register Format" .cbf .spb Legend: .spb M__a_s_k K__e_y F__i_e_l_d M__e_a_n_i_n_g .spb .fin .inl 30 .unl 30 777776 RP REG primary OU operation register. RP REG receives the instruction operation code and other data from the CU during the CU instruction cycle while the OU may be be busy with a prior operation. RP REG is further substructured as described below. .unl 30 777000 OP CODE (ouhr.nopc) the nine MSB of the operation code for the instruction. Basic (non-EIS) operations do not involve bit 27; hence, the 9-bit field is sufficient to define the operation code. .unl 30 000400 a 9 CHAR (ouhr.itw) character size for IT mods. .brf 0 = 6-bit character. .brf 1 = 9-bit character. .unl 30 000340 b,c,d TAG1,2,3 (ouhr.ntg) three LSB of the modifier of the instruction. This field may contain a character position for an IT character modifier. .unl 30 000020 e CR FLG (ouhr.cmod) character operation flag. .spb .unl 30 000010 f DR FLG (ouhr.dir) direct operation flag. .unl 30 000006 EAC (ouhr.efad) effective address counter for lreg/sreg instructions. .unl 30 777000 RS REG (ouhr.rp) secondary OU operation register. OP CODE is moved from RP REG to RS REG during the operand fetch and is held until completion of the instruction. .unl 30 000400 g RB1 FULL (ouhr.opbf) OP CODE buffer full. .unl 30 000200 h RP FULL (ouhr.frpf) RP REG full. .spb .unl 30 000100 i RS FULL (ouhr.srf) RS REG full. .unl 30 000040 j GIN (ouhr.fgin) first cycle for all OU operations. .unl 30 000020 k GOS (ouhr.fgos) second cycle for OU multi-ops. .unl 30 000010 l GD1 (ouhr.fgd1) first divide cycle. .unl 30 000004 m GD2 (ouhr.fgd2) second divide cycle. .spb .unl 30 000002 n GOE (ouhr.fgoe) exponent compare cycle. .unl 30 000001 o GOA (ouhr.fgoa) mantissa alignment cycle. .unl 30 400000 p GOM (ouhr.fgom) general OU cycle. .unl 30 200000 q GON (ouhr.fgon) normalize cycle. .unl 30 100000 r GOF (ouhr.fgof) final OU cycle. .spb .unl 30 040000 s STR OP (ouhr.fstr) OU store data available. .brp .pdl 104 .unl 30 M__a_s_k K__e_y F__i_e_l_d M__e_a_n_i_n_g .unl 10 _____ .unl 30 020000 t DA-AV (ouhr.dn) data not available. .unl 20 _ _____ .unl 30 010000 A A-REG (ouhr.an) A register not in use. .spb .inl 30 .unl 20 _ _____ .unl 30 004000 Q Q-REG (ouhr.qn) Q register not in use. .unl 20 _ _____ .unl 30 002000 0 X0-RG (ouhr.x0n) X0 not in use. .spb .unl 20 _ _____ .unl 30 001000 1 X1-RG (ouhr.x1n) X1 not in use. .unl 20 _ _____ .unl 30 000400 2 X2-RG (ouhr.x2n) X2 not in use. .unl 20 _ _____ .unl 30 000200 3 X3-RG (ouhr.x3n) X3 not in use. .unl 20 _ _____ .unl 30 000100 4 X4-RG (ouhr.x4n) X4 not in use. .unl 20 _ _____ .unl 30 000040 5 X5-RG (ouhr.x5n) X5 not in use. .spb .unl 20 _ _____ .unl 30 000020 6 X6-RG (ouhr.x6n) X6 not in use. .unl 20 _ _____ .unl 30 000010 7 X7-RG (ouhr.x7n) X7 not in use. .spb .unl 30 777777 ICT TRACKER (ouhr.ict) the CU ICT value carried as the current offset to the PSR. Since the CU and OU run asynchronously and overlap is usually enabled, the value of ICT TRACKER may not be the address of the OU instruction currently being executed. .inl 0 .srv draft "L68 DU HISTORY REG FORMAT" .cbn .ifi l2h "L68 DU History Register Format" .cbf The decimal unit history registers (DU-HR) show the conditions in the DU for the last 16 C_U_ cycles (since the DU and CU run synchronously). The format is specified as a collection of 72 separate bits since fields are not defined. A minus sign (-) preceding the flag name indicates that the complement of the flag is shown. Unused bits are stored as binary "1"s. .spb PL/I Declaration (history_regs.incl.pl1) .fif .spb dcl 1 duhr based(duhrp) aligned, (2 pol bit(1), 2 pop bit(1), 2 ndesc bit(1), 2 seladr bit(1), 2 dlendr bit(1), 2 dfrst bit(1), 2 exr bit(1), 2 ldfrst bit(1), 2 dulea bit(1), 2 dusea bit(1), 2 redo bit(1), 2 wcws bit(1), 2 exh bit(1), 2 eseq bit(1), 2 einst bit(1), 2 durw bit(1), 2 pradb0 bit(1), 2 pradb1 bit(1), 2 aidesc bit(3), 2 wrd bit(1), 2 nine bit(1), 2 six bit(1), 2 four bit(1), 2 bit bit(1), 2 du_pad1 bit(4), 2 samplint bit(1), 2 sfcsq bit(1), 2 adjlen bit(1), 2 intind bit(1), 2 inhibstc1 bit(1), 2 du_pad2 bit(1), 2 duidl bit(1), 2 dcldgt bit(3), 2 nopl1 bit(1), 2 nopgl1 bit(1), 2 nopl2 bit(1), 2 nopgl2 bit(1), 2 aoplg1 bit(1), 2 aoplg2 bit(1), 2 lrwrg1 bit(1), 2 lrwrg2 bit(1), 2 dataav bit(1), 2 rw1rl bit(1), 2 numstg bit(1), 2 anstg bit(1), 2 opav bit(1), 2 endseq bit(1), 2 len128 bit(1), 2 charop bit(1), 2 anpk bit(1), 2 exmop bit(1), 2 blnk bit(1), 2 du_pad3 bit(1), 2 bde bit(1), 2 dbe bit(1), 2 shft bit(1), 2 flt bit(1), 2 rnd bit(1), 2 addsub bit(1), 2 multdiv bit(1), 2 expon bit(1), 2 du_pad4 bit(4))unaligned; .ifi fig "?????" .inl 40 .fin .spb 2 .unl 40 M__a_s_k B__i_t F__i_e_l_d M__e_a_n_i_n_g .unl 40 .spb 400000 0 - FPOL (duhr.pol) preparing operand length. .unl 40 200000 1 - FPOP (duhr.pop) preparing operand pointer. .unl 40 100000 2 - NEED-DESC (duhr.ndesc) need descriptor. .spb .unl 40 040000 3 - SEL-ADR (duhr.seladr) select address register. .unl 40 020000 4 - DLEN=DIRECT (duhr.dlendr) length equals direct. .unl 40 010000 5 - DFRST (duhr.dfrst) descriptor being processed for first time. .spb .unl 40 004000 6 - FEXR (duhr.exr) extended register modification. .unl 40 002000 7 - DLAST-FRST (duhr.ldfrst) last cycle of DFRST. .unl 40 001000 8 - DDU-LDEA (duhr.dulea) DU load. .spb .unl 40 000400 9 - DDU-STAE (duhr.dusea) DU store. .unl 40 000200 10 - DREDO (duhr.redo) redo operation without pointer and length update. .unl 40 000100 11 - DLVLE (complemented) .unl 40 _____ .brf .unl 40 010000 x BTDS binary to decimal gate (complemented) .unl 40 ____ .brf .unl 40 004000 y SP15 align cycles (complemented) .unl 40 _____ .brf .unl 40 002000 z FSWEQ single word sequence flag (complemeneted) .unl 40 ____ .brf .unl 40 001000 A FGCH character cycle (complemeneted) .unl 40 000400 B DFRST processing descriptor for first time .unl 40 000200 C EXH exhaust .unl 40 _____ .brf .unl 40 000010 D FGADO add cycle (complemented) .unl 40 000040 E INTRPTO interrupted .unl 40 000020 F GLDP2 load DP2 .unl 40 000010 G GEMC multiply gate C .unl 40 000004 H GBDA bin to dec gate A .unl 40 000002 I GSP5 final align cycle .unl 40 .spb >>>>>> ICT instruction counter .spb .unl 40 >>>000 RS OU op-code register (RSO-8) .unl 40 000776 IR the indicator reg .unl 40 000400 J ZERO zero indicator .unl 40 000200 K NEG negative indicator .unl 40 000100 L CARRY carry indicator .unl 40 000040 M OVFL overflow indicator .unl 40 000020 N EOVFL exponent overflow indicator .unl 40 000010 O EVFL Exponent underflow indicator .unl 40 000004 P OFLM Overflow mask indicator .unl 40 000002 Q HEX hex made indicator .unl 40 000001 R DTRGO transfer G0 .inl 0 .ifi l1h "DPS 8M Appending Unit (APU) History Registers" .ifi l1toc "DPS 8M Appending Unit (APU) History Registers" .inl 5 F__o_r_m_a_t: - 72 bits each .inl 0 .spb Even word of Y-pair as stored by Store Central Processor register (scpr) .brf Tag = 00 .spb .fif 0 1 1 1 1 1 1 2 2 2 2 2 2 2 2 3 3 3 3 0 4 5 6 7 8 9 0 1 2 3 4 5 6 9 0 1 4 5 -------------------------------------------------------------------- | | | | | | | | | | | | | | | | 0 | ESN | a |b|c|d|e|f|g|h|i|j| SDWAML |k| PTWAML |l| -------------------------------------------------------------------- 15 2 1 1 1 1 1 1 1 1 1 1 4 1 4 1 .spb .fin .inl 0 Odd word of Y-pair as stored by Store Central Processor Register (scpr), .brf Tag = 00 .spb .fif 3 5 6 6 6 6 6 6 6 6 6 7 7 6 9 0 2 3 4 5 6 7 8 9 0 1 --------------------------------------------------------------------- | | | | | | | | 1 | ADD | TSR |a 0 0|b|c 0 0|d|0| |____________________________________________________________________ 24 3 1 2 1 1 2 1 1 .fin .ifi fig "DPS 8 Appending Unit (APU) History Register Format" .spb D__e_s_c_r_i_p_t_i_o_n: .spb Sixty-four combinations of flags and regisers from the appending unit. The 64 registers are handled as a rotating queue controlled by the appending unit history register counter. The counter is always set to the number of oldest entry and advances by one for each history register reference (data entry or Store Central Processor Register (scpr) instruction). .spb 2 F__u_n_c_t_i_o_n: .spb An appending unit history register entry shows the conditions in the appending unit at the end of an address preparation cycle in appending mode. The 64 registers will hold the conditions for the last 64 such address preparation cycles. Entries are made according to controls set in the mode register. (See mode register earlier in this section.) .spb .inl 0 Legend: .spb .fif M__a_s_k K__e_y F__l_a_g N__a_m_e M__e_a_n_i_n_g .spb 777770 ESN Effective segment number (Tpr.TSR) 000006 a BSY Data source for ESN .spb 00 - from PPR.PSR 01 = from PRn_.SNR 10 - from TPR.TSR 11 = not used .spb 000001 b FDSPTW Descriptor segment PTW fetch 400000 c MDSPTW Descriptor segment PTW modification 200000 d FSDWP SDW fectch from paged descriptor segment 100000 e FPTW PTW fetch 040000 f FPTW2 PTW+1 fetch (prepaging for certain EIS infromation) 020000 g MPTW PTW modification 100000 h FANP Final address fetch from nonpaged segment 040000 i FAP Final address fetch from paged segment 002000 j SDWAMM SDWAM match occurred 001700 SDWAML SDWAML level if SDWAMM=1; SDWAM level number in error if FAULT REGISTER bit 48 is set. 000040 k PTWAMM PTWAM match occured 000036 PTWAML PTWAM level is PTWAMM=1; PTWAM level number in FAULT REGISTER bit 47 is sel. 000001 l FLT Access violation or directed fault on this cycle 77777777 ADD 24-bit absolute main memory address from this cycle 007000 TRR Ring number from this cycle (TPR.TRR) 000400 CA Segment in encachaeble 000020 Multiple match error is SDWAM 000002 FHLD An access violation or directed fault is waiting .cbf .inl 0 .srv draft "FAULT DATA" .ifi l1h "Fault Data" The processor has 32 active faults in Multics mode and 16 active faults in GCOS mode. .ifi l2h "Processor Faults" The fault vector is located at 100(8) and the fault pair for each fault is at 2_*_O_C_T_ relative to 100(8). .spb .fif .ifi tab "Processor Fault Numbers" .spb 2 .inl 5 F/I ADDR O__c_t D__e_c _i_n_S_C_U___d_a_t_a N__a_m_e M__n_e_m_o_n_i_c P__r_i_o_r_i_t_y G__r_o_u_p M__o_d_e .spb 0 0 01 Shutdown sdf 27 VII M/G 1 1 03 Store str 10 IV M/G 2 2 05 Master Mode Entry 1 mme1 11 V M/G 3 3 07 Fault Tag 1 ftg1 17 V M/G .spb 4 4 11 Timer Runout tro 26 VI M/G 5 5 13 Command cmd 9 IV M/G 6 6 15 Derail drl 15 V M/G 7 7 17 Lockup luf 5 IV M/G .spb 10 8 21 Connect con 25 VII M/G 11 9 23 Parity par 8 IV M/G 12 10 25 Illegal Procedure ipr 16 V M/G 13 11 27 Op Not Complete onc 4 II M/G .spb 14 12 31 Startup suf 1 I M/G 15 13 33 Overflow ofl 7 III M/G 16 14 35 Divide Check dvck 6 III M/G 17 15 37 Execute exc 2 I M/G .spb 20 16 41 Directed Fault 0 dft0 20 VI M 21 17 43 Directed Fault 1 dft1 21 VI M 22 18 45 Directed Fault 2 dft2 22 VI M 23 19 47 Directed Fault 3 dft3 23 VI M .spb 24 20 51 Access Violation acv 24 VI M 25 21 53 Master Mode Entry 2 mme2 12 V M 26 22 55 Master Mode Entry 3 mme3 13 V M 27 23 57 Master Mode Entry 4 mme4 14 V M .spb 30 24 61 Fault Tag 2 ftg2 18 V M 31 25 63 Fault Tag 3 ftg3 19 V M 32 26 65 Unassigned 33 27 67 Unassigned .spb 34 28 71 Unassigned 35 29 73 Unassigned 36 30 75 Unassigned 37 31 77 Trouble trb 3 II M .fin .inl 0 .ifi l2h "Fault Register Format" The CPU fault register contains the conditions in the CPU for several of the hardware faults. The register is stored and cleared by the scpr (tag 01) command. The data is stored into the word pair at location Y. .cbn For a L68 Processor, the contents of Y+1 are cleared. For DPS 8 Processor, The odd word contains information relevant to the 8K cache. This second word is known as the extended format register. .cbf .spb .cbd .spb .cbn .fif F__a_u_l_t R__e_g_i_s_t_e_r (F_R_)_ .spb Evevn word of Y-pair as stored by Store Central Processor (scpr), TAG = 01 .spb .fif 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 2 2 2 2 2 3 3 3 3 3 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 9 0 3 4 7 8 1 2 3 4 5 --------------------------------------------------------------------------- 0 |a|b|c|d|e|f|g|h|i|j|k|l|m|n|o|0| IAA | IAB | IAC | IAD |p|q|r|s| --------------------------------------------------------------------------- .spb 2 .fin DP word for the DPS M CPU Fault Register for L68 and DPS Processors, this word would be all zeros. .spb .fif 3 3 3 3 4 4 4 4 4 4 4 4 4 4 7 6 7 8 9 0 1 2 3 4 5 6 7 8 9 1 ___________________________________________________________________________ 1 |t|u|v|w|x|y|z|a|b|c|d|e|f| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ___________________________________________________________________________ .fin .ifi fig "Fault Register (FR) Format" .spb D__e_s_c_r_i_p_t_i_o_n: .spb A combination of flags and registers all located in the control unit. The register is stored _a_n_d cleared by the Store Central Processor Register (scpr), Tag = 01, instruction. Note that the data is stored into _w_o_r_d _p_a_i_r at location Y. the fault register cannot be loaded. .spb F__u_n_c_t_i_o_n: .spb The fault register contains the conditions in the processor for several of the hardware faults and on the DPS 8M CPU, cache directory buffer overflows. Data is strobed into the faults register during a fault or buffer overflow sequence. Once a bit or field in the fault register is set, it remains set until the register is stored and cleared. The data is not overwritten during subsequent events. .spb The functions of the constituent flags and registers are: .spb .fif F__l_a_g _o_r M__a_s_k K__e_y R__e_g_i_s_t_e_r F__a_u_l_t F__u_n_c_t_i_o_n .spb 400000 a ILL OP IPR An illegal operation code has been deleted. 200000 b ILL MOD IPR An illegal address modifier has been deleeted. 100000 c ILL SLV IPR An illegal BAR mode has been encountered. 040000 d ILL PROC IPR An illegal procedure other than the three above has been encountered. 020000 e NEM ONC A nonexistent main memory address has been requested. 010000 f OOB STR A BAR mode boundary violation has occurred. 004000 g ILL DIG IPR An illegal decimal digit or sign has been detected by the decimal unit. 002000 h PROC PARU PAR A parity error has been detected in the upper 36 bits of data. 001000 i PROC PARL PAR A parity error was detected in the lower 36 bits of data. 000400 j $CON A CON A $CONNECT signal has been received through port A. 000200 k $CON B CON A $CONNECT signal has been received through port B. 000100 l $CON C CON A $CONNECT signal has been received through port C. 000400 m $CON D CON A $CONNECT signal has been received through port D. 000200 n DA ERR1 ONC Operation not complete. Processor/system controller interface sequence error 1 has been detached. ($DATA-AVAIL received with no prior $INTERRUPT sent.) 000010 o DA ERR2 ONC Operation not complete. Processor/system controller interface sequence error 2 has been detached. (Multiple $DATA-AVAIL received or $DATA-AVAIL received out of order.) 000003U IAA Coded illegal action, 600000L port A. (See Table 3-2) 170000 IAB Coded illegal action, port B. (See Table 3-2) 007400 IAC Coded illegal action, port C. (See Table 3-2) 000360 IAD Coded illegal action, port D. (See Table 3-2) 000010 p CPAR DIR PAR A parity error has been detached in the cache memory. 000004 q CPAR STR STR A data parity has been detached in the cache memory. 000002 r CPAR IA STR An illegal action has been received from a system controller during a store operation with cache memory enabled. This implies that the data is correct in cache memory and incorrect in main memory. 000001 s CPAR BLK PAR A cache memory parity error has occurred during a cache memory data block load. .spb .inl 0 ------------------------------------------------------------------ | Illegal | | | | | Action | | | | | Code | Priority | Fault |Reason | ------------------------------------------------------------------ | 00 | -- | | No illegal action | | 01 | -- | Command | Unassinged | | 02 | 05 | Store | Nonexistent address | | 03 | 01 | Command | Stop on condition | | 04 | -- | Command | Unassigned | | 05 | 12 | Parity | Data parity, store unit | | | | | to system controller | | 06 | 11 | Parity | Data parity, in store unit | | 07 | 10 | Parity | Data parity in store unit and | | | | | store unit to system | | | | | controller | | 10 | 04 | Command | Not control (a) (Not relevant | | | | | to later model | | 11 | 13 | Command | Port not enabled | | | | | system controllers) | | 12 | 03 | Command | Illegal command | | 13 | 07 | Store | Store unit not ready | | 14 | 02 | Parity | Zone-address-command parity, | | | | | processor to system | | | | | controller to store unit | | 15 | 06 | Parity | Data parity, processor to | | | | | system controller | | 16 | 08 | Parity | Zone-address-command parity, | | | | | processor to system | | | | | controller to store unit | | 17 | 09 | Parity | Data parity, system controller | ------------------------------------------------------------------ .ifi fig "System Controller Illegal Action Codes"Flag or .spb F__l_a_g _o_r M__a_s_k K__e_y R__e_g_i_s_t_e_r F__a_u_l_t F__u_n_c_t_i_o_n .spb Cache Duplicate Directory WNO Buffer Overflow- 400000 T NONE Port A 200000 U NONE Port B 100000 V NONE Port C 040000 W NONE Port D 020000 X NONE Cache Primary Directory WNO Buffer Overflow- 010000 Y PAR Write Notify (WNO) Parity Error on Port A, B, C, or D. Cache Duplicate Directory Parity Error- 004000 Z PAR Level 0 002000 A PAR Level 1 001000 B PAR Level 2 000400 C PAR Level 3 000200 D PAR Cache Duplicate Directory Multiple Match 000100 E PAR Page Table Word Associative Memory Directory or Entry Parity Error; or Multiple Match 00040 F PAR Segment Descriptor Word Associative Memory Directory or Entry Parity Error; or Multiple Match .fin .cbf .inl 0 .ifi l1h "Miscellaneous Register Formats" .srv draft "SCU DATA FORMAT" .ifi l2h "Store Control Unit Data Format" .fin The following is the format of the eight words stored by the scu instruction (the SCU data). The fields marked with (*) are _n_o_t restored by the restore control unit (rcu) instruction. .spb 2 .fif PL/I Declaration (mc.incl.pl1) .spb 2 dcl 1 scu based (scup) aligned, /* Word 0 */ (2 ppr, 3 prr bit(3), 3 psr bit(15), 3 p bit(1), 2 apu, 3 xsf bit(1), 3 sdwm bit(1), 3 sd_on bit(1), 3 ptwm bit(1), 3 pt_on bit(1), 3 pi_ap bit(1), 3 dsptw bit(1), 3 sdwnp bit(1), 3 sdwp bit(1), 3 ptw bit(1), 3 ptw2 bit(1), 3 fap bit(1), 3 fanp bit(1), 3 fabs bit(1), 2 fault_cntr bit(3), /* continued below */ 2 fd, /* Word 1 */ 3 iro bit(1), 3 oeb bit(1), 3 e_off bit(1), 3 orb bit(1), 3 r_off bit(1), 3 owb bit(1), 3 w_off bit(1), 3 no_ga bit(1), 3 ocb bit(1), 3 ocall bit(1), 3 boc bit(1), 3 inret bit(1), 3 crt bit(1), 3 ralr bit(1), 3 am_er bit(1), 3 oosb bit(1), 3 paru bit(1), 3 parl bit(1), 3 onc_1 bit(1), 3 onc_2 bit(1), 2 port_stat, 3 ial bit(4), 3 iac bit(3), 3 con_chan bit(3), 2 fi_num bit(5), 2 fi_flag bit(1), .spb 2 .inl 3 0 0 0 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3 3 3 _0____2__3____________________________7__8__9__0__1__2__3__4__5__6__7__8__9__0__1__2______5__ | | | | | | | | | | | | | | | | | | | | PRR | PSR |a|b|c|d|e|f|g|h|i|j|k|l|m|n|o| FCT | _|______|______________________________|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|______| 3 15 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3 .inl 0 .ifi fig "SCU Data Format, Word 0" .spb .fin Legend: .spb .inl 30 .unl 30 M__a_s_k K__e_y F__i_e_l_d M__e_a_n_i_n_g .unl 30 .spb 700000 PRR (scu.ppr.prr) procedure ring register. .unl 30 077777 PSR (scu.ppr.psr) procedure segment register. .unl 30 .cbn 400000 a P (scu.ppr.p) privileged mode flag. .cbf .unl 30 200000 b XSF (scu.apu.xsf) external segment flag. .unl 30 100000 c * SDWM (scu.apu.sdwm) match on SDWAM. .spb .unl 30 040000 d * SD-ON (scu.apu.sd_on) SDWAM enabled. .unl 30 020000 e * PTWM (scu.apu.ptwm) match on PTWAM. .unl 30 010000 f * PT-ON (scu.apu.pt_on) PTWAM enabled. .unl 30 004000 g * PI-AP (scu.apu.pi_ap) instruction fetch append cycle. .unl 30 002000 h * DSPTW (scu.apu.dsptw) fetch descriptor segment PTW. .spb .unl 30 001000 i * SDWNP (scu.apu.sdwnp) fetch SDW, unpaged. .unl 30 000400 j * SDWP (scu.apu.sdwp) fetch SDW, paged. .unl 30 000200 k * PTW (scu.apu.ptw) fetch PTW. .unl 30 000100 l * PTW2 (scu.apu.ptw2) fetch prepage PTW. .unl 30 000040 m * FAP (scu.apu.fap) fetch final address, paged. .spb .unl 30 000020 n * FANP (scu.apu.fanp) fetch final address, unpaged. .unl 30 000010 o * FABS (scu.apu.fabs) fetch final address, absolute. .unl 30 000007 FCT (scu.fault_cntr) number of unsuccessful attempts to execute the instruction. .inl 0 .fif .spb .inl 0 .fin (Also see declaration for scux in mc.incl.pl1) .spb 2e .fif .inl 3 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 3 3 3 _0__1__2__3__4__5__6__7__8__9__0__1__2__3__4__5__6__7__8__9__0______3__4____6__7____9__0________4__5__ | | | | | | | | | | | | | | | | | | | | | | | | | | |a|b|c|d|e|f|g|h|i|j|k|l|m|n|o|p|q|r|s|t| IA |IACHN|CNCHN| F/I ADDR|u| _|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|________|______|______|__________|__| 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 4 3 3 5 1 .inl 0 .fin .ifi fig "SCU Data Format, Word 1" .spb Legend: .spb .inl 0 .fin M__a_s_k K__e_y F__i_e_l_d _f_l_t__a_d_d_r M__e_a_n_i_n_g .inl 40 .unl 40 .spb 400000 a * IRO 51(acv) (scu.fd.iro) illegal ring order. .spb .unl 40 200000 b * OEB 51(acv) (scu.fd.oeb) out of execute bracket. .unl 30 * IOC 25(ipr) (scux.fd.ioc) illegal op code. .spb .unl 40 100000 c * E-OFF 51(acv) (scu.fd.e_off) execute bit is off. .unl 40 * IA+IM 25(ipr) (scux.fd.ia_am) invalid address or modifier. .spb .unl 40 040000 d * ORB 51(acv) (scu.fs.orb) out of read bracket. .unl 40 * ISP 25(ipr) (scux.fd.isp) invalid slave procedure. .spb .unl 40 020000 e * R-OFF 51(acv) (scu.fd.r_off) read bit is off. .unl 40 * IPR 25(ipr) (scux.fd.ipr) all other illegal procedure. .spb .unl 40 010000 f * OWB 51(acv) (scu.fd.owb) out of write bracket. .unl 40 * NEA 03(str) (scux.fd.nea) nonexistent address. .spb .unl 40 004000 g * W-OFF 51(acv) (scu.fd.w_off) write bit is off. .unl 40 * OOB 03(str) (scux.fd.oobb) out of bounds. .spb .unl 40 002000 h * NO GA 51(acv) (scu.fd.no_ga) not a gate, or out-of-call limiter. .spb .unl 40 001000 i * OCB 51(acv) (scu.fd.ocb) out of call bracket. .spb .unl 40 000400 j * OCALL 51(acv) (scu.fd.ocall) outward call. .spb .unl 40 000200 k * BOC 51(acv) (scu.fd.boc) bad outward call. .spb .unl 40 000100 l * INRET 51(acv) (scu.fd.inret) inward return. .unl 40 000040 m * CRT 51(acv) (scu.fd.crt) cross ring transfer. .spb .unl 40 000020 n * RALR 51(acv) (scu.fd.ralr) ring alarm. .spb .unl 40 000010 o * AM-ER 51(acv) (scu.fd.am_er) associative memory error. .spb .unl 40 000004 p * OOSB 51(acv) (scu.fd.oosb) out of segment bounds. .spb .unl 40 000002 q * PARU 23(par) (scu.fd.paru) processor parity upper. .unl 40 000001 r * PARL 23(par) (scu.fd.parl) processor parity lower. .spb .unl 40 400000 s * ONC1 27(onc) (scu.fd.onc_1) SC/CPU sequence error #1. .spb .unl 40 200000 t * ONC2 27(onc) (scu.fd.onc_2) SC/CPU sequence error #2. .spb .unl 40 170000 * IA any IA (scu.port_stat.ial) SC illegal action lines. .brf (see "SC Illegal Action Codes" in Section!II.) .spb .unl 40 007000 * IACHN any IA (scu.port_stat.iac) illegal action CPU port. .spb .unl 40 000700 * CNCHN 21(con) (scu.port_stat.con_chan) connect (CIOC) CPU port. .spb .unl 40 000076 * F/I ADDR any (scu.fi_num) modulo 2 fault/interrupt vector address. .spb .unl 40 000001 u * F/I any (scu.fi_flag) fault/interrupt bit. .inl +4 .unl 4 0 = interrupt caused the data to be stored. .unl 4 1 = fault caused the data to be stored. .spb 3 .inl 0 .fif 2 tpr, /* Word 2 */ 3 trr bit(3), 3 tsr bit(15), .cbn 2 sdw bit(4), 2 ptw bit(4), 2 pad2 bit(1), 2 cpu_no bit(3), .cbf 2 delta bit(6), /* continued below */ .spb 2 .cbn .inl 3 0 0 0 1 1 2 2 2 2 2 3 3 0 2 3 7 8 1 2 6 7 9 0 5 ------------------------------------------------------------ | TRR | TSR | <- o L68 o ->|0|CPU| DELTA | | | | SDW | PTW | | | ------------------------------------------------------------ 3 15 4 4 1 3 6 .cbf .inl 0 .ifi fig "SCU Data Format, Word 2" .fin .spb Legend: .spb TRR (scu.tpr.trr) temporary ring register. .spb TSR (scu.tpr.tsr) temporary segment register. .cbn .spb * SDW (scu.sdw) SDW associative memory level enabled (DPS 8 only) .spb * PTW (scu.ptw) PTW associative memory level enabled (DPS 8 only) .cbf .spb * CPU (scu.cpu_no) CPU number (from maintenance panel switches.) .spb DELTA (scu.delta) address increment for repeats. .fif .spb 2 2 word3 bit(18), /* Word 3 */ 2 tsr_stat, 3 tsna, 4 prn bit(3), 4 prv bit(1), 3 tsnb, 4 prn bit(3), 4 prv bit(1), 3 tsnc, 4 prn bit(3), 4 prv bit(1), 2 tpr_tbr bit(6), /* continued below */ .spb 2 .inl 3 0 1 1 2 2 2 2 2 3 3 _0__________________________________7__8______1__2______5__6______9__0__________5__ | | | | | | |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| TSNA | TSNB | TSNC | TEMP BIT | _|____________________________________|________|________|________|____________| 18 4 4 4 6 .fin .inl 0 .ifi fig "SCU Data Format, Word 3" .spb Legend: .spb .alb .inl 10 .unl 10 TSNA (scu.tsr_stat.tsna...) temporary pointer register number for non-multiword instruction operands _o_r temporary pointer register number for operand descriptor 1 of multiword instructions. .spb TSN(n)(0-2) pointer register number. .brf TSN(n)(3) 1 = TSN(n)(0-2) is valid. .spb .unl 10 TSNB (scu.tsr_stat.tsnb...) temporary pointer register number for operand descriptor 2 of multiword instructions. .spb .unl 10 TSNC (scu.tsr_stat.tsnc...) temporary pointer register number for operand descriptor 3 of multiword instructions. .spb .unl 10 TEMP BIT (scu.tpr_tbr) contents of BITNO field of current ITS, ITP, or (if an EIS decimal instruction) ADR pointer. .inl 0 .spb 3 .fif 2 ilc bit(18), /* Word 4 */ 2 ir, 3 zero bit(1), 3 neg bit(1), 3 carry bit(1), 3 ovfl bit(1), 3 eovf bit(1), 3 eufl bit(1), 3 oflm bit(1), 3 tro bit(1), 3 par bit(1), 3 parm bit(1), 3 bm bit(1), 3 tru bit(1), 3 mif bit(1), 3 abs bit(1), .cbn 3 hex bit(1), 3 pad bit(3), .spb 2 .inl 3 .fif 0 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3 3 3 _0__________________________________7__8__9__0__1__2__3__4__5__6__7__8__9__0__1__2______5__ | | | | | | | | | | | | | | | | | | | ICT |a|b|c|d|e|f|g|h|i|j|k|l|m|n|o|0 0 0| _|____________________________________|__|__|__|__|__|__|__|__|__|__|__|__|__|__|________| 18 1 1 1 1 1 1 1 1 1 1 1 1 1 1 4 .inl 0 .cbf .ifi fig "SCU Data Format, Word 4" .spb Legend: .spb .inl 30 .unl 30 M__a_s_k K__e_y F__i_e_l_d M__e_a_n_i_n_g .fin .unl 30 .spb 777777 ICT (scu.ilc) instruction counter. .unl 30 400000 a ZERO (scu.ir.zero) zero indicator. .unl 30 200000 b NEG (scu.ir.neg) negative indicator. .unl 30 100000 c CARY (scu.ir.carry) carry indicator. .unl 30 040000 d OVFL (scu.ir.ovfl) overflow indicator. .spb .unl 30 020000 e EOVF (scu.ir.eovf) exponent overflow indicator. .unl 30 010000 f EUFL (scu.ir.eufl) exponent underflow indicator. .unl 30 004000 g OFLM (scu.ir.oflm) overflow mask indicator. .unl 30 002000 h TRO (scu.ir.tro) tally runout indicator. .unl 30 001000 i PAR (scu.ir.par) parity error indicator. .spb .unl 30 000400 j PARM (scu.ir.parm) parity mask indicator. .unl 10 __ .unl 30 000200 k BM (scu.ir.bm) BAR mode indicator. .brf If bit is set, CPU is not in BAR (GCOS slave) mode. .unl 30 000100 l TRU (scu.ir.tru) EIS truncation indicator. .unl 30 000040 m MIF (scu.ir.mif) midinstruction fault interrupt (EIS). .unl 30 000020 n ABS (scu.ir.abs) absolute mode. .spb .cbn .unl 30 000010 o HEX (scu.ir.hex) Hex mode instruction (DPS 8M Processor only). .cbf .spb 3 .inl 0 .fif 2 ca bit(18), /* Word 5 */ 2 cu, 3 rf bit(1), 3 rpt bit(1), 3 rd bit(1), 3 rl bit(1), 3 pot bit(1), 3 pon bit(1), 3 xde bit(1), 3 xdo bit(1), 3 poa bit(1), 3 rfi bit(1), 3 its bit(1), 3 if bit(1), 2 tag bit(6)) unaligned, /* continued below */ .spb 2 .inl 3 .fif 0 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3 _0__________________________________7__8__9__0__1__2__3__4__5__6__7__8__9__0__________5__ | | | | | | | | | | | | | | | | COMPUTED ADDRESS |a|b|c|d|e|f|g|h|i|j|k|l| CT HOLD | _|____________________________________|__|__|__|__|__|__|__|__|__|__|__|__|____________| 18 1 1 1 1 1 1 1 1 1 1 1 1 1 6 .inl 0 .ifi fig "SCU Data Format, Word 5" Legend: .spb .inl 30 .unl 30 M__a_s_k K__e_y F__i_e_l_d M__e_a_n_i_n_g .unl 30 .spb 777777 * COMPUTED ADDRESS .fin (scu.ca) effective address value (offset) used in the last address preparation cycle. .spb .unl 30 400000 a RF (scu.cu.rf) first cycle of a repeat operation. .spb .unl 30 200000 b RPT (scu.cu.rpt) executing a repeat. .spb .unl 30 100000 c RD (scu.cu.rd) executing a repeat double. .spb .unl 30 040000 d RL (scu.cu.rl) executing a repeat link. .spb .unl 30 020000 e POT (scu.cu.pot) prepare operand tally. .brf This flag is on until the indirect word of an IT indirect cycle is successfully fetched. .spb .unl 30 010000 f PON (scu.cu.pon) prepare operand notally. .brf This flag is on until the indirect word of a "return" type instruction is successfully fetched. It indicates that there is no indirect chain even though an indirect fetch is being done. .spb .unl 30 004000 g XDE (scu.cu.xde) execute double from even ICT. .spb .unl 30 002000 h XDO (scu.cu.xdo) execute double from odd ICT. .spb .unl 30 001000 i ITP (scu.cu.poa) ITP cycle. .spb .unl 30 000400 j RFI (scu.cu.rfi) restart this instruction at RCU time. .spb .unl 30 000200 k ITS (scu.cu.its) executing ITS indirect cycle. .spb .unl 30 000100 l IF (scu.cu.if) fault occurred during instruction fetch. .spb .unl 30 000077 CT HOLD (scu.tag) contents of the "remember modifier" register. .inl 0 .fif .spb 3 2 even_inst bit (36), /* Word 6 - continued below */ .spb 2 .inl 3 0 1 1 2 2 2 3 3 _0__________________________________7__8__________________7__8__9__0__________5__ | | | | | | | ADDRESS | OPCODE |I|P| TAG | _|____________________________________|____________________|__|__|____________| 18 10 1 1 6 .inl 0 .ifi fig "SCU Data Format, Word 6" Legend: .spb .inl 10 .unl 10 ADDRESS current effective 18-bit address. .spb .unl 10 OPCODE current operation code. .spb .unl 10 I interrupt inhibit bit. .brf 0 = interrupts permitted. .brf 1 = interrupts inhibited. .spb .unl 10 P pointer register flag. .inl +4 .fin .alb .unl 4 0 = Do not use a pointer register for this address preparation cycle. If in appending mode, ADDRESS is an 18-bit offset relative to the procedure segment as specified in PPR. .unl 4 1 = Decode ADDRESS(0,2) as the number of a pointer register to be used in this address preparation cycle. ADDRESS(3-17) is an offset relative to the base of the segment specified in the pointer register. .spb .inl -4 .unl 10 TAG current address modifier. .spb .inl 0 Word 6 is the contents of the "working instruction register" and reflects conditions at the exact point of address preparation when the fault/interrupt occurred. Each instruction of the current pair is moved to this register before actual address preparation begins. At the time this word is stored, it may no longer be identical to the original instruction fetched from memory. .spb 3 .inl 0 .fif 2 odd_inst bit (36); /* Word 7 */ .spb 2 .inl 3 0 1 1 2 2 2 3 3 _0__________________________________7__8__________________7__8__9__0__________5__ | | | | | | | ADDRESS | OPCODE |I|P| TAG | _|____________________________________|____________________|__|__|____________| 18 10 1 1 6 .inl 0 .ifi fig "SCU Data Format, Word 7" .spb Legend: .spb .inl 10 .unl 10 .fin .alb ADDRESS address as in word 6. .spb .unl 10 OPCODE operation code as in word 6. .spb .unl 10 I interrupt inhibit bit as in word 6. .spb .unl 10 P pointer register flag as in word 6. .spb .unl 10 TAG address modifier as in word 6. .spb .inl 0 Word 7 is the contents of the "instruction holding register". It contains the odd word of the last instruction pair fetched from main memory if word 6 contains the even word. Primarily because of store overlap, this instruction is not necessarily paired with the instruction in word 6. .inl 0 .brf .srv draft "RSW DATA FORMAT" .ifi l2h "Read Switches Data Format" The read switches (rsw) instruction provides the ability to interrogate various switches on the processor maintenance and configuration panels. .cbn The least significant bits of the computed address are used to select the switches to be read. .cbn RSW instruction address fields containging xxxxx0 through xxxxx4 are valued for the L68 and DPS Processors, while address fields containing xxxxx0 though xxxxx2 for the DPS 8M Processor. Data is placed in the A register. .spb On the L68 the 3 least significant bits (bits 15-17) of the computed address are used to select the switches to be read. On the DPS 8 the 2 least significant bits (bits 16-17) are used. .spb .fif .inl 0 _b_i_t_s 1_5_-1_7_ _n_m_e_u_m_o_n_i_c L_6_8_ D_P_S_ 8_ .spb 000 rswo data switches data switches 001 rsw1 ports A,B,C,D ports A,B,C,D 010 rsw2 L68 configuration DPS 8 configuration 011 rsw3 ports E,F,G,H data switches (shouldn't be used) 100 rsw4 L68 interlace data switches 101 ---- ---- ports A,B,C,D 110 ---- ---- DPS 8 configuration 111 ---- ---- data switches (shouldn't be used) .inl 0 .fin .ifi tab "NEEDS A NAME" .cbf .spb This is unformatted data; hence, there is no software declaration for the data in main memory. .spb .fif .inl 3 0 3 _0______________________________________________________________________5__ | | | Maintenance Panel Data Switches | _|________________________________________________________________________| .inl 0 .ifi fig "rsw xxxxx0 Data Format" .spb .cbn rsw xxxxx2 for the L68 and DPS Processors: .spb PL/I Declaration (rsw.incl.pl1) .spb .fif dcl 1 dps_rsw_2 aligned based (rswp), (2 pad1 bit (4), 2 cpu_type fixed bin (2) unsigned, 2 fault_base bit (7), 2 pad2 bit (6), 2 dps_option bit (1), 2 pad3 bit (7), 2 cache2 bit (1), 2 ext_gcos bit (1), 2 id bit (4), 2 cpu_num fixed bin (3) unsigned) unaligned; 0 0 0 0 0 1 1 1 1 2 2 2 2 2 3 3 3 0 3 4 5 0 2 3 8 9 0 6 7 8 9 2 3 5 _____________________________________________________________ | | | | | | | | | | | |0000|a| FLT BASE |000000|b|0000000|c|d| CPU ID | CPU | |____|_|__________|______|_|_______|_|_|______________|_____| 4 2 7 6 1 7 1 1 4 3 .ifi fig "rsw xxxxx2 Data Format for L68 and DPS Processors" Legend: .spb K__e_y F__i_e_l_d M__e_a_n_i_n_g .spb a CPU_TYPE (dps_rsw_2.cpu_type) equals "0 0"s For a L68 or a DPS Processor FLT BASE (dps_rsw_2.fault_base) seven MSB of the 12-bit fault base address. b (dps_rsw_2.dps_option) 0 = L68 Processor 1 = DPS Processor c (dps_rsw_2.cache2) 2 K cache option 0 = disabled 1 = enabled d (dps_rsw_2.ext_gcos) GCOS mode extended memory option 0 = disabled 1 = enabled CPUID (dps_rsw_2.id) These bit positions have configuration of "1110"s for a L68 or DPS CPU. CPU (dps_rsw_2. CPU_num) Processor number from config panel processor number switches. .spb 2 .inl 0 rsw xxxxx2 Format For DPS 8M Processor: .spb PL/1 Declaration (rsw.incl.pl1) .spb dcl 1 dps8_rsw_2 aligned based (rswp), (2 interlace_info (0:3) bit (1), 2 cpu_type fixed bin (2) unsigned, 2 fault_base bit (7), 2 id_prom bit (1), 2 pad1 bit (5), 2 dps_option bit (1), 2 cache8 bit (1), 2 pad2 bit (2), 2 multics_cpu bit (1), 2 pad3 bit (6), 2 cpu_speed bit (4), 2 cpu_num fixed bin (3) unsigned) unaligned; 0 0 0 0 0 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 3 3 3 0 3 4 5 6 2 3 4 7 8 9 0 1 2 3 4 5 6 8 9 2 3 5 _____________________________________________________________ | | | | | | | | | | | | | | | | | | | |A|B|C|D| b | FLT |c|0000|d|e|f|0 0|g|h|i|000|SPEED | CPU | |-------| | | | | | | | | | | | | | | |a|a|a|a| | BASE| | | | | | | | | | | | | |_|_|_|_|___|_____|_|____|_|_|_|___|_|_|_|___|______|_______| 4 2 7 1 4 1 1 1 211 1 1 3 4 3 .ifi fig "rsw xxxxx2 Format For DPS 8 Processors" .spb Lengend: .spb K__e_y F__i_e_l_d M__e_a_n_i_n_g a (dps 8_rsw_2. interlace_info) IF rsw1.port_info.interlace_enable = "1"b The 0 = 4 word interlace 1 = 2 word interlace For Ports A-D b (dps 8_rsw_2.cpu_type) Processor Type 00 = L68 or DPS Processor 01 = DPS 8M Processor 10 = reserved for Multics ELS processor 11 = reserved for furture use FLT BASE (dps8_rsw_2. Fault_base) seven MSB of The 12-bit Fault base address (dps8_rsw_2.1dprom IO prom c 0 = 1d prom not installed 1 = 1d prom installed d BCD option (Marketing designation) (Not declared) 1 = BCD option installed e DPS option (Marketing designation) 1 = DPS option f 8k cache 1 = 8k cache installed g DPS 8 Processor type designation 1 = DPS 8/xx M 0 = DPS 8/xx GCOS/VMS or Multics switch position 1 = Virtual Mode 0 = GCOS Mode Current or new product line peripheral type 1 = NPL 0 = CPL SPEED Processor speed options 0000 = 8/70 0100 = 8/52 CPU Processor number .fin .spb 3 .inl 0 rsw1 or rsw3: .spb For this operation, 1 = ports A,B,C,D and 3 = ports E,F,G,H. Note that rsw3 on DPS 8 Processors is the same as rsw0. .spb Fpr DPS 8M Processors, rswxxxxx1 only is valid. .cbf .spb PL/I Declaration (rsw.incl.pl1) .spb dcl 1 rsw_13 aligned based (rswp), (2 port_info (0 : 3), 3 port_assignment bit(3), 3 port_enable bit(1), 3 initialize_enable bit(1), 3 interlace_enable bit(1), 3 mem_size bit(3)) unaligned; .spb 2 .fif .inl 3 0 0 0 1 1 2 2 3 _0________________8__9________________7__8________________6__7________________5__ | PORT A/E | PORT B/F | PORT C/G | PORT D/H | |-----------------|-----------------|-----------------|-----------------| _|_A_D_R___|_a_|_b_|_c_|_M_E_M___|_A_D_R___|_a_|_b_|_c_|_M_E_M___|_A_D_R___|_a_|_b_|_c_|_M_E_M___|_A_D_R___|_a_|_b_|_c_|_M_E_M___| 3 1 1 1 3 3 1 1 1 3 3 1 1 1 3 3 1 1 1 3 .inl 0 .ifi fig "rsw xxxxx1/3 Data Format" Legend: .spb .fin .alb .inl 20 .unl 20 K__e_y F__i_e_l_d M__e_a_n_i_n_g .unl 10 .spb ADR (rsw_13.port_info.port_assignment) setting of address assignment switches for port. .spb .unl 20 a (rsw_13.port_info.port_enable) port enabled flag. .spb .unl 20 b (rsw_13.port_info.initialize_enable) initialize control flag. .spb .unl 20 c (rsw_13.port_info.interlace_enabled) interlace enabled flag. .spb .unl 10 MEM (rsw_13.port_info.mem_size) coded memory size .cbn for a L68 and DPS Processor .cbf determined as follows: .cbn .spb .inl +5 .fif M_E_M_ _o_n L_6_8_ _o_n D_P_S_ 8_ .spb 000 32K 32K 001 64K 64K 010 96K _o_r 160K 128K 011 128K 256K 100 512K 512K 101 1024K 1024K 110 2048K 2048K 111 256K 4096K .spb .fif .inl 0 dcl 1 dps_rsw_2 aligned based (rswp), (2 pad1 bit (4), 2 cpu_type fixed bin (2) unsigned, 2 fault_base bit (7), 2 pad2 bit (6), 2 dps_option bit (1), 2 pad3 bit (7), 2 cache2 bit (1), 2 ext_gcos bit (1), 2 id bit (4), 2 cpu_num fixed bin (3) unsigned) unaligned; 0 0 0 0 0 1 1 1 1 2 2 2 2 2 3 3 3 0 3 4 5 0 2 3 8 9 0 6 7 8 9 2 3 5 _____________________________________________________________ | | | | | | | | | | | |0000|a| FLT BASE |000000|b|0000000|c|d| CPU ID | CPU | |____|_|__________|______|_|_______|_|_|______________|_____| 4 2 7 6 1 7 1 1 4 3 .ifi fig "rsw xxxxx2 Data Format for L68 and DPS Processors" Legend: .spb K__e_y F__i_e_l_d M__e_a_n_i_n_g .spb a CPU_TYPE (dps_rsw_2.cpu_type) equals "0 0"s For a L68 or a DPS Processor FLT BASE (dps_rsw_2.fault_base) seven MSB of the 12-bit fault base address. b (dps_rsw_2.dps_option) 0 = L68 Processor 1 = DPS Processor c (dps_rsw_2.cache2) 2 K cache option 0 = disabled 1 = enabled d (dps_rsw_2.ext_gcos) GCOS mode extended memory option 0 = disabled 1 = enabled CPUID (dps_rsw_2.id) These bit positions have configuration of "1110"s for a L68 or DPS CPU. CPU (dps_rsw_2. CPU_num) Processor number from config panel processor number switches. .spb 2 rsw xxxxx2 Format For DPS 8M Processor: .spb PL/1 Declaration (rsw.incl.pl1) .spb dcl 1 dps8_rsw_2 aligned based (rswp), (2 interlace_info (0:3) bit (1), 2 cpu_type fixed bin (2) unsigned, 2 fault_base bit (7), 2 id_prom bit (1), 2 pad1 bit (5), 2 dps_option bit (1), 2 cache8 bit (1), 2 pad2 bit (2), 2 multics_cpu bit (1), 2 pad3 bit (6), 2 cpu_speed bit (4), 2 cpu_num fixed bin (3) unsigned) unaligned; 0 0 0 0 0 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 3 3 3 0 3 4 5 6 2 3 4 7 8 9 0 1 2 3 4 5 6 8 9 2 3 5 _____________________________________________________________ | | | | | | | | | | | | | | | | | | | |A|B|C|D| b | FLT |c|0000|d|e|f|0 0|g|h|i|000|SPEED | CPU | |-------| | | | | | | | | | | | | | | |a|a|a|a| | BASE| | | | | | | | | | | | | |_|_|_|_|___|_____|_|____|_|_|_|___|_|_|_|___|______|_______| 4 2 7 1 4 1 1 1 211 1 1 3 4 3 .ifi fig "rsw xxxxx2 Format For DPS 8 Processors" .spb Lengend: .spb K__e_y F__i_e_l_d M__e_a_n_i_n_g a (dps 8_rsw_2. interlace_info) IF rsw1.port_info.interlace_enable = "1"b The 0 = 4 word interlace 1 = 2 word interlace For Ports A-D b (dps 8_rsw_2.cpu_type) Processor Type 00 = L68 or DPS Processor 01 = DPS 8M Processor 10 = reserved for Multics ELS processor 11 = reserved for furture use FLT BASE (dps8_rsw_2. Fault_base) seven MSB of The 12-bit Fault base address (dps8_rsw_2.1dprom IO prom 0 = 1d prom not installed 1 = 1d prom installed d BCD option (Marketing designation) (Not declared) 1 = BCD option installed e DPS option (Marketing designation) 1 = DPS option f 8k cache 1 = 8k cache installed g DPS 8 Processor type designation 1 = DPS 8/xx M 0 = DPS 8/xx GCOS/VMS or Multics switch position 1 = Virtual Mode 0 = GCOS Mode Current or new product line peripheral type 1 = NPL 0 = CPL SPEED Processor speed options 0000 = 8/70 0100 = 8/52 CPU Processor number .fin .inl 0 .spb 3 rsw xxxxx4 format for L68 and DPS Processors; rsw xxxxx4 is not valid for DPS 8M Processors. .cbf .spb PL/I Declaration (rsw.incl.pl1) .spb dcl 1 rsw_4 aligned based (rswp), (2 mbz1 bit(13), 2 port_interlace (0 : 7), 3 four bit(1), 3 half_controller bit(1), 2 mbz2 bit(7)) unaligned; .spb 2 .inl 3 0 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 0 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 5 --------------------------------------------------------------------------- | | A |B | C | D | E | F | G | H | | | 0 0 0 0 0 0 0 0 0 0 0 0 0--------------------------------|0 0 0 0 0 0 0 | | |a|b|a|b|a|b|a|b|a|b|a|b|a|b|a|b| | ___________________________________________________________________________ 13 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 7 .inl 0 .ifi fig "rsw xxxxx4 Data Format" Legend: .spb .inl 20 .fin .alb .unl 20 K__e_y F__i_e_l_d M__e_a_n_i_n_g .unl 10 .spb A,B,..,H tags for the eight processor ports. .spb .unl 20 a (rsw4.port_interlace.four) interlace mode for port. .brf 1 = 4-word interlace, if interlace enabled for port. .brf 0 = 2-word interlace, if interlace enabled for port. .spb .unl 20 b (rsw4.port_interlace.half_controller) memory range for port. .brf 0 = full range. .brf 1 = half range, but "size" is taken as full. .inl 0 .srv draft "MODE REGISTER FORMATS" .ifi l2h "Mode Register and Cache Mode Register Formats" .fin .alb The mode register and cache register contain several dynamic CPU and cache conditions and program accessible controls. The cache mode register is loaded with the lcpr (tag 02) instruction, and the mode register is loaded with the lcpr (tag 04) instruction. The scpr (tag 06) stores the mode register and the cache mode register in a word pair. .spb .fif PL/I Declaration (mode_reg.incl.pl1) for L68 and DPS Processors .spb dcl 1 mrg based(mrp) aligned, /* Even word */ (2 ffv bit(15), 2 pad0 bit(1), 2 top bit(1), 2 tam bit(1), 2 opcss bit(10), /* See switch bits below */ 2 tcuov bit(1), 2 scuop bit(1), 2 ehr bit(1), 2 ehrrs bit(1), 2 test bit(1), 2 pad1 bit(2), 2 emr bit(1)) unaligned; .spb dcl 1 mrg_sw based(mrp) aligned, /* Switch bits in opcss */ (2 pad0 bit(18), 2 scuolin bit(1), 2 ssolin bit(1), 2 ssdpar bit(1), 2 sszacpar bit(1), 2 stm bit(2), 2 svm bit(2), 2 pad3 bit(10))unaligned; .spb .cbd .spb .inl 3 0 1 1 1 1 1 2 2 2 3 3 3 3 3 3 _0____________________________4__5__6__7__8__________________7__8__9__0__1__2__3__4__5__ | | | | | | | | | | | | | | FFV |0|a|b| OPCODE |c|d|e|f|g|0 0|h| _|______________________________|__|__|__|____________________|__|__|__|__|__|____|__| 15 1 1 1 10 1 1 1 1 1 2 1 .cbn .ifi fig "Mode Register Format, L68 and DPS Processors" .cbf .spb .cbd .inl 0 .fin Legend: .spb .fin .inl 20 .unl 20 K__e_y F__i_e_l_d M__e_a_n_i_n_g .unl 10 .spb FFV (mrg.ffv) the "floating fault vector" address. .brf This address consists of the 15 MSB of the modulo 8 base address of four word pairs. These floating faults are generated by other conditions settable by the mode register. .spb .unl 20 a OC TRAP (mrg.top) trap on OPCODE match. (See "Notes" below.) .brf If this bit is set and OPCODE matches the operation code of the instruction for which an address is being prepared (including indirect cycles), generate the second floating fault (xed FFV|2). .spb .unl 20 b ADR TRAP (mrg.tam) trap on FFV match. (See "Notes" below.) .brf If this bit is set and the contents of the address register of the CPU match the setting of the address switches on the maintenance panel, generate the fourth floating fault (xed FFV|6). .spb .unl 10 OPCODE (mrg.opcss) opcode upon which to trap. .brf If either bit 16 (key a) or bit 29 (key d) is set, interpret bits 18-27 as an opcode value. If both bit 16 and bit 29 are not set and bit 32 (key g) is set, interpret bits 18-27 as follows: .spb .inl +6 .unl 6 _b_i_t _m_e_a_n_i_n_g .unl 5 18 (mrg_sw.scuolin) set CU overlap inhibit. The CU waits for the OU to complete execution of the even instruction before it begins address preparation for the associated odd instruction. The CU also waits for the OU to complete execution of the odd instruction before it fetches the next instruction pair. .spb .unl 5 19 (mrg_sw.ssolin) set store overlap inhibit. The CU waits for completion of a current memory fetch (read cycles only) before requesting a memory access for another fetch. .spb .unl 5 20 (mrg_sw.ssdpar) set store incorrect data parity. The CU causes incorrect data parity to be sent to the SC for the next data store instruction and then resets bit 20. .spb .unl 5 21 (mrg_sw.sszacpar) set store incorrect ZAC parity. The CU causes incorrect zone-address-command (ZAC) parity to be sent to the SC for each memory cycle of the next data store instruction and resets bit 21 at the end of the instruction. .spb .inl 0 M__a_s_k F__i_e_l_d M__e_a_n_i_n_g .spb .inl 26 .unl 6 22,23 (mrg_sw.stm) set timing margins. If bit 32 (key g) is set and the margin control switch on the CPU maintenance panel is in program position, set CPU timing margins as follows: .spb .fif 2_2_,_3_3_ _m_a_r_g_i_n 0,0 normal 0,1 slow 1,0 normal 1,1 fast .spb .fin .inl 26 .unl 6 24,25 (mrg_sw.svm) set +5 voltage margins. If bit 32 (key g) is set and the margin control switch on the CPU maintenance panel is in the program position, set +5 voltage margins as follows: .spb .fif 2_4_,_2_5_ _m_a_r_g_i_n 0,0 normal 0,1 low 1,0 high 1,1 normal .fin .alb .spb .unl 6 26,27 not used .inl -6 .spb .inl 20 .unl 20 c (mrg.tcuov) trap on CU-HR count overflow. (See "Notes" below.) .brf If this bit is set and bit 30 (key e) is set and the CU-HR counter overflows, generate the third floating fault (xed FFV|4). Further, if bit 31 (key f) is set, reset bit 30, locking the history registers. An lcpr instruction setting bit 28 resets the CU-HR counter to zero. .spb .unl 20 d O-C c| (mrg.scuop) strobe CU-HR on OPCODE match. .brf If this bit and bit 30 (key e) are set and the operation code of the current instruction matches OPCODE, strobe the CU-HR on all CU cycles (including indirect cycles). .spb .unl 20 e STROBE c| (mrg.ehr) enable history registers. .brf If this bit is set, all history registers are strobed at appropriate points in the various CPU cycles. If this bit is reset or bit 35 (key h) is reset, all history registers are locked. This bit is reset with an lcpr instruction providing a 0 bit, an onc fault, and, conditionally, by other faults (see bit 31 (key f) below). Once reset, the bit must be set with an lcpr instruction providing a 1 bit before the history registers again become active. .spb .unl 20 f FAULT (mrg.ehrrs) history register lock control. .brf .spb .unl 10 RESET If this bit is set, reset bit 30, locking the history registers, for the following faults and conditions: .spb .inl +10 .all .fif luf Lockup Fault par Parity Fault cmd Command Fault str Store Fault ipr Illegal Procedure Fault sdf Shutdown Fault OPCODE trap CU-HR counter overflow trap Address match trap .inl -10 .fin .alb .spb .unl 20 g c| VOLTAGE (mrg.test) test mode indicator. .brf This bit is set whenever the TEST/NORMAL switch on the maintenance panel is in TEST position and is reset otherwise. It serves to enable the program control of voltage and timing margins. .spb .unl 20 h MR ENABLE (mrg.emr) enable mode register. .brf When this bit is set, all other bits and controls of the mode register are active. When this bit is reset, the mode register controls are disabled. .spb .fif .cbn .inl 0 DPS 8 PL/I Declaration (dps8_mode_reg.incl.pl1) .spb dcl 1 dps8_mrg based (mrp) aligned, (2 pad1 bit(18), 2 cuolin bit(1), 2 solin bit(1), 2 sdpar bit(1), 2 szacpar bit(1), 2 tm bit(2), 2 vm bit(2), 2 pad2 bit(2), 2 lrhlt bit(1), 2 ehr bit(1), 2 ehrrs bit(1), 2 mrgctl bit(1), 2 hexfp bit(1), 2 pad3 bit(1), 2 emr bit(1)) unaligned; .inl 0 .fif .spb 0 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 0 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 _________________________________________________________________ | | | | | | | | | | | | | | | | | | 000 000000 000000 000 |a|b|c|d| e | f |0 0|g|h|i|j|k|l|o|m| ----------------------------------------------------------------- 18 1 1 1 1 2 2 2 1 1 1 1 1 1 1 1 .fin .ifi fig "DPS 8Mode Register Format" .spb .inl 0 Legend: .spb .fin .inl 20 .unl 20 K__e_y F__i_e_l_d M__e_a_n_i_n_g .unl 20 .spb a (dps8mrg.cuolin) set CU ovelap inhibit. The CU waits for the OU to complete execution of the even instruction before it begins address prepation for the associated odd instruction. the CU also waits for the OU to complete execution of the odd instruction before it fectches the next instruction pair. .spb .unl 20 b (dps8_mrg.solin) set store overlap inhibit. The CU waits for completion of a current memory fetch (read cycles only) before requesting a memory access for another fetch. .spb .unl 20 c (dps8_mrg.sdpar) set store incoorect data parity. the CU causes incorrect data parity to be sent to the SC for the next data store instruction and then resets bit 20. .spb .unl 20 d (dps8_mrg.szacpar) set store incorrect ZAC parity. The CU causes incorrect zone-address-command (ZAC) parity to be sent to the SC for each memory cycle of the next data store instrcution and resets bit 21 at the ned of the instruciton. .spb .unl 20 e (dps8mrg.tm) set timing margins. If bit 32 (key k) is set and the margin control switch on the CPU maintenance panel is in program position, set CPU timing margins as follows: .spb .fif 2_2_.3_3_ _m_a_r_g_i_n 0,0 normal 0,1 slow 1,0 normal 1,1 fast .spb .fin .unl 20 f (dps_mrg.vm) set +5 voltage margins. If bit 32 (key k) is set and the margin control switch on the CPU maintenance panel is in the program position, set +5 voltage margins as follows: .spb .fif 2_4_.2_5_ _m_a_r_g_i_n 0,0 normal 0,1 low 1,0 high 1,1 normal .fin .spb .unl 20 g (dps_mrg.hrhlt) Stop HR Strobe on HR Counter Overflow. (Setting bit 28 shall cause the HR counter to be reset to zero.) .spb .unl 20 l (dps_mrg.hrxfr) Strobe the HR on Transfer Made. If bits 29,30 and 35 are = 1, the HR will be stored on all Transfers Made. Bits 36-53 of the OU/DU register will indicate the "From" location and bits 35-59 of the Cu register will contain the real address of the final "To" location. .spb .unl 20 i (dps8_mrg.ehr) Enable History Registers. If bit 30 = 1, the HR's may be strobed. If bit 30 = 0 or bit 35 = 0, they will be locked out. This bit will be reset by either an LCPR with the bit correcponding to 30 = 0 or by an Op Not Complete fault. It may be reset by other faults (see bit 31). After being reset, it must be enabled by another LCPR instruction before the History Registers may be strobed again. .spb .unl 20 j (dps8_mrg.ehrrs) Additional Resetting of bit 30. if bit 31 = 1, the following faults will also reset bit 30: .spb .fif - Lock up - Parity - Command - Store - Illegal Procedure - Shutdown .spb .inl 20 .unl 20 k (dps8_mrg.mrgctl) Margin Control. Bit 32 shall be used to inform the software when it can control margins. A one shall indicate that software has control. When the LOCAL/REMOTE switch on the power supply is in REMOTE and bit 35 = 1, bit 32 shall be set to one by occurrence of the position. The memory and CU Overlap Inhibit switches are OFF, the TIMING Margin s for the OU, CU, DU and VU are NORMAL, and the Forced Data and ZAC Parity are OFF. .spb .inl 20 .unl 20 l (dps8_mrg.hexfp) Hexadecimal Exponent Floating Point Arithmetic Mode can be set. When this bit is set, hte Hex mode will be come effective when the Indicator Register bit 32 is set to ONE. .spb .unl 20 m (dps_mrg.emr) unless bit 35 = 1, all other bits in the Mode Register will be ignored and the History Register will be locked. .inl 0 .fin .ifi l2h "Cache Mode Register" PL/I Declaration (cache_mode_reg.incl.pl1) .spb .fif dcl 1 cmr based aligned, (2 address_mask bit(15), 2 dir_parity bit(1), 2 level_full bit(1), 2 pad1 bit(1), 2 cache_1_on bit(1), 2 cache_2_on bit(1), 2 inst_from_cache bit(1), 2 pad2 bit(1), 2 cache_to_reg_mode bit(1), 2 store_aside bit(1), 2 column_full bit(1), 2 rro_mask bit(2), 2 pad3 bit(4), 2 byp bit(1), 2 pad4 bit(1), 2 luf_reg_mask bit(2)) unaligned; .spb 3 5 5 5 5 5 5 5 5 5 5 6 6 6 6 6 6 6 6 7 7 6 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 7 8 9 0 1 -------------------------------------------------------------------- | CACHE DIR ADDRESS |a|b|0|c|d|e|f|g|b|i|j|k|0 0 0|0|l|0|m|n| -------------------------------------------------------------------- 15 1 1 1 1 1 1 1 1 1 1 1 1 6 1 1 .ifi fig "Cacahe Mode Register Format" .spb .inl 10 .unl 10 CACHE DIR ADDRESS .spb .brf (cmr.address_mask) cache block address from cache directory. .spb .inl 20 .unl 20 a PAR BIT (cmr.dir_parity) cache directory parity bit. .spb .unl 20 b LEV FUL (cmr.level_full) cache level is full. .spb .unl 20 c CSH1 ON (cmr.cache_1_on) first two levels of the cache are enabled. .spb .unl 20 d CSH2 ON (cmr.cache_2_on) second two levels of the cache is enabled. .spb .unl 20 e OPND ON (cmr.operands_from_cache) cache is enabled for operands. .brf (valid only for L68 and DPS Processors) This bit .brf is diregarded on DPS 8 Processors. .spb .unl 20 f INST ON (cmr.inst_from_cache) cache is enabled for instructions. .spb .unl 20 g CSH REG (cmr.cache_to_reg_mode) enabled cache/register. .spb .unl 20 l STR ASD (cmr.store_aside) store aside enabled. .spb .unl 20 i COL FUL (cmr.column_full) column is full. .spb .unl 20 j RRO A round robin counter, bit A. .spb .unl 20 k RRO B round robin counter, bit B. .brf (RRO A,B collected as cmr.rro_mask) .spb .unl 20 l BYP (cmr.byp) Enables the bypass option of SDW.C when set OFF. (for DPS 8M Processors only , this bit will be 0 for L68 and DPS Processors). See Notes below for more information. .spb .unl 20 m LUF MSB lockup timer setting, most significant bit. .spb .unl 20 n LUF LSB lockup timer setting, least significant bit. .brf (LUF MSB,LSB collected as cmr.luf_reg_mask) .inl 0 .fin .ifi l2h "Notes" .inl 10 .unl 5 1. The Floating Fault Vectors, Address and OPCODE Traps have been eliminated on DPS 8M Processors. .spb .unl 5 2. For L68 and DPS Processors these traps (address match, OPCODE match, CU-HR counter overflow) occur after completion of the next _o_d_d _i_n_s_t_r_u_c_t_i_o_n_s following their detection. They are handled as Group VII faults in regard to servicing and inhibition. The complete Group VII priority sequence is: .spb .fif .inl +5 1 - con 2 - tro 3 - sdf 4 - OPCODE trap 5 - CU-HR counter overflow 6 - Address match trap 7 - External interrupts .inl -5 .fin .spb .unl 5 3. The COL FUL, RRO A, RRO B, and CACHE DIR ADDRESS fields reflect different loctions in cache depending on the final (absolute) address of the scpr instruction storing this data. .spb .unl 5 4. If either cache Enable bit c or d changes from Disable state to Enable state, the entire cache is cleared. .spb .unl 5 5. The DPS 8M Processors contain an FK hardware controlled cache memory. Bit 68 of the Cache Mode Register (reference L), has been provided to allow the DPS 8M Processors to work software compatable with the older 2K software controlled cache in the L68 and DPS Processors, when running a mixed configuration, with both DPS 8M and L68 Processors. What follows is a summary of how the DPS 8M hardware controlled cache works: .spb .inl +5 .unl 5 a. The Cache bypass option in the segment descriptor word is retained. An overriding bypass enable, bit 68 of the Cache mode register is added. The cache mode is set as follows: .spb .fif ______________________________________________________ | | | | | SDW.C | CMR | RESULTING CACHE MODE | |_______________|_________6_8_____|_______________________| | | | | | Use Cache | X | Use Cache | |_______________|_______________|_______________________| | | | | | Bypass Cache | Bypass Cache | Bypass Cache | |_______________|_______________|_______________________| | | | | | Bypass Cache | Use Cache | Use Cache | |_______________|_______________|_______________________| .fin .spb .unl 5 b. All close gate instructions, LDAC, LDQC, STAC, STACQ, and SZNC will automatically bypass Cache. Two features are added to ensure integrity of gated shared data; one is added during the close gate operation and the other during the open gate operation. The instruction following the close gate instruction will bypass cache if the instruction is a Read or a Read-alter-rewrite. The open gate operation must be performed with either a STCZ of STACQ which includes the synchronizing function. The synchronizing function forces the processor to delay the open gate operation until it is notified by the SCU that write completes have occurred and write notifications requesting cache block clears have been sent to the other processors for all write instructions that the processor has previously issued. .spb .unl 5 c. Read-alter-rewrite instructions will no longer automatically bypass cache. Cache behavior for these instructions is determined fully by SDW.C. If the bypass cache mode is set, these instructions will bypass cache and issue read-lock-write-unlock commands to memory. If a cache directory match occurs, the location is cleared. .spb .unl 5 d. All accesses to memory by SDW and PTW associative memory hardware will continue to bypass cache. Operations used will be Reads for SDWs, Read-alter-rewrites with lock for PTWs and setting the page Used bit, and Writes for setting the page Modified and Used bits. For Writes, the hardware will also disable the key line so that the SCU lock is honored. This is consistent with dynamic PTW modification by software which also bypasses cache and uses Read-alter-rewrite instructions. .spb .unl 5 e. The instructions which cleared the associative memories and also cleared Cache or selective portions of Cache are changed to eliminate the Cache clear function. .bba Bit C (TPR.CA)Hv15H^ .bea is ignored. These instructions will also include disable/enable capabilities for each quarter of the associative memories. .spb .unl 5 f. Cache mode register bit 56, which had previously controlled Cache bypass for operands is disregarded. All other Cache control bits are continued. However, maintenance panel cache control function is restricted to Cache half enable/disable functions. .inl .fin .brp .cbf  pf.hsf.compin 10/22/84 1044.6r w 10/22/84 1043.8 864 .ifi init_mpm "AN87-01" .srv file_no "2L13" .ifi preface "1980" TO BE SUPPLIED .brp .fin .inl 0  s2.hsf.compin 10/22/84 1044.7r w 05/14/81 0909.8 156087 .ifi init_mpm "AN87-01" .srv draft_date "" .srv section 2 .ifi l0h "Series 60 System Controller and Memory" This section gives the format of the program accessible registers of the Series 60 Level 66 Controller (SCU), the Level 68 System Controller (SC), and their associated memory. .ifi l1h "System Controller Illegal Action Codes" The following are illegal action codes for the SC. .spb 2 C__o_d_e P__r_i_o_r_i_t_y C_P_U___f_l_t N__a_m_e .spb 00 no illegal action. 01 12(cmd) unassigned. 02 5 02(str) nonexistent address. 03 1 12(cmd) stop on condition. (Level 68 only) .spb 04 12(cmd) unassigned. 05 12 22(par) data parity, store to SC. 06 11 22(par) data parity in store. 07 10 22(par) data parity in store and store to SC. .spb 10 4 12(cmd) not control. (Level 68 only) 11 13 12(cmd) port not enabled. 12 3 12(cmd) illegal command. 13 7 02(str) store not ready. .spb 14 2 22(par) ZAC parity, active module to SC. 15 6 22(par) data parity, active module to SC. 16 8 22(par) ZAC parity, SC to store. 17 9 22(par) data parity, SC to store. .spb 00 12 no illegal action. -- -- 12(cmd) not used by system controller. 02 5 02(str) nonexistent address. -- -- 12(cmd) not used. .spb -- -- 12(cmd) not used. 05 10 22(par) data parity, store to SCU. 06 9 22(par) data parity in store. 07 8 22(par) data parity in store and store to SCU. .spb -- -- 12(cmd) not used. 11 11 12(cmd) port masked. 12 2 12(cmd) illegal command. 13 5 02(str) store not ready. .spb 14 1 22(par) ZAC parity, active module to SCU. 15 4 22(par) data parity, active module to SCU. 16 6 22(par) ZAC parity, SCU to store unit. 17 7 22(par) data parity, SCU to store unit. .srv draft "ILLEGAL ACTION CODES" .ifi l1h "System Controller Registers Format" The read system controller register instructions and set system controller register (rscr and sscr) provide the ability to read several registers in SCs and SCUs. The effective absolute address of the instruction selects the SC (or SCU) to be referenced by referring to the port address assignment switches. Bits 3-14 of the instruction address are sent to the SC (or SCU) to specify the register to be referenced. Bits 15-17 are not interpreted since they are used in port selection for normal data and instruction fetches when port interlace is being used. The rscr instruction reads data into the combined A and Q registers of the processor. The sscr instruction sets data from the A and Q registers. .ifi l2h "System Controller Mode Register (rscr/sscr 00000X)" .srv draft "REGISTERS FORMAT" PL/I declaration (scr.incl.pl1) .spb .fif dcl 1 scr_mr aligned, (2 pad1 bit(50), 2 identification bit(4), 2 TS_strobe_margin bit(2), 2 GO_strobe_margin bit(2), 2 ANSWER_strobe_margin bit(2), 2 DA_Strobe_margin bit(2), 2 EOC_strobe_margin bit(2), 2 PLUS_5_VOLT_margin bit(2), 2 parity_override bit(1), 2 parity_disable bit(1), 2 store_IA_disable bit(1), 2 ZAC_parity_error bit(1), 2 SGR_accepted bit(1), 2 pad2 bit(1)) unal; .spb 2 Upper Half (A register): .spb .inl 3 .fif 0 3 _0___________________________________________________________5__ | | | ALL ZEROS | _|_____________________________________________________________| .spb 2 .unl 3 Lower Half (Q register): .spb 3 4 5 5 5 7 _6_______________________9__0________3__4________________________1__ | | | | | ZEROS | ID | MODE REG | _|_________________________|__________|__________________________| .inl .ifi fig "Controller Mode Register (rscr/sscr 00000X) Data Format" .spb Legend: .spb .inl 10 .unl 10 ID (scr.mr.identification) controller ID code. .brf 0000 = 8034, 8035 .brf 0001 = Level 68 SC .brf 0010 = Level 66 SCU .spb .unl MODE REG these fields are used only by T&D. .inl 0 .ifi l2h "System Controller Configuration Switches (rscr/sscr 00001X)" Note that the configuration switches of an SC cannot be set. .spb .fif PL/I Declaration (scr.incl.pl1) .spb dcl 1 scr_cfg1 aligned, /* Upper half */ (2 mode_a bit(3), 2 bdry_a bit(3), 2 mode_b bit(3), 2 bdry_b bit(3), 2 int bit(1), 2 lwr bit(1), 2 addr_offset bit(2), 2 port_no bit(4), 2 port_enable (0:7) bit(2), 2 pima (4) bit(9)) unaligned; /* Lower half */ .spb 2 Upper Half (A register): .fif .spb .fif .inl 3 0 0 0 0 0 0 0 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 _0____2__3____5__6____8__9____1__2__3__4__5__6______9__0__1__2__3__4__5__6__7__8__9__0__1__2__3__4__5__ | | | | | | | | | | | | | | | | | |MOD A|BND A|MOD B|BND B|a|b|ADR| PORT | A | B | C | D | E | F | G | H | _|______|______|______|______|__|__|____|________|____|____|____|____|____|____|____|____| 3 3 3 3 1 1 2 4 2 2 2 2 2 2 2 2 .spb 2 .unl 3 Lower Half (Q register): .spb 3 4 4 5 5 6 6 7 _6________________4__5________________3__4________________2__3________________1__ | | | | | | MASK A | MASK B | MASK C | MASK D | _|__________________|__________________|__________________|__________________| 9 9 9 9 .inl 0 .ifi fig "SC Configuration Switches (rscr 00001X) Data Format" .spb Legend: .spb .fin .inl 20 .unl 20 K__e_y F__i_e_l_d M__e_a_n_i_n_g .unl 10 .spb MOD A/B (scr_cfg1.mode_a/b) state of store A/B. .brf 000 = online. .brf 001 = in test. .brf 010 = offline. .spb .unl 10 BND A/B (scr_cfg1.bdry_a/b) size of memory in store A/B. .brf 000 = 32K. .brf 001 = 64K. .brf 011 = 128K. .brf 111 = 256K. .spb .unl 20 a (scr_cfg1.int) interlace flag. .brf 0 = stores are not interlaced. .brf 1 = stores are interlaced. .spb .unl 20 b (scr_cfg1.lwr) low-order store flag. .brf 0 = store A is low order. .brf 1 = store B is low order. .brp .spb .unl K__e_y F__i_e_l_d M__e_a_n_i_n_g .spb .unl 10 ADR (scr_cfg1.addr_offset) setting of ADDRESS CONTROL OFFSET switch. .brf 00 = no offset. .brf 01 = 16K offset. .brf 10 = 32K offset. .brf 11 = 64K offset. .spb .unl 10 PORT (scr_cfg1.port_no) 4-bit port number of the SC port through which the rscr instruction was received. Port 8 (1000) is the maintenance panel. .spb .unl 10 A,B...H (scr_cfg1.port_enable) port state for each of the eight SC ports. .brf 00 = port disabled. .brf 01 = port in program control. .brf 11 = port enabled. .spb .unl 10 MASK A,...,MASK D .brf (scr_cfg1.pima) EXECUTE INTERRUPT MASK ASSIGNMENT (EIMA) switch settings, i.e., port assignment for each of the four execute interrupt masks. The assigned port corresponds to the bit position within the field. Absence of a bit indicates that the mask is not assigned. Port 8 is the maintenance panel. .spb .inl 0 PL/I declaration (scr.incl.pl1) .spb 1 .fif dcl 1 scr_cfg2 aligned, (2 mask_a_assign bit(9), 2 a_online bit(1), 2 a1_online bit(1), 2 b_online bit(1) 2 b1_online bit(1), 2 port_no bit(4), 2 pad1 bit(1), 2 mode bit(1) 2 nea_enabled bit(1), 2 nea bit(7), 2 int bit(1), 2 lwr bit(1), 2 port_mask_0_3 bit(4), 2 mask_b_assign bit(9), 2 pad2 bit(12), 2 cyclic_prior bit(7), 2 pad3 bit(4), 2 port_mask_4_7 bit(4)) unal; .inl 3 .spb 2 Upper Half (A register): .spb .fif .inl 3 0 0 0 1 1 1 1 1 1 1 2 2 2 2 3 3 3 3 _0________________8__9____1__2__3__4__5__6______9__0__1__2______________9__3__1__2_____5__ | | | | | | | | |M| |I|L| PMR | | MASK A |SIZE |A|A|B|B| PORT |O|O| NEA |N|W| 0-3 | _|__________________|______|__|1__|__|1__|________|__|D__|________________|T__|R__|_______| .brp Lower Half (B register): .spb 3 4 4 5 5 6 6 6 6 7 _6________________4__5______________________6__7____________3__4______7__8_____1__ | | | CYCLIC | not | PMR | | MASK B | not used | PRIOR | used | 4-7 | _|__________________|________________________|______________|________|_______| .ifi fig "SCU Configuration Switches (rscr/sscr 00001x Data Format)" .spb .inl Legend: .spb .fin .inl 10 .unl 10 MASK A (scr_cfg2.mask_a_assign) EIMA switch setting for mask A. The assigned port corresponds to the bit position within the field. A bit in position 9 indicates that the mask is not assigned. .spb .unl 10 SIZE (scr.cfg2.size) size of lower store. .spb .brf 000 = 32K .brf 001 = 64K .brf 010 = 128K .brf 011 = 256K .brf 100 = 512K .brf 101 = 1M .brf 110 = 2M .brf 111 = 4M .spb .unl 10 A (scr_cfg2.a_online) store unit A online. .spb .unl 10 A1 (scr_cfg2.a1_online) store unit A1 online. .spb .unl 10 B (scr_cfg2.b_online) store unit B online. .spb .unl 10 B1 (scr_cfg2.B1_online) store unit B1 online. .spb .unl 10 PORT (scr_cfg.port_no) 4-bit port number of the SCU port through which the rscr instruction was received. This field cannot be set with the sscr instruction. .spb .unl 10 MOD (scr_cfg2.mode) program/manual mode. If this bit is a 1, all settable bits of the configuration register may be altered. This bit cannot be set with the sscr instruction. .spb .unl 10 NEA (scr_cfg2.nea_enabled and scr_cfg2.nea) nonexistent address enable bit and nonexistent address. The first nonexistent address is 32,768 times the switch setting. .spb .unl 10 INT (scr_cfg2.int) interlace flag .brf 0 = stores are not interlaced .brf 1 = stores are interlaced. .spb .unl 10 LWR (scr_cfg2.lwr) low-order store flag. .brf 0 = store A is low-order. .brf 1 = store B is low-order. .spb .unl 10 PMRO-3 (scr_cfg2.port_mask_0_3) port enable register for ports 0 through 3. .spb .unl 10 MASK B (scr_cfg2.mask_b_assign) EIMA switch setting for mask B. (See mask A above.) .spb .unl 10 CYCLIC (scr_cfg2.cyclic_prior) settings of the cyclic port priority .unl 10 PRIOR ("anti-hogging") switches. .spb .unl 10 PRM 4-7 (scr_cfg2.port_mask_4_7) port enable register for ports 4 through 7. .inl 0 .brf .ifi l2h "System Controller Interrupt Mask Register (rscr/sscr 000N2X)" PL/I declaration (scr.incl.pl1) .spb 2 .fif dcl 1 scr_msk aligned, (2 interrupt_mask_1 bit(16), 2 pad1 bit(16), 2 port_mask_1 bit(4), 2 interrupt_mask_2 bit (16), 2 pad2 bit(16), 2 port_mask_2 bit (4)) unal; .fin .inl .spb 2 Upper Half (A register): .spb .fif .inl 3 0 1 1 3 3 3 _0______________________________5__6______________________________1__2______5__ | | | | | IER0-15 |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0|PER0-3 | _|________________________________|________________________________|________| 16 16 4 .spb 2 .unl 3 Lower Half (Q register): .spb 3 5 5 6 6 7 _6______________________________1__2______________________________7__8______1__ | | | | | IER16-31 |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0|PER4-7 | _|________________________________|________________________________|________| 16 16 4 .inl 0 .ifi fig "Interrupt Mask Register (rscr/sscr 000N2X) Data Format" .spb Legend: .spb .inl 10 .unl 10 IER0-15 (scr_msk.interrupt_mask_1) program interrupt enable register for interrupts 00 through 15. .spb .unl 10 PER0-3 (scr_msk.port_mask_1) port enable register for ports 0 through 3. This field is not set by sscr instruction. .spb .unl 10 IER16-31 (scr_msk.interrupt_mask_2) program interrupt enable register for interrupts 16 through 31. .spb .unl 10 PER4-7 (scr_msk.port_mask_2) port enable register for ports 4 through 7. This field is not set by sscr instruction. .inl 0 .brp .fin .ifi l2h "System Controller Interrupt Cells (rscr/sscr 00003X)" (There is no include file for the declaration of this data.) .fif .spb 2 Upper Half (A register): .spb .fif .inl 3 0 1 1 3 _0______________________________5__6______________________________________5__ | | | | Interrupt Cells 0-15 |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| _|________________________________|________________________________________| 16 20 .spb 2 .unl 3 Lower Half (Q register): .spb 3 5 5 7 _6______________________________1__2______________________________________1__ | | | | Interrupt Cells 16-31 |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| _|________________________________|________________________________________| 16 20 .inl 0 .ifi fig "Interrupt Cells (rscr/sscr 00003X) Data Format" .spb .fin A bit appearing in any position of the data indicates that the corresponding interrupt cell is set. .inl 0 .fif .ifi l2h "System Controller Clock (rscr/sscr 00004X)" (There is no include file for the declaration of this data.) .spb 2 Upper Half (A register): .spb .fif .inl 3 0 1 2 3 _0______________________________________9__0______________________________5__ | | | |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| CLOCK BITS 0-15 | _|________________________________________|________________________________| 20 16 .spb 2 .unl 3 Lower Half (Q register): .fif .spb 3 7 _6______________________________________________________________________1__ | | | CLOCK BITS 16-51 | _|________________________________________________________________________| 36 .inl 0 .ifi fig "System Clock (rscr/sscr/rccl 00004X) Data Format" .spb .brp .fin .inl 12 .unl 7 NOTE: The rccl instruction may also be used to read the system clock. The clock in an SC cannot be set with the sscr instruction. It must be set manually. The clock in an SCU cannot be set manually. It must be set using the sscr instruction. .inl .ifi l2h "Store Unit Mode Register (rscr/sscr 00006X)" PL/I declaration (scr.incl.pl1) .spb 2 dcl 1 scr_su aligned, (2 pad1 bit(36), 2 ZAC_line bit(6), 2 syndrome bit(8), 2 identification bit(4), 2 EDAC_disabled bit(1), 2 pad2 bit(4), 2 MINUS_5_VOLT_margin bit(2), 2 PLUS_5_VOLT_margin bit(2), 2 spare_margin bit(2), 2 PLUS_19_VOLT_margin bit(2), 2 pad3 bit(1), 2 SENSE_strobe_margin bit(2), 2 pad4 bit(1), 2 maint_functions_enabled bit(1)) unal; .spb 2 .inl Upper Half (A register): .spb .fif .inl 3 0 3 _0__________________________________________________________5__ | | | ALL ZEROS | _|____________________________________________________________| .spb 2 .unl Lower Half (Q Register): .spb 3 4 4 4 5 5 5 5 7 _6______1__2_______9__0______3__4__5_______________________________1__ | | | | | | | ZAC | SYN | ID |a| MAINT | _|________|_________|________|__|_________________________________| .ifi fig "Store Mode Register (rscr/sscr 00006X) Data Format" .inl .brp Legend: .spb .inl 20 .unl K__e_y F__i_e_l_d M__e_a_n_i_n_g .spb .unl ZAC (scr_su.ZAC_line) address lines. .spb .unl SYN (scr_su.syndrome) failure syndrome. .spb .unl ID (scr_su.identification) store unit type identification. .brf 0000 = high-speed core model AA1. .brf 0001 = high-speed core model AA3. .brf 0100 = 1K chip MOS memory with EDAC enabled. .brf 1100 = 1K chip MOS memory with EDAC disabled. .brf 1111 = 4K chip MOS memory. .unl .spb a (scr_su.EDAC_disabled) this bit is turned on when EDAC is disabled. .spb .unl MAINT these fields are used only by T&D. .fin .inl 0 .brp  s3.hsf.compin 10/22/84 1044.7r w 05/14/81 0910.4 252810 .ifi init_mpm "AN87-01" .srv draft_date "" .srv draft "IOM MAILBOX LAYOUT" .srv section 3 .ifi l0h "Level 68 Input/Output Multiplexer" This section gives the formats for the control words and the program accessible registers of the Level 68 Input/Output Multiplexer (IOM). .ifi l1h "IOM Mailbox Layout" The IOM mailbox is a dedicated area in main store used for communication with the IOM and its attached peripherals. Its location is specified by the settings of the INTERRUPT BASE and IOM BASE switches on the IOM configuration panel. Multics currently allows two IOMs and requires that the INTERRUPT BASE for both be set to 1200(8). The IOM BASE settings required are 1400(8) for IOM A and 2000(8) for IOM B. .spb PL/I Declaration (iom_data.incl.pl1) .spb .all .fif dcl 1 iom_mailbox$ aligned ext, 2 imw_array (32) bit(32), 2 system_fault_words (32) bit(36), 2 spec_status_words (32) bit(36), 2 unused (32) bit(36), 2 mailboxes (2), 3 mailbox (0:63) like channel_mailbox; .spb 2 .inl 10 ------------------------------------------ 1200 | | | IMW ARRAY | ------------------------------------------ 1240 | | | SYSTEM FAULT WORD CIRCULAR QUEUES | ------------------------------------------ 1300 | | | SPECIAL STATUS WORD CIRCULAR QUEUES | ------------------------------------------ 1340 | | | UNUSED | ------------------------------------------ 1400 | | | IOM A CHANNEL MAILBOXES | ------------------------------------------ 2000 | | | IOM B CHANNEL MAILBOXES | ------------------------------------------ .fin .ifi fig "IOM Mailbox Layout" .brp .inl 0 The IMW ARRAY is indexed by interrupt number and contains one word for each interrupt. When channel "M" of the IOM signals interrupt "N", the IOM central sets bit "M" of 1200(8)+"N" to 1. .spb 2 The SYSTEM FAULT WORD CIRCULAR QUEUES contains a 16-word circular queue for the system fault words from each of the allowed IOMs. See "System Fault Status" and Figure 3-9 later in this section. .spb 2 The SPECIAL STATUS WORD CIRCULAR QUEUES contains a 16-word circular queue for the special status words from each of the allowed IOMs. See "Special Status" and Figure 3-11 later in this section. .spb 2 The IOM A/B CHANNEL MAILBOXES contain a 4-word mailbox for each of the 64 channels of IOM A/B. See "IOM Channel Mailbox Layout" and Figure 3-2 below. .ifi l1h "IOM Channel Mailbox Layout" .alb Each of the 64 allowed channels of the IOM has a 4-word mailbox located at + 4*. .spb PL/I Declaration (iom_data.incl.pl1) .spb dcl 1 channel_mailbox based aligned, 2 lpw bit(36), 2 lpwx bit(36), 2 scw bit(36), 2 dcw bit(36); .spb 2 .fif .inl 3 0 3 _0______________________________________________________________________5__ | | | LPW | _|________________________________________________________________________| | | | LPW EXTENSION | _|________________________________________________________________________| | | | SCW | _|________________________________________________________________________| | | | DCW | _|________________________________________________________________________| .inl 0 .fin .ifi fig "IOM Channel Mailbox Layout" .spb Legend: .spb .inl 10 .unl 10 LPW, .unl 10 LPW EXTENSION .brf (channel_mailbox.lpw and channel_mailbox.lpwx) See Figure 3-3 below. .spb .unl 10 SCW (channel_mailbox.scw) See Figure 3-8 below. .spb .unl 10 DCW (channel_mailbox.dcw) See Figure 3-5 through 3-7 below. .ifi l1h "IOM Control Word Formats" .srv draft "IOM LPW" .ifi l2h "List Pointer Word (LPW)" .all .fif .inl 0 PL/I Declaration (iom_lpw.incl.pl1) .spb dcl 1 lpw based (lpwp) aligned, (2 dcw_addr bit(18), 2 res bit(1), 2 iom_rel bit(1), 2 ae bit(1), 2 nc bit(1), 2 tal bit(1), 2 rel bit(1), 2 tally bit(12)) unal; .spb dcl 1 lpw_ext based (lpwep) aligned, (2 base bit(9), 2 bound bit(9), 2 idcwp bit(18)) unal; .fin .spb (Also see Figure 3-2 above.) .spb LPW: .spb .inl 3 .fif 0 1 1 1 2 2 2 2 2 3 _0__________________________________7__8__9__0__1__2__3__4______________________5__ | | | | | | | | | | DCW (PCW) PTR |R|H|E|N|T|S| TALLY | |____________________________________|__|__|__|__|__|__|________________________| 18 1 1 1 1 1 1 12 .spb 2 .unl 3 LPW Extension: .fif .spb 0 0 0 1 2 3 _0________________8__9________________7__8__________________________________5__ | | | | | LOW BND | SIZE | IDCW PTR | _|__________________|__________________|____________________________________| 9 9 18 .inl 0 .fin .ifi fig "IOM List Pointer Word (LPW) Format" .spb Legend: .spb .inl 10 .alb .unl 10 DCW (PCW) PTR .brf (lpw.dcw_addr) address of DCW list, or, for connect channel (channel 2) only, PCW address. See Figure 3-4 through 3-7 below. .spb .unl 10 R (lpw.res) IDCW restrict bit. (The IDCW control bit from every TDCW (tdcw.res) is ORed into this LPW bit. See "Data Control Word" below.) .brf 0 = IDCWs are permitted. .brf 1 = IDCWs are prohibited. .spb .unl 10 H (lpw.iom_rel) hardware relative addressing bit. A copy of the software relative addressing bit, bit 23, made at IDCW fetch or first list service. .spb .brp .unl 10 E (lpw.ae) DCW address extension bit. (the address extension control bit from every TDCW (tdcw.ec) is ORed into this bit.) .brf .inl +4 .unl 4 0 = Fetch DCWs according to the DCW PTR (lpw.dcw_addr) without regard to the address extension value (pcw.ext). All DCWs must reside in lower 256K of store. .unl 4 1 = Fetch DCWs according to the DCW PTR (lpw.dcw_addr) and the address extension (pcw.ext). DCWs may reside anywhere in main store. .inl -4 .spb .unl 10 N (lpw.nc) tally control bit. .brf 0 = update TALLY and DCW PTR as DCWs are fetched. .brf 1 = do not update TALLY or DCW PTR. .spb .unl 10 S (lpw.rel) software relative addressing bit. (The relative addressing control bit from every TCDW (tdcw.rel) is ORed into this LPW bit.) .inl +4 .unl 4 0 = Perform data transfers to absolute store addresses determined by the address extension value and the DCW data address (dcw.address) without regard to LOW BND and SIZE. .unl 4 1 = Perform data transfers to store addresses determined by considering the DCW data address as a relative offset to the address extension value and the value of LOW BND. Also, check each DCW data address against the value of SIZE for boundary violations. .inl -4 .spb .unl 10 T (lpw.tal) tally runout flag. .brf 0 = do not signal tally runout on TALLY exhaust. .brf 1 = signal tally runout on TALLY exhaust. .spb .unl 10 TALLY (lpw.tally) count of DCWs in list. .spb .unl 10 LOW BND (lpw_ext.base) mod512 base address for current data transfer. .spb .unl 10 SIZE (lpw_ext.bound) mod512 bound for current data transfer. (Relative to LOW BND.) .spb .unl 10 IDCW PTR (lpw_ext.idiwp) address of most recent IDCW. .inl 0 .srv draft "IOM PCW" .ifi l2h "Peripheral Control Word (PCW)" .fif .all PL/I Declaration (iom_pcw.incl.pl1) .spb dcl 1 pcw based (pcwp) aligned, (2 command bit(6), 2 device bit(6), 2 ext bit(6), 2 code bit(3), 2 mask bit(1), 2 control bit(2), 2 chan_cmd bit(6), 2 count bit(6), 2 mbz1 bit(3), 2 channel bit(6), 2 mbz2 bit(27)) unal; .spb 2 Even Word: .spb .inl 3 0 0 0 1 1 1 1 2 2 2 2 2 2 3 3 _0__________5__6__________1__2__________7__8____0__1__2__3__4__________9__0__________5__ | | | | | | | | | | DEV CMND | DEV CODE | ADR EXTN |1 1 1|M| CN| CHN CMND | CHN DATA | _|____________|____________|____________|______|__|____|____________|____________| 6 6 6 3 1 6 6 .brp .spf 2 .unl 3 Odd Word: .spb 0 0 0 0 0 3 _0____2__3__________8__9____________________________________________________5__ | | | | |0 0 0| CHN NMBR |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| _|______|____________|______________________________________________________| 3 6 27 .inl 0 .fin .ifi fig "IOM Peripheral Control Word (PCW) Format" .spb Legend: .spb .inl 10 .alb .unl 10 DEV CMND (pcw.command) device command. .spb .unl 10 DEV CODE (pcw.device) device address. .spb .unl 10 ADR EXTN (pcw.ext) address extension for addressing beyond 256K. .spb .unl 10 M (pcw.mask) channel control mask. .brf 0 = normal operation. .brf 1 = mask channel OFF and initialize. .spb .unl 10 CN (pcw.control) channel control. .brf 00 = terminate at end of I/O operation. .brf 10 = proceed (list service) at end of I/O operation. .brf 11 = set marker interrupt and proceed at end of I/O operation. .spb .unl 10 CHN CMND (pcw.chan_cmd) channel command. .brf 00 = single record data transfer. .brf 02 = nondata transfer. .brf 06 = multirecord data transfer. .brf 10 = single character record data transfer. .spb .unl 10 CHN DATA (pcw.count) channel data as required. .brf (filemark character, backspace count, etc.) .spb .unl 10 CHN NMBR (pcw.channel) the channel to be connected with this PCW. .inl 0 .srv draft "IOM DCW" .ifi l2h "Data Control Word (DCW)" .fin There are three types of data control words: .spb 2 DCW Data Transmission DCW. .brf IDCW Instruction DCW. .brf TDCW Transfer DCW. .all .fif .ifi l3h "Data Transmission DCW" PL/I Declaration (iom_dcw.incl.pl1) .spb dcl 1 dcw based (dcwp) aligned, (2 address bit(18), 2 char_pos bit(3), 2 m64 bit(1), 2 type bit(2), 2 tally bit(12)) unal; .spb 2 .fif .inl 3 0 1 1 2 2 2 2 2 3 _0__________________________________7__8____0__1__2__3__4______________________5__ | | | | | | | ADDRESS | CP |C| T | TALLY | _|____________________________________|______|__|____|________________________| 18 3 1 2 12 .inl 0 .fin .ifi fig "IOM Data Transmission DCW Format" .spb Legend: .spb .inl 10 .unl 10 ADDRESS (dcw.address) data address. .spb .unl 10 CP (dcw.char_pos) character position address (byte size determined by channel). .spb .unl 10 C (dcw.m64) tally control. .brf 0 = word tally. .brf 1 = character tally. .spb .unl 10 T (dcw.type) I/O operation type. .brf 00 = IOTD (transmit and disconnect). .brf 01 = IOTP (transmit and proceed). .brf 11 = IONTP (no transmit and proceed). .spb .unl 10 TALLY (dcw.tally) element (word or character) count. .fif .inl 0 .srv draft "IOM IDCW" .ifi l3h "Instruction DCW" PL/I Declaration (iom_pcw.incl.pl1) .spb dcl 1 idcw based (idcwp) aligned, (2 command bit(6), 2 device bit(6), 2 ext bit(6), 2 code bit(3), 2 ext_ctl bit(1), 2 control bit(2), 2 chan_cmd bit(6), 2 count bit(6)) unal; .spb 2 .fif .inl 3 0 0 0 1 1 1 1 2 2 2 2 2 2 3 3 _0__________5__6__________1__2__________7__8____0__1__2__3__4__________9__0__________5__ | | | | | | | | | | DEV CMND | DEV CODE | ADR EXTN |1 1 1|M| CN| CHN CMND | CHN DATA | _|____________|____________|____________|______|__|____|____________|____________| 6 6 6 3 1 2 6 6 .inl 0 .fin .ifi fig "IOM Instruction DCW Format" .spb Legend: .spb .inl 10 .unl 10 DEV CMND (idcw.command) device command. .spb .unl 10 DEV CODE (idcw.device) device address. .spb .unl 10 ADR EXTN (idcw.ext) address extension for addressing beyond 256K. .spb .unl 10 M (idcw.ext_ctl) address extension control. .brf 1 = reset address extension value. .brf 0 = do not reset address extension value. .spb .unl 10 CN (idcw.control) channel control. .brf 00 = terminate at end of I/O operation. .brf 10 = proceed (list service) at end of I/O operation. .brf 11 = set marker interrupt and proceed at end of I/O operation. .spb .unl 10 CHN CMND (idcw.chan_cmd) channel command. .brf 00 = single record data transfer. .brf 02 = nondata transfer. .brf 06 = multirecord data transfer. .brf 10 = single character record data transfer. .spb .unl 10 CHN DATA (idcw.count) channel data as required. (filemark character, backspace count, etc.). .inl 0 .srv draft "IOM IDCW" .ifi l3h "Transfer DCW" PL/I Declaration (iom_dcw.incl.pl1) .spb dcl 1 tdcw based (tdcwp) aligned, (2 address bit(18), 2 mbz1 bit(4), 2 type bit(2), 2 mbz2 bit(9), 2 ec bit(1), 2 res bit(1), 2 rel bit(1)) unal; .spb 2 .fif .inl 3 0 1 1 2 2 2 2 3 3 3 3 _0__________________________________7__8______1__2__3__4________________2__3__4__5__ | | | | | | | | | ADDRESS |0 0 0 0|1 0|0 0 0 0 0 0 0 0 0|E|I|R| _|____________________________________|________|____|__________________|__|__|__| 18 4 2 9 1 1 1 .inl 0 .fin .ifi fig "IOM Transfer DCW Format" .spb Legend: .spb .inl 10 .unl ADDRESS (tdcw.address) address of next DCW. .unl 10 .spb E (tdcw.ec) address extension control, ORed into LPW "E" bit, (See Figure 3-3 above). .unl .spb I (tdcw.res) IDCW control, ORed into LPW "R" bit (see Figure 3-3 above). .spb .inl 10 .unl 10 R (tdcw.rel) relative addressing control, ORed into LPW "S" bit (see Figure 3-3 above). .inl 0 .srv draft "IOM SCW" .brp .ifi l2h "Status Control Word (SCW)" PL/I Declaration (iom_scw.incl.pl1) .spb dcl 1 scw based (scwp) aligned, (2 address bit(18), 2 lq bit(2), 2 mbz bit(4), 2 tally bit(12)) unal; .spb 2 .fif .inl 3 0 1 1 1 2 2 2 3 _0__________________________________7__8__9__0______3__4______________________5__ | | | | | | ADDRESS | Q |0 0 0 0| TALLY | _|____________________________________|____|________|________________________| 18 2 4 12 .inl 0 .fin .ifi fig "IOM Status Control Word (SCW) Format" .spb Legend: .spb ADDRESS (scw.address) status data address. .spb .inl 10 .unl 10 Q (scw.lq) status queue control. .brf 00 = store status in normal tallying mode. .brf 01 = store status into a 3-word circular queue. .brf 10 = store status into a 32-word circular queue. .brf 11 = reserved. .inl 0 TALLY (scw.tally) status tally count. .brf .inl 0 .ifi l1h "IOM Status Word Formats" .srv draft "IOM STATUS FORMATS" .ifi l2h "System Fault Status" .fin A system fault word is stored as data by the system fault channel (channel 1) of the IOM at the location specified in the fault channel DCW mailbox whenever a system fault is detected by the IOM central. .spb .fif PL/I Declaration (iom_stat.incl.pl1) .spb dcl 1 faultword based (statp) aligned, (2 mbz1 bit(9), 2 channel bit(9), 2 serv_req bit(5), 2 mbz2 bit(3), 2 controller_fault bit(4), 2 io_fault bit(6)) unal; .spb .inl 3 0 0 0 1 1 2 2 2 2 2 2 2 3 3 _0________________8__9________________7__8____0__1__2__3____5__6______9__0__________5__ | | | | | | | | | |0 0 0 0 0 0 0 0 0| CHN | SR |M|D|0 0 0| IAC | FLT CODE | _|__________________|__________________|______|__|__|______|________|____________| 9 9 3 1 1 3 4 6 .inl 0 .fin .ifi fig "IOM System Fault Status Word Format" .spb Legend: .spb .inl 10 .unl 10 .alb CHN (faultword.channel) channel being serviced when the fault was detected. .spb .unl 10 SR, M, D (faultword.serv_req) the SR, M, and D fields are decoded together to indicate the service being performed when the system fault occurred. .spb S_R_ M_ D_ _s_e_r_v_i_c_e .spb 0 x x invalid. .spb 1 1 0 first list service. .brf 0 x normal (^first) list service. .brf 1 1 backup list service. .spb 2 x x status service. .spb 3 x x program interrupt service. .spb 4 0 0 single-precision indirect data load. .brf 0 1 double-precision indirect data load. .spb 5 0 0 single-precision indirect data store. .brf 0 1 double-precision indirect data store. .spb 6 0 0 single-precision direct data load. .brf 0 1 double-precision direct data load. .brf 1 0 direct read and clear data load. .spb 7 0 0 single-precision direct data store. .brf 0 1 double-precision direct data store. .spb .unl 10 IAC (faultword.controller_fault) illegal action code as received from SC or SCU (See "System Controller Illegal Action Codes" in Section!II). .spb .unl 10 FLT CODE (faultword.io_fault) coded IOM central fault. .spb O__c_t_a_l__v_a_l_u_e M__e_a_n_i_n_g .spb .inl +15 .fin .alb .unl 10 00 no fault. .inl 10 .vmh 0 .hla 1 |O__c_t_a_l__v_a_l_u_e M__e_a_n_i_n_g| .hla 2 || .inl 25 .unl 10 .spb .cbn 01 attempt to issue a PCW to an illegal channel number. Channel numbers are 0 through 37(8) or 0 through 77(8) depending on IOM options installed. .cbf .unl 10 .spb 02 a channel requested a service with a service request code of zero, a channel number of zero, .cbn or an illegal channel number (see 01 above). (NOTE: Illegal channel number >_ (40)8 fault is inhibited when IOM is in test.) .cbf .unl 10 .spb 03 parity error on the read data when accessing IOM scratchpad. .unl 10 .spb 04 control word address will be incremented to all zeros (256K overflow) and tally will not be decremented to zero. .unl 10 .spb 05 tally was zero for an update LPW (LPW bit 21 = 0) when the LPW was fetched for the connect channel. .unl 10 .spb 06 DCW fetched for the connect channel did not have bits 18-20 = "111"b. .unl 10 .spb 07 DCW fetched for a data service was a TDCW or had bits 18-20 = "111"b. .unl 10 .spb 10 DCW fetched for a 9-bit channel contained an invalid character position. .unl 10 .spb 11 no response to an interrupt from an SC or SCU within 16.5 microseconds. .spb .unl 10 12 parity error on the read data when accessing an SC or SCU. .spb .unl 10 13 illegal tally control for an LPW (LPW bits 21-22 = "00"b) when the LPW was fetched for the connect channel. .spb .unl 10 14 LPW fetched indicates relative address DCWs (LPW bit 23 = "1"b) while operating in Multics mode. .spb .unl 10 15 fetched a modulo-64 DCW (DCW bit 21 = "1"b) while operating in standard or extended GCOS mode. .spb .unl 10 16 LPW fetched indicates use of address extension (LPW bit 20 = "1"b) while operating in standard GCOS mode. .spb .unl 10 17 no port selected during attempt to access main memory. .inl 0 .ifi l2h "Channel Status" .hla PL/I Declaration (iom_stat.incl.pl1) .spb dcl 1 status based (statp) aligned, (2 t bit(1), 2 power bit(1), 2 major bit(4), 2 sub bit(6), 2 eo bit(1), 2 marker bit(1), 2 soft bit(2), 2 initiate bit(1), 2 abort bit(1), 2 channel_stat bit(3), 2 central_stat bit(3), 2 ext bit(6), 2 rcount bit(6), 2 address bit(18), 2 char_pos bit(3), 2 r bit(1), 2 type bit(2), 2 tally bit(12)) unal; .spb 2 Even Word: .spb .all .fif .inl 3 0 0 0 0 0 1 1 1 1 1 1 1 1 2 2 2 2 2 3 3 _0__1__2______5__6__________1__2__3__4__5__6__7__8____0__1____3__4__________9__0__________5__ | | | | | | | | | | | | | | |1|P| MAJOR | SUBSTATUS |E|M|S/W|I|A| CHN | CEN | ADDREXT | RECORDRES | _|__|__|________|____________|__|__|____|__|__|______|______|____________|____________| 1 1 4 6 1 1 2 1 1 3 3 6 6 .brp .spf 2 .unl 3 Odd Word: .spb 0 1 1 2 2 2 2 2 3 _0__________________________________7__8____0__1__2__3__4______________________5__ | | | | | | | NEXT DATA ADDR | CHR |R| T | DCW TALLY RESIDUE | _|____________________________________|______|__|____|________________________| 18 3 1 2 12 .inl 0 .fin .ifi fig "IOM Channel Status Data Format" .spb Legend: .spb .inl 10 .alb .unl 10 (status.power) device power bit. .brf 0 = device is online and operable. .brf 1 = device is not cabled or is powered off. .spb .unl 10 MAJOR (status.major) device major status (see Section V or Appendix C under the specific device). .spb .unl 10 SUBSTATUS (status.sub) device substatus (see Section V or Appendix C under the specific device). .spb .unl 10 E (status.eo) PSI even/odd bit. .inl +4 .unl 4 0 = termination occurred after the odd word was stored by a PSI channel operating in binary mode. .unl 4 1 = termination occurred after the even word was stored by a PSI channel operating in binary mode. .brf (NOTE: This bit will always be "0" for PSI channels in ASCII mode and for non-PSI channels.) .inl -4 .spb .unl 10 M (status.marker) marker bit. .brf 0 = initiate/terminate status as per "I" bit described below. .brf 1 = marker interrupt status. .spb .unl 10 S/W (status.soft) 2-bit field set to 0's by hardware and available for use by software interrupt handler. .spb .unl 10 I (status.initiate) initiation bit. .brf 0 = terminate/marker status as per "M" bit described above. .brf .inl +4 .unl 4 1 = initiate status in response to a request status (reqs) or reset status (ress) command. .inl -4 .brf .spb .unl 10 A (status.abort) software abort bit (set to 0 by hardware). .spb .unl 10 CHN (status.channel_stat) IOM channel status. .spb .inl +2 .unl 2 V__a_l_u_e M__e_a_n_i_n_g .spb 0 normal. .brf 1 unexpected PCW (connect while busy). .brf 2 invalid channel instruction in PCW. .brf 3 incorrect DCW on list service. .brf 4 incomplete command sequence. .brf 5 unassigned. .brf 6 parity error at peripheral interface. .brf 7 parity error on I/O bus, data _t_o channel. .spb .inl -2 .unl 10 CEN (status.central_stat) IOM central status. .spb .brp .inl +2 .unl 2 V__a_l_u_e M__e_a_n_i_n_g .spb 0 normal. .brf 1 LPW tally runout, not connect channel. .brf 2 two TDCWs. .brf 3 boundary error. .brf 4 address extension change in restricted mode. .brf 5 IDCW in restricted mode. .brf 6 character position/size discrepancy, list service. .brf 7 parity error on I/O bus, data _f_r_o_m channel. .spb .inl 10 .unl 10 ADDREXT (status.ext) address extension value. .spb .unl 10 RECORDRES (status.rcount) residue in PCW or last IDCW record count field. .spb .unl 10 NEXT DATA ADDR .brf (status.address) address of _n_e_x_t data word to be transmitted. .spb .unl 10 CHR (status.char_pos) character position of _n_e_x_t character to be transmitted. .spb .unl 10 R (status.r) read bit. .brf 0 = device is writing. .brf 1 = device is reading. .spb .unl 10 T (status.type) TYPE field of last DCW. .spb .unl 10 DCW TALLY RESIDUE .brf (status.tally) residue in TALLY field of last DCW. .inl 0 .ifi l2h "Special Status" .fin .alb A special status word is stored as data by the special status channel (channel 6) of the IOM whenever the appropriate service request is made by a PSI channel. PSI channels store terminate and marker status through their own channel mailboxes, but store status for special interrupts through the special status channel. .spb .all PL/I Declaration (iom_stat.incl.pl1) .spb dcl 1 special_status based (statp) aligned, (2 t bit(1), 2 channel bit(8), 2 pad1 bit(3), 2 device bit(6), 2 pad2 bit(1), 2 byte2 bit(8), 2 pad3 bit(1), 2 byte3 bit(8)) unal; .spb 2 .inl 3 .fif 0 0 0 0 0 1 1 1 1 2 2 2 3 _0____2__3__________8__9__0______________7__8__9______________6__7__8______________5__ | | | | | | | | | |1 0 0| CHNNO |0| DEVICE |0| HEX1,2 |0| HEX3,4 | _|______|____________|__|________________|__|________________|__|________________| 3 6 1 8 1 8 1 8 .inl 0 .fin .ifi fig "IOM Special Status Word Format" .brp Legend: .spb .alb .inl 10 .unl 10 CHNNO (special_status.channel) the number of the channel storing this special status. .spb .unl 10 DEVICE (special_status.device) the device address of the device causing the special interrupt. .spb .unl 10 HEX1,2 (special_status.byte2) the first 8-bit status byte from the MPC. .spb .unl 10 HEX3,4 (special_status.byte3) the second 8-bit status byte from the MPC. .inl 0 .ifi l3h "Device Special Interrupts" If DEVICE in Figure 3-11 above is nonzero, the special interrupt was caused by a signal from a device attached to the MPC and the status description is as follows: .spb 2 .inl 30 .unl 25 HEX1,2 HEX3,4 .unl 25 (__o_c_t_a_l)_ (__o_c_t_a_l)_ M__e_a_n_i_n_g .unl 25 000 000 printer to run: normal. .unl 25 000 001 disk pack changed or, .brf tape drive(*) malfunction or, .brf reader/punch to ready or, .brf printer to run: print one line. .unl 25 000 002 disk drive released or, .brf tape drive(*) released or, .brf reader/punch released or, .brf printer to run: forward space. .unl 25 .cbn 000 003 printer to run: forward to Top (Top of Page). .cbf .unl 25 000 004 tape drive(*) standby loaded or, .brf printer to run: invalid line. .unl 25 000 005 printer to run: reverse rewind. .unl 25 000 006 printer to run: backspace. .unl 25 .cbn 000 007 printer to run: backspace to Top (Top of Page). .cbf .unl 25 000 010 tape drive(*) to standby. .unl 25 000 020 tape drive(*) to ready. .unl 25 000 040 tape drive(*) unload complete. .unl 25 000 100 tape drive(*) rewind complete. .spb .inl 5 .unl 5 (*) status bits from tape drives may be ORed together to show multiple status conditions. .inl 0 .brp .ifi l3h "Controller Special Interrupts" If DEVICE in Figure 3-11 above is zero, the special interrupt was caused by an internal controller condition and the status description is as follows: .spb 2 .inl 30 .unl 25 HEX1,2 HEX3,4 .unl 25 (__o_c_t_a_l)_ (__o_c_t_a_l)_ M__e_a_n_i_n_g .unl 25 001 000 suspend command accepted. .unl 25 .cbn 001 000 controller suspended (MTD0610) .cbf .unl 25 002 000 release command accepted. .unl 25 .cbn 002 000 controller released (MTP0610) .unl 25 004 000 ITRs overlayed (MTP0610) .cbf .inl 5 .vmh 0 .hla 1 |(__o_c_t_a_l)_ (__o_c_t_a_l)_ M__e_a_n_i_n_g| .hla 2 || .inl 30 .unl 25 004 002 completed Test LAELT or CSELT#1. .unl 25 004 004 completed Test ELT#2. .unl 25 004 005 completed Test CSELT#2. .unl 25 004 006 completed Test MMLT. .unl 25 004 023 completed Test ELT#1. .unl 25 004 121 completed Test CAITR1 for MTS500. .unl 25 004 122 completed Test CAITR2 for MTS500. .unl 25 004 123 completed Test CAITR3 for MTS500. .unl 25 004 146 completed Test BTLT. .unl 25 004 312 completed Test CAITR1 or CAITR2 for DSS181/DSS190. .unl 25 xxx xxx if the first two bits of HEX1,2 are "01"b, then the operator has pressed the INTERRUPT key on the MPC and: .brf For DSS190 or URC - setting of thumbwheel switches. .brf For DSS181 or MTS500 - setting of configuration switches. .inl 0 .fin .hla  bulkstore.compin 10/22/84 1044.8r w 04/23/82 0953.9 140616 .ifi init_mpm "AN87-01" .srv draft "BULK STORE" .srv draft_date "" .srv section 4 .ifi l0h "Level 68 Bulk Store" This section gives the formats of the control words and status words for the bulk store. .ifi l1h "Bulk Store Mailbox Layout" The bulk store mailbox is a dedicated area in main store used for communication with the Bulk Store Subsystem. Its location is determined by the setting of the CONTROL BASE switches for the port group being used by Multics on the bulk store controller (BSC) configuration panel. Multics currently requires this setting to be 1100(8). .all .fif .spb (There is no include file for the declaration of this data.) .spb 2 .inl 19 __________________________________________ .unl 2 0 | | | CURRENT STATUS BLOCK (CSB) | |________________________________________| .unl 2 1 | | | SOFTWARE INFORMATION | |________________________________________| .inl 0 .ifi fig "Bulk Store Mailbox Layout" .ifi l1h "Current Status Block Format" PL/I Declaration .spb 2 Word 0: .spb 2 dcl 1 csb aligned based, 2 dcb_address bit(24) unaligned, 2 rel bit(1) unaligned, 2 mbz bit(6) unaligned, 2 status unaligned, 3 sse bit(1) unaligned, 3 nde bit(1) unaligned, 3 spe bit(1) unaligned, 3 ss bit(1) unaligned, 3 busy bit(1) unaligned, .fif .spb 2 .inl 3 0 2 2 2 3 3 3 3 3 3 _0______________________________________________3__4__5__________0__1__2__3__4__5__ | | | | | | | | | | DCB ADDRESS |A|0 0 0 0 0 0|a|b|c|d|e| _|________________________________________________|__|____________|__|__|__|__|__| 24 1 6 1 1 1 1 1 .inl 0 .ifi fig "Bulk Store Current Status Block (CSB) Format, Word 0" .spb Legend: .spb .inl 20 .unl 20 .fin .alb K__e_y F__i_e_l_d M__e_a_n_i_n_g .spb .unl 10 DCB ADDRESS .brf (csb.dcb_address) address of current data control block (DCB). .spb .unl 10 A (csb.rel) relative/absolute bit. .brf 0 = DCB ADDRESS is relative to mailbox base. .brf 1 = DCB ADDRESS is absolute. .spb .unl 20 a SSE (csb.status.sse) status storage error. .brf The BSC was unable to store status properly. DCB ADDRESS contains the address of the DCB for which status was to be stored. Flag applies to both DCB status block storage (see Figures 4-7 through 4-11 following) and single-word status storage. The BSC has halted and reset the BUSY bit (see below). .spb .unl 20 b NDE (csb.status.nde) next DCB error. .brf The BSC was unable to read the NEXT DCB ADDRESS in the DCB referenced by the CSB. The BSC has stopped and reset the BUSY bit. .spb .unl 20 c SPE (csb.status.spe) status pointer error. .brf The BSC was unable to access and use the DCB status pointer. DCB ADDRESS contains the DCB for which status was to be stored. The BSC has stopped and reset the Busy bit. .spb .unl 20 d SS (csb.status.ss) service started. .brf This bit is set to "1"b by the BSC when it responds to a connect. It remains set until the the completion of the service and then is reset. .spb .unl 20 e BUSY (csb.status.busy) busy. .brf 0 = BSC is stopped. .brf 1 = BSC is busy. .inl 0 .ifi l1h "Data Control Block Format" PL/I Declaration .spb 2 dcl 1 dcb (1), 2 abs_thread bit(24) unaligned, 2 rel bit(1) unaligned, 2 mbz bit(9) unaligned, 2 op_started bit(1) unaligned, 2 mbz1 bit(1) unaligned, 2 status, 3 status_block_ptr bit(23) unaligned, 3 rel bit(1) unaligned, 3 unused bit(10) unaligned, 2 mem_addr bit(24) unaligned, 2 tally bit(12) unaligned, 2 store_addr bit(24) unaligned, 2 control_field unaligned, 3 tis bit(1) unaligned, 3 tad bit(1) unaligned, 3 sps bit(1) unaligned, 3 ieo bit(1) unaligned, 3 seo bit(1) unaligned, 3 mbz bit(1) unaligned, 3 int bit(1) unaligned, 3 dcw bit(1) unaligned, 3 instr bit(3) unaligned, .spb 2 Word 0: .spb .inl 3 .fif 0 2 2 2 3 3 3 _0______________________________________________3__4__5________________3__4__5__ | | | | | | | NEXT DCB |A|0 0 0 0 0 0 0 0 0|a|0| _|________________________________________________|__|__________________|__|__| 24 1 9 1 1 .fin .inl 0 .ifi fig "Bulk Store Data Control Block (DCB) Format, Word 0" .spb Legend: .spb .inl 20 .unl 20 K__e_y F__i_e_l_d M__e_a_n_i_n_g .spb .fin .alb .unl 10 NEXT DCB (dcb.abs_thread) address of next DCB in DCB chain. If address is zero, the BSC stops after completion of this DCB execution. .spb .unl 10 A (dcb.rel) relative/absolute bit. .brf 0 = NEXT DCB is relative to mailbox base. .brf 1 = NEXT DCB is absolute. .spb .unl 20 a (dcb.op_started) op_started. .brf A software flag used by the bulk_store_control program to signal that the DCB is active. .inl 0 .all .fif .spb 2 Word 1: .spb .inl 3 0 2 2 2 3 _0______________________________________________3__4__5____________________5__ | | | | | STATUS ADR |A|0 0 0 0 0 0 0 0 0 0 0| _|________________________________________________|__|______________________| 24 1 11 .inl 0 .ifi fig "Bulk Store Data Control Block (DCB) Format, Word 1" .spb Legend: .spb .inl 10 .unl 10 STATUS ADR .brf (dcb.status.status_block_ptr) address of DCB status block. .spb .unl 10 A (dcb.status.rel) relative/absolute flag. .brf 0 = STATUS ADR is relative to mailbox base. .brf 1 = STATUS ADR is absolute. .fif .inl 0 .spb 2 Word 2: .spb .inl 3 0 2 2 3 _0______________________________________________3__4______________________5__ | | | | MAIN STORE ADR | TALLY | _|________________________________________________|________________________| 24 12 .inl 0 .ifi fig "Bulk Store Data Control Block (DCB) Format, Word 2" .spb .fin Legend: .spb .inl 10 .unl 10 MAIN STORE ADR .brf (dcb.mem_addr) main memory address for data transfer. .spb .unl 10 TALLY (dcb.tally) tally count for data transfer. (See TIS field in Figure 4-6 below for size of increment.) .inl 0 .spb 2 Word 3: .spb .fif .inl 3 0 2 2 2 2 2 2 2 3 3 3 3 _0______________________________________________3__4__5__6__7__8__9__0__1__2______5__ | | | | | | | | | | | | BSU ADR |a|b|c|d|0|e|f|g| CMD | _|________________________________________________|__|__|__|__|__|__|__|__|________| 24 1 1 1 1 1 1 1 1 4 .inl 0 .ifi fig "Bulk Store Data Control Block (DCB) Format, Word 3" .spb Legend: .spb .inl 20 .unl 20 K__e_y F__i_e_l_d M__e_a_n_i_n_g .spb .unl 10 .fin .alb BSU ADR (dcb.store_addr) Bulk Store Unit (BSU) address for data transfer. .spb .unl 20 a TIS (dcb.control_field.tis) tally increment selector. Selects the increment to be used on the TALLY field of DCB Word 2. .brf 0 = 64-word increment. .brf 1 = 1-word increment. .spb .unl 20 b T&D (dcb.control_field.tad) T&D mode indicator. The command in CMD is redefined as a Test & Diagnostic command. .spb .unl 20 c SPS (dcb.control_field.sps) status pointer selector. Used to define the mode of status storage. .brf 0 = store single-word status into DCB, word 1. .inl +4 .unl 4 1 = store DCB status block at address given in DCB, word 1. .inl -4 .spb .unl 20 .inl 0 .vmt 6 .vmh 0 .hla 1 |K__e_y F__i_e_l_d M__e_a_n_i_n_g| .hla 2 || .inl 20 .unl 20 d IOE (dcb.control_field.ioe) interrupt on error. If set, the BSC generates a program interrupt at the completion of DCB execution and status storage if the status is other than SUBSYSTEM READY (See Bulk Store Peripheral Status). .inl 20 .unl 20 .spb e SOE (dcb.control_field.soe) stop on error. If set, the BSC will stop at the completion of DCB execution and status storage if the status is other than SUBSYSTEM READY. .spb .unl 20 f INT (dcb.control_field.int) interrupt. If set, the BSC generates a program interrupt at the completion of DCB execution and status storage. .spb .unl 20 g DCW (dcb.control_field.dcw) DCW control flag. .brf .inl +4 .unl 4 0 = DCB, word 2, is a main store address for data transfer. .unl 4 1 = DCB, word 2, is the main store address of a GCOS type DCW list for data transfer control. .inl -4 .spb .unl 10 CMD (dcb.control_field.inst) coded BSC command. .spb .all .fif 00 nop 02 load configuration 04 load base and limit (not used by Multics) 05 power off enable 06 read configuration 10 write zeros 11 write 12 write conditional 13 write and verify 14 compare 15 read 16 read nontransfer .spb (Undefined commands will cause a BSC abort.) .inl 0 .vmt 6 .vmh 0 .hla .ifi l1h "Bulk Store Status Block Format" .fin (This bulk store status has the same format whether it appears as word 0 of the status block or as word 1 of the DCB.) .all .fif .spb 2 PL/I Declaration .spb dcl 1 dcb status_block, 2 status bit(36), 2 dcw_residue, 3 abs_addr bit(24) unaligned, 3 tally bit(12) unaligned, 2 hardware_indicators bit(36), 2 dcw_pointer bit(36); .spb 2 Word 0: .spb .inl 3 0 0 0 0 0 1 1 1 1 1 1 1 2 2 2 2 2 2 2 3 _0__1__2______5__6__________1__2____4__5__6__7__8____0__1____3__4__5__6__7________________5__ | | | | | | | | | | | | | | |1|0| MAJ | SUBSTATUS | EDAC|0|I|0|0 0 0| ERR |R| T |0 0 0 0 0 0 0 0 0| _|__|__|________|____________|______|__|__|__|______|______|__|____|__________________| 1 1 4 6 3 1 1 1 3 3 1 2 9 .inl 0 .ifi fig "Bulk Store DCB Status Block Format, Word 0" .spb Legend: .spb .inl 10 .unl 10 MAJOR, SUBSTATUS .brf .fin .alb These fields are directly analogous to the MAJOR and SUBSTATUS fields as stored by the IOM. See "Bulk Store Peripheral Status" below for a description of these fields. .spb .unl 10 EDAC error indicators. .spb .unl 10 I initiation interrupt flag. .brf Used only with DCB COMMAND REJECT status (See "Bulk Store Peripheral Status" below). .spb .unl 10 ERR error indicators. .spb .unl 10 R read flag. .brf 0 = data was read from the BSU to main store. .brf 1 = data was written from main store to the BSU. .spb .unl 10 T type code. .brf This field is set to the DCW type if DCWs are used. .all .inl 0 .spb 2 Word 1: .spb .inl 3 .fif 0 3 _0______________________________________________________________________5__ | | | DCW RES | _|________________________________________________________________________| 36 .fin .inl 0 .ifi fig "Bulk Store DCB Status Block Format, Word 1" .spb Legend: .spb .inl 10 .unl 10 DCW RESIDUE .brf .fin .alb This word contains the 24-bit main store address and 12-bit residual tally after the final word of the DCB execution is transmitted. .all .fif .inl 0 .spb 2 Word 2: .spb .inl 3 0 3 _0______________________________________________________________________5__ | | | HARDWARE DIAGNOSTIC INDICATORS | _|________________________________________________________________________| 36 .inl 0 .ifi fig "Bulk Store DCB Status Block Format, Word 2" .spb .brp Word 3: .fif .spb .inl 3 0 3 _0______________________________________________________________________5__ | | |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| _|________________________________________________________________________| 36 .inl 0 .fin .ifi fig "Bulk Store DCB Status Block Format, Word 3" .spb Not used by Multics. .spb 2 Word 4: .fif .fif .spb .inl 3 0 3 _0______________________________________________________________________5__ | | | HARDWARE DIAGNOSTIC INDICATORS | _|________________________________________________________________________| 36 .inl 0 .ifi fig "Bulk Store DCB Status Block Format, Word 4" .ifi l1h "Bulk Store Peripheral Status" The MAJOR and SUBSTATUS fields in Figure 4-7 are interpreted according to the list below. .spb 2 .inl 20 .unl 20 .fin .alb MAJOR SUBSTATUS .spb .unl 20 40 SUBSYSTEM READY. .spb .unl 10 00 subsystem ready. .spb .unl 20 42 SUBSYSTEM ATTENTION. .spb .unl 10 01 hardware write inhibited. .brf A write operation was attempted to a bulk store unit (BSU) that had its WRITE INHIB switch ON. .spb .unl 10 02 no response from BSU. .brf The addressed BSU did not respond within the allowable time. .spb .unl 10 04 error detected in BSU. .brf The selected BSU detected a parity error at the address specified, or the selected BSU was offline or powered down. .spb .unl 10 20 BSU address not present. .brf No BSU is configured for the address specified in the command. .spb .brp .unl 20 43 DATA ALERT. .spb .unl 10 01 uncorrectable BSU data error. .brf One of the following occurred: .inl +4 .unl 4 1. One or more multiple-bit errors were detected in the data transferred from the BSU. .unl 4 2. The hardware EDAC syndrome indicated the wrong BSU location was addressed during a read operation. .unl 4 3. A data parity error was detected when the EDAC function was inactive. .inl -4 .spb .unl 10 02 data parity error. .brf A parity error was detected within the bulk store controller (BSC), by the system controller (SC), or on the BSC/SC interface. .spb .unl 10 04 write conditional inhibited. .brf A write conditional command was attempted but was not executed because the first BSU word addressed did not contain zeros. .spb .unl 10 10 hardware detected control error. .brf One of the following occurred: .inl +4 .unl 4 1. The BSC detected an internal parity error on an address or tally used for data transfer control. .unl 4 2. The SC did not respond to a BSC request within the allowable time. .unl 4 3. The SC reported an illegal action (IA) which was _n_o_t data parity, out-of-bounds, or nonexistent memory. .inl -4 .spb .unl 10 20 write verification failed. .brf A write and verify command was attempted and the data read from the BSU contained uncorrectable errors. .spb .unl 10 40 failed to compare. .brf A compare command was executed and the data did not compare. .spb .unl 20 44 END OF FILE .spb .unl 10 00 The tally in DCB, word 2, (see Figure 4-5 above) exhausted before tally exhaust in a given DCW string. Multics does not use this DCW feature and this status should never be seen. .spb .unl 20 45 DCB COMMAND REJECT. .spb .unl 10 01 invalid command. .brf The BSC is unable to recognize the command code in the DCB. .spb .unl 10 02 DCB parity error. .brf A parity error occurred during the reading of the DCB from main store. .spb .unl 10 04 invalid BSU address. .brf The bulk store unit (BSU) address for data transfer was not 0 modulo 4. .spb .unl 10 10 hardware detected control error. .brf One of the following occurred: .inl +4 .unl 4 1. An error was detected by the BSC while reading the third and fourth words of the DCB. .unl 4 2. An IA other than data parity was returned by the SC during the control sequence. .inl -4 .spb .brp .unl 20 55 DCW REJECT. .spb .unl 10 01 invalid DCW. .brf .spb .unl 10 02 hardware detected data error. .brf .spb .unl 10 04 DCW out of bounds. .brf .spb .unl 10 10 hardware detected control error. .inl 0 .fin .brp  s4.hsf.compin 10/22/84 1044.8r w 06/02/81 0857.9 252963 .ifi init_mpm "AN87-01" .srv section 4 .srv draft "PERIPHERALS" .srv draft_date "" .ifi l0h "Peripherals" This section gives a brief summary of the peripheral devices supported by Multics, the commands for these devices, and the status they return. If more detail is required for a particular status, consult Appendix C. Peripheral status is shown in two ways. The major and substatus is given. In addition, the status is shown in octal as it appears in the four MSD of an IOM status word. .ifi l1h "Peripherals Supported by Multics" The various peripherals supported on the Multics system are listed below. .spb 2 .fif Card Readers CRZ201 .cbn CRU0500 .cbf CRU1050 .spb Card Punches CPZ201 PCU0120 .spb Line Printers PRT201/202 PRT300/301 PRT303 PRU1200/1600 .spb 2 Disk Storage Subsystems DSS181 DSS190/191 NDM400 .cbn DSSA51 MSS0451 MSS0500/0501 .cbf .spb 2 Magnetic Tape Subsystems MTS400 MTS500 .cbn MTS0610 .spb 2 System Consoles CO8030 (IBM) CSU6001 (EMC) CSU6002 (SCC) (SU6601 (LCC) .cbf .fin .brf .brp .ifi l1h "Disk Storage Characteristics" M_S_U_0_4_5_4_ M_S_U_0_4_0_0_ D_S_U_1_9_0_ D_S_U_1_8_1_ .spb 2 .fif sectors per track 40 40 31 18 .spb tracks per cylinder 19 19 19 20 .spb sectors per cylinder 760 760 589 360 .spb cylinders per device 814 410 410 202 .spb sectors per device 618640 311600 241490 72720 .spb Multics records per cylinder 47 47 36 22 .spb Unused sectors per cylinder 8 8 13 8 .spb Multics records per device 38258 19270 14760 4444 .spb Avg. seek time 25ms 30ms 30ms 34ms .spb Avg. Rotational latency 8.3ms 8.3ms 8.3ms 12.5ms .spb Transfer time for Multics records 6.7ms 6.7ms 8.6ms 22.5ms .brf .brp .ifi l1h "Card Reader" .fif C__o_m_m_a_n_d O__c_t_a_l_C__o_d_e .spb Request Status 00 .brf Reset Status 40 .brf Read Card Binary 01 Read Card Alphanumeric 02 Read Card Mixed 03 .spb Read Card ASCII (not in CPL) 04 Read Card ASCII Mixed (not in CPL) 05 Read Card EBCDIC (not in CPL) 06 Read Card Mixed ASCII (not in CPL) 07 Reserve Device (not in CPL) 66 .spb Release Device (not in CPL) 67 Set Native Mode (not in CPL) 65 .spb 2 .fif S__t_a_t_u_s M__a_j_o_r S__u_b_s_t_a_t_u_s O__c_t_a_l .spb Channel Ready 0000 .brf 51-Column Cards 000001 4001 .spb Attention 0010 .brf Off-Line 000000 4200 .brf Hopper/Stacker xxx0x1 4201 .brf Manual Halt xxx01x 4202 .brf Last Batch xxx1x1 4205 .brf .brf Feed Alert 0x10xx 4210 .brf Card Jam x1x0xx 4220 .brf Read Alert 1x00xx 4240 .brf Sneak Feed 1x10xx 4250 .spb Data Alert 0011 .brf Transfer Timing Alert 000001 4301 .brf Validity Alert 000x10 4302 .brf Dual Read Alert 0001x0 4304 No Read Instruction 001000 4310 .spb Command Reject 0101 .brf Invalid Op Code 0000x1 4501 .brf Invalid Device Code 00001x 4502 .brf Parity, IDCW/LC# 000100 4504 .spb MPC Attention 1010 .brf IAI Error 000001 5201 .brf DAI Error 000010 5202 .brf DA Transfer Error 000100 5204 .brf Invalid Punch 001000 5210 .spb MPC Data Alert 1011 .brf Transmission Parity 000001 5301 .brf DAI Error 000101 5305 .spb MPC Command Reject 1101 .brf Illegal Procedure 000001 5501 .brf Illegal LC# 000010 5502 .brf Device Reserved 001000 5510 .brf .brp .ifi l1h "Card Punch" C__o_m_m_a_n_d O__c_t_a_l_C__o_d_e .fif .spb Request Status 00 Reset Status 40 Punch Card Binary 11 Punch Card Alphanumeric 12 Punch Card Edited Alphanumeric 13 .spb Punch Card ASCII (not in CPI version) 14 Punch Card EBCDIC (not in CPI version) 15 Reserve Device (not in CPI version) 66 Release Device (not in CPI version) 67 .spb 2 .fif S__t_a_t_u_s M__a_j_o_r S__u_b_s_t_a_t_u_s O__c_t_a_l .spb Channel Ready 0000 .brf Ready 000000 4000 .spb Attention 0010 .brf Off-Line 000000 4200 .brf Hopper/Stacker 0xxxx1 4201 .brf Manual Halt 0xxx1x 4202 .brf Chad Box Full 0xx1xx 4204 .brf Feed Failure 0x1xxx 4210 .brf Card Jam 01xxxx 4220 .spb Data Alert 0011 .brf Transfer Timing Alert 000xx1 4301 .brf Transmission Parity Alert 000x1x 4302 .brf Punch Alert 0001xx 4304 .spb Command Reject 0101 .brf Invalid Op Code 000001 4501 .brf Invalid Device Code 000010 4502 .brf Parity Error, IDCW/LC# 000100 4504 .spb MPC Attention 1010 .brf IAI Error 000001 5201 .brf DAI Error 000010 5202 .brf DA Transfer Error 000100 5204 .spb MPC Data Alert 1011 .brf Transmission Parity 000001 5301 .brf DAI Error 000101 5305 .brf PSI Data Overflow 000110 5306 .spb MPC Command Reject 1101 .brf Illegal LC# 000010 5502 .brf Illegal Procedure 000001 5501 .brf Device Reserved 001000 5510 .brf .brp .ifi l1h "Printers" C__o_m_m_a_n_d_(_M__o_d_e_l_s_P_R_T_2_0_3_/_3_0_3_,__P_R_U_1_2_0_0_/_1_6_0_0_)_ O__c_t_a_l_C__o_d_e .fif .spb Request Status 00 Reset Status 40 Print Nonedited BCD, Slew Zero Lines 10 Print Nonedited BCD, Slew One Line 11 Print Nonedited BCD, Slew Two Lines 12 .spb Print Nonedited BCD, Slew Top of Page 13 Print Edited BCD, Slew Zero Lines 30 Print Edited BCD, Slew One Line 31 Print Edited BCD, Slew Two Lines 32 Print Edited BCD, Slew Top of Page 33 .spb .brn 10 Print Nonedited ASCII, Slew Zero Lines 14 Print Nonedited ASCII, Slew One Line 15 Print Nonedited ASCII, Slew Two Lines 16 Print Nonedited ASCII, Slew Top of Page 17 Print Edited ASCII, Slew Zero Lines 34 .spb Print Edited ASCII, Slew One Line 35 Print Edited ASCII, Slew Two Lines 36 Print Edited ASCII, Slew Top of Page 37 Slew One Line 61 Slew Two Lines 62 .spb Slew Top of Page 63 Load Image Buffer (ASCII mode only) 01 Read Status 03 Reserve Device 66 Release Device 67 Load VFC Image 05 .spb 2 .fif C__o_m_m_a_n_d_(_M__o_d_e_l_P_R_T_2_0_2_/_3_0_0_)_ O__c_t_a_l_C__o_d_e .spb Print in Edited Mode (data controls slewing) 30 Print in Edited Mode--slew single line 31 Print in Edited Mode--slew double line 32 Print in Edited Mode--slew to Top of Page 33 Print in Nonedited mode--slew no lines 10 .spb Print in Nonedited mode--slew single line 11 Print in Nonedited mode--slew double line 12 Print in Nonedited mode--slew to Top of Page 13 Slew single line--no print 61 Slew double line--no print 62 .spb Slew to Top of Page--no print 63 Load Image Buffer--no slew 14 Reset Status 40 Request Status 00 .spb 2 .brp .fif S__t_a_t_u_s_(_M__o_d_e_l_s_P_R_T_3_0_3_,__P_R_U_1_2_0_0_/_1_6_0_0_)_ M__a_j_o_r S__u_b_s_t_a_t_u_s O__c_t_a_l .spb Ready 0000 .brf Normal 000000 4000 .brf Print One Line 000001 4001 .brf Forward Space 000010 4002 .brf Forward To Top 000011 4003 .brf Invalid Line 000100 4004 .brf Reverse Rewind 000101 4005 .brf Backspace 000110 4006 .brf Backspace Top 000111 4007 .spb .brn 10 Attention 0010 .brf Power Fault 000000 4200 .brf Out of Paper 000001 4201 .brf Manual Halt 000010 4202 .brf VFC Image Error/Tape Alert 000100 4204 .brf Check Alert 001000 4210 .spb Data Alert 0011 .brf Image Buffer Alert/Invalid Character Code 000000 4300 .brf Transfer Timing Alert 0000x1 4301 .brf Alert Before Print 00001x 4302 .brf Alert After Start of Print 000100 4304 .brf Paper Low 001000 4310 .brf Paper Motion Alert/Slew Error 010000 4320 .brf Top of Page Echo 1000x0 4340 .spb Command Reject 0101 .brf No VFC 000000 4500 .brf Invalid Command Code 000xx1 4501 .brf Invalid Device Code 000x1x 4502 .brf Parity error on command or device code 0001xx 4504 .brf No Belt Image 001000 4510 .brf Slew Error on Last Operation 010000 4520 .brf Top of Page Echo on Last Slew 100000 4540 .spb MPC Attention 1010 .brf IAI Error 000001 5201 .brf DAI Error 000010 5202 .spb MPC Data Alert 1011 .brf Transmission Parity 000001 5301 .brf Sum Check Error 000011 5303 .brf DAI Error 000101 5305 .brf PSI Data Overflow 000110 5306 .spb MPC Command Reject 1101 .brf Illegal Procedure 000001 5501 .brf Illegal Logical Channel No. 000010 5502 .brf Device Reserved 001000 5510 .brf .brp .ifi l1h "Operator's Console" .fif C__o_m_m_a_n_d O__c_t_a_l_C__o_d_e .spb Read 03 Write 13 Write Alert 51 Reset Status 40 Request Status 00 Write ASCII 33 Read ASCII 23 T&D Read 07 .spb 2 .fif S__t_a_t_u_s M__a_j_o_r S__u_b_s_t_a_t_u_s O__c_t_a_l .spb Channel Ready 0000 .brf No Substatus 000000 4000 .spb Device Attention 0010 .brf No Substatus 000000 4200 .spb Data Alert 0011 .brf Transfer Timing Error 000001 4301 .brf Transmission Parity Error 0x0010 4302 .brf Operator Input Error 000100 4304 .brf Operator Distracted 001000 4310 .brf Incorrect Format 0100x0 4320 .brf Message Length Alert 100000 4340 .brf .spb Command Reject 0101 .brf Invalid Instruction Code 000001 4501 .brf .brp .ifi l1h "Tape" .fif C__o_m_m_a_n_d O__c_t_a_l_C__o_d_e .spb Request Status 00 Reset Status 40 Request Device Status 50 Reset Device Status 51 Survey Devices 57 .spb Read Control Registers 26 Write Control Registers 16 Set File Protect 62 Set File Permit 63 Rewind 70 .spb Tape Load 75 Rewind/Unload 72 Reserve Device 66 Release Device 67 Set 200 BPI 64 .spb Set 556 BPI 61 or 43 Set 800 BPI 60 or 42 .cbn Set 1600 BPI 65 .cbf Forward Space One Record 44 Forward Space One File 45 .spb Backspace One Record 46 Backspace One File 47 Control Store Overlay 10 Load From Device 05 Erase 54 .spb .brn 10 Write End-of-File Record 55 Write Tape Nine 13 Read Tape Nine 03 Write Binary Record 15 Read Binary Record 05 .spb Reread Binary Record 07 Write BCD Record 14 Read BCD Record 04 Reread BCD Record 06 Write EBCDIC Record 34 .spb Read EBCDIC Record 24 Write ASCII Record 37 Read ASCII Record 27 Write ASCII/EBCDIC Record 35 Read ASCII/EBCDIC Record 25 .spb Diagnostic Mode Control 31 Main Memory Overlay 11 .cbn Set 6250 41 .cbf .spb 2 .brn 11 .fin .fif S__t_a_t_u_s M__a_j_o_r S__u_b_s_t_a_t_u_s O__c_t_a_l .spb Peripheral Subsystem Ready 0000 .brf Ready 000000 4000 Write Protected xx0xx1 4001 Positioned at BOT 000x1x 4002 9-Track Handler xxx1xx 4004 2-Bit Fill 010x0x 4020 4-Bit Fill 100x0x 4040 6-Bit Fill 110x0x 4060 ASCII Alert 001100 4014 .spb Device Busy 0001 In Rewind 000001 4101 Device Reserved 100000 4140 Alternate Channel in Control 000010 4102 Device Loading 000100 4104 .spb Device Attention 0010 Write Protected 00xx01 4201 No Such Handler 000010 4204 Handler in Standby 0xx10x 4204 Handler Check 0x1x0x 4210 Blank Tape on Write 01xx00 4220 .spb Device Data Alert 0011 Transfer Timing Alert 000001 4301 Blank Tape on Read 000010 4302 Bit Detected During Erase Operation xxxx11 4303 Transmission Parity Alert xxx1xx 4304 Lateral Tape Parity Alert xx1xxx 4310 Longitudinal Tape Parity Alert x1xxxx 4320 End of Tape Mark 1xxxxx 4340 .spb End of File 0100 End of File Mark (7-Track) 001111 4417 End of File Mark (9-Track) 010011 4423 Data Alert Condition 111111 4477 Single Character Record xxxxxx 44xx .spb .brn 10 Command Reject 0101 Invalid density 000000 4500 Invalid Op Code 000xx1 4501 Invalid Device Code 000x1x 4502 Invalid IDCW Parity 0001xx 4504 Positioned at Bot 001000 4510 Forward Read After Write 010000 4520 9-Track Error 100000 4540 .spb MPC Device Attention 1010 Configuration Switch Error 000001 5201 Multiple Devices 000010 5202 Illegal Device ID Number 000011 5203 Incompatible Mode 001000 5210 TCA Malfunction 0011xx 5214 MTH Malfunction 010000 5220 Multiple BOT 010001 5221 .spb MPC Device Data Alert 1011 Transmission Alert 000001 5301 Inconsistent Command 000010 5302 Sum Check Error 000011 5303 Byte Locked Out 000100 5304 PE-Burst Write Error 001000 5310 Preamble Error 001001 5311 T&D Error 001010 5312 Multitrack Error 010000 5320 Skew Error 010001 5321 Postamble Error 010010 5322 NRZI CCC Error 010011 5323 Code Alert 010100 5324 Marginal Condition 100000 5340 .spb MPC Command Reject 1101 Illegal Procedure 000001 5501 Illegal LC Number 000010 5502 Illegal Suspended LC Number 000011 5503 Continue Bit Not Set 000100 5504 .brf .brp .fin .ifi l1h "Disks" .fif C__o_m_m_a_n_d O__c_t_a_l_C__o_d_e .spb Seek 34 Special Seek (T&D) 36 Preseek 37 Restore 42 Read 25 .spb Read ASCII 23 Write 31 Write ASCII 32 Write and Compare 33 Read Nonstandard Size 04 .spb Read Track Header 27 Format Track 17 Request Status 00 Reset Status 40 Read Control Register 26 .spb Write Control Register 16 Read Status Register 22 Read EDAC Register 21 Release 76 Reserve Device 77 .spb Set Standby 72 Bootload CS 10 ITR Boot 11 Execute Device Command (DLI) 30 .spb 2 .fif S__t_a_t_u_s M__a_j_o_r S__u_b_s_t_a_t_u_s O__c_t_a_l .spb Channel Ready 0000 No Substatus 000000 4000 Retries (xx = Retry count) 0000xx 400x Device in T&D 0010xx 4010 .spb Busy 0001 Positioning 000000 4100 Alternate Channel 100000 4140 .spb Attention 0010 Write Inhibit 000001 4201 Seek Incomplete 000010 4202 Device Inoperable 001000 4210 Device in Standby 010000 4220 Device Off-Line 100000 4240 .spb Data Alert 0011 Transfer Timing 000001 4301 Transmission Parity 000010 4302 Invalid Seek Address 000100 4304 Header Verification 0x1000 4310 Cyclic Check x1x000 4320 Compare Alert 1x0000 4340 .spb End-of-File 0100 Good Track 000000 4400 Last Consecutive Block 0000x1 4401 Block Count Limit 00001x 4402 Defective Track-Alt. Assg. 000100 4404 Defective Track-No Alt. 001000 4410 Alt. Track Det. 010000 4420 .spb Command Reject 0101 Invalid Op Code 000001 4501 Invalid Device Code 000010 4502 IDCW Parity 000100 4504 Invalid Inst. Sequence 001000 4510 .spb Channel Busy 1000 No substatus xxxxxx 5000 .spb MPC Device Attention 1010 Configuration Error 000001 5201 Multiple Device 000010 5202 Device No. Error 000011 5203 CA Error or OPI Down 001011 5213 Alert EN1 001100 5214 CA EN1 Error 001101 5215 CA Alert (no EN1) 001110 5216 .spb MPC Device Data Alert 1011 Transmission Parity 000001 5301 Inconsistent Command 000010 5302 Sum Check Error 000011 5303 Byte Lockout 000100 5304 EDAC Parity 001110 5316 Sector Size Error 010001 5321 Nonstandard Sector Size 010010 5322 Search Alert (1st) 010011 5323 Cyclic Code (/= 1st) 010100 5324 Search Alert (/= 1st) 010101 5325 Sync Byte /= Hex 19 010110 5326 Error in Alt. Track Processing 010111 5327 EDAC Corr. - Last Sect. 011001 5331 EDAC Corr. /= Last Sect. 011010 5332 EDAC Corr. Block Count Limit 011011 5333 EDAC Uncorrectable 011100 5334 EDAC Corr. Short Block 011101 5335 .spb MPC Command Reject 1101 Illegal Procedure 000001 5501 Illegal Logical Channel Number 000010 5502 Illegal Suspended 000011 5503 Continue Bit Not Set 000100 5504  appa.hsf.compin 10/22/84 1044.8r w 05/22/81 1126.6 27549 .ifi init_mpm "AN87" .srv draft "ACRONYMS" .srv draft_date "" .srv section "A" .ifi l0h "Acronym Definitions" .fif ACU automatic call unit APU appending unit APU-HR appending unit history registers ASCII American Standard Code for Information Interchange AST active segment table BAR base address register BAW base address word BCD Binary-Coded Decimal BOS Bootload Operating System BOT beginning of tape BSC bulk store controller BSU bulk store unit CA controller adapter CCC character control character CCT character control table CPI common peripheral interface CPU central processor unit CSB current status block CU control unit CU-HR control unit history registers DA device adapter DAI device adapter interface DBR descriptor base register DCB data control block DCW data control word DIA direct interface adapter DLI device level interface DSBR descriptor segment base register (usually referred to as DBR) DU decimal unit DU-HR decimal unit history registers EBCDIC Extended Binary-Coded Decimal Interchange Code EDAC error detection and correction EIA Electronic Industries Association EIMA execute interrupt mask assignment EIS extended instruction set EOF end of file ESC escape ESN effective segment number FIM fault intercept module FNP DATANET 6600 Front-End Network Processor or DATANET 355 Front-End Network Processor HSLA high-speed line adapter IA illegal action IAI internal adapter interface ICT instruction counter ICW indirect control word IDCW instruction DCW IMW interrupt multiplex word IOC illegal opcode IOM input/output multiplexer IPR illegal procedure IPS interprocess signal ITP indirect-to-pointer (pointer pair) ITS indirect-to-segment (pointer pair) LPW list pointer word LSB least significant bit(s) LSD least significant digit(s) LSLA low-speed line adapter MF modification field MFM modified frequency modulation MOS metal oxide semiconductor MPC microprogrammed peripheral controller MSB most significant bit(s) MSD most significant digit(s) NRZI nonreturn to zero; change on ones (tape drive modes) OPI operational-in (line) OU operations unit OU-HR operations unit history registers PCW peripheral control word PE phase encoded (tape drive modes) PRNUM pointer register number PRR procedure ring register PSI peripheral subsystem interface PSR procedure segment register PTW page table word PTWAM page table word associative memory RPS rotational position sensing RSCR read system controller registers RSR read status register (MPC command) SC system controller SCU store control unit SCW status control word SDW segment descriptor word SDWAM segment descriptor word associative memory SNR segment number register (part of pointer register) SST system segment table T&D test and diagnostics TCA tape controller adapter TDCW transfer DCW TPR temporary pointer register TRR temporary ring register TSR temporary segment register URC unit record controller URMPC unit record microprogrammed peripheral controller VFC vertical format control VFU vertical format unit ZAC zone address control .fin .brp .inl 0  appb.hsf.compin 10/22/84 1044.9r w 05/22/81 1127.8 140373 .ifi init_mpm "AN87-01" .srv section "B" .srv draft_date "" .ifi l0h "Data and Control Word Formats" This appendix consists of information described in more detail in other sections of this manual. The information is repeated here to provide a quick and easy reference for user convenience. .spb 2 .srv draft "IOM FORMATS" Even Word: .spb .fif .inl 3 0 0 0 1 1 1 1 2 2 2 2 2 2 3 3 _0__________5__6__________1__2__________7__8____0__1__2__3__4__________9__0__________5__ | | | | | | | | | | DEV CMND | DEV CODE | ADR EXTN |1 1 1|M| CN| CHN CMND | CHN DATA | _|____________|____________|____________|______|__|____|____________|____________| 6 6 6 3 1 6 6 .spb 2 .unl 3 Odd Word: .spb 0 0 0 0 0 3 _0____2__3__________8__9____________________________________________________5__ | | | | |0 0 0| CHN NMBR |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| _|______|____________|______________________________________________________| 3 6 27 .spb .bbe 1 ||IOM PCW & DCW Format|| .spb .fif .inl 3 0 0 0 1 1 1 1 2 2 2 2 2 2 3 3 _0__________5__6__________1__2__________7__8____0__1__2__3__4__________9__0__________5__ | | | | | | | | | | DEV CMND | DEV CODE | ADR EXTN |1 1 1|M| CN| CHN CMND | CHN DATA | _|____________|____________|____________|______|__|____|____________|____________| 6 6 6 3 1 2 6 6 .spb .bbe 1 ||IOM DCW Format|| .spb 2 .fif .inl 3 0 1 1 2 2 2 2 2 3 _0__________________________________7__8____0__1__2__3__4______________________5__ | | | | | | | ADDRESS | CP |C| T | TALLY | _|____________________________________|______|__|____|________________________| 18 3 1 2 12 .inl 0 .spf .bbe 1 ||IOM TDCW Format|| .ifi fig "IOM Formats" .brp .inl 3 .fif 0 1 1 1 2 2 2 2 2 3 _0__________________________________7__8__9__0__1__2__3__4______________________5__ | | | | | | | | | | DCW (PCW) PTR |R|H|E|N|T|S| TALLY | _|____________________________________|__|__|__|__|__|__|________________________| 18 1 1 1 1 1 1 12 .spb .bbe 1 ||IOM LPW Format|| .fif .spb .spb 0 0 0 1 2 3 _0________________8__9________________7__8__________________________________5__ | | | | | LOW BND | SIZE | IDCW PTR | _|__________________|__________________|____________________________________| 9 9 18 .spb .inl 0 .bbe 1 ||IOM LPW Extension Format|| .spb 2 .fif .inl 3 0 1 1 1 2 2 2 3 _0__________________________________7__8__9__0______3__4______________________5__ | | | | | | ADDRESS | Q |0 0 0 0| TALLY | _|____________________________________|____|________|________________________| 18 2 4 12 .spb .fin .inl 0 .bbe 1 ||IOM SCW Format|| .spb 2 Even Word: .spb .all .fif .inl 3 0 0 0 0 0 1 1 1 1 1 1 1 1 2 2 2 2 2 3 3 _0__1__2______5__6__________1__2__3__4__5__6__7__8____0__1____3__4__________9__0__________5__ | | | | | | | | | | | | | | |1|P| MAJOR | SUBSTATUS |E|M|S/W|I|A| CHN | CEN | ADDREXT | RECORDRES | _|__|__|________|____________|__|__|____|__|__|______|______|____________|____________| 1 1 4 6 1 1 2 1 1 3 3 6 6 .spb 2 .unl 3 Odd Word: .spb 0 1 1 2 2 2 2 2 3 _0__________________________________7__8____0__1__2__3__4______________________5__ | | | | | | | NEXT DATA ADDR | CHR |R| T | DCW TALLY RESIDUE | _|____________________________________|______|__|____|________________________| 18 3 1 2 12 .spb .inl 0 .bbe 1 ||IOM Status Format|| .spb 2 .fif .inl 3 0 0 0 1 1 2 2 2 2 2 2 2 3 3 _0________________8__9________________7__8____0__1__2__3____5__6______9__0__________5__ | | | | | | | | | |0 0 0 0 0 0 0 0 0| CHN | SR |M|D|0 0 0| IAC | FLT CODE | _|__________________|__________________|______|__|__|______|________|____________| 9 9 3 1 1 3 4 6 .spb 2 .inl 0 .bbe 1 ||Figure B-1 (cont). IOM Formats|| .brp .srv draft "BULK STORE FORMATS" .spb 3 .fif 0 2 2 2 3 3 3 0_______________________________________________3__4__5________________3__4__5__ | | | | | | | NEXT DCB |A|0 0 0 0 0 0 0 0 0|a|0| Word 0 _|________________________________________________|__|__________________|__|__| 24 1 9 1 1 .spb 0 2 2 2 3 0_______________________________________________3__4__5____________________5__ | | | | | STATUS ADDRESS |A|0 0 0 0 0 0 0 0 0 0 0| Word 1 _|________________________________________________|__|______________________| 24 1 11 .spb 0 2 2 3 0_______________________________________________3__4______________________5__ | | | | MAIN STORE ADDRESS | TALLY | Word 2 _|________________________________________________|________________________| 24 12 .spb 0 2 2 2 2 2 2 2 3 3 3 3 0_______________________________________________3__4__5__6__7__8__9__0__1__2______5__ | | | | | | | | | | | | BSU ADDRESS |a|b|c|d|0|e|f|g| CMD | Word 3 _|________________________________________________|__|__|__|__|__|__|__|__|________| 24 1 1 1 1 1 1 1 1 4 .ifi fig "Bulk Store Data Control Block (DCB) Format" .fif .spb 0 0 0 0 0 1 1 1 1 1 1 1 2 2 2 2 2 2 2 3 0___1__2______5__6__________1__2____4__5__6__7__8____0__1____3__4__5__6__7________________5__ | | | | | | | | | | | | | | |1|0| MAJ | SUBSTATUS | EDAC|0|I|0|0 0 0| ERR |R| T |0 0 0 0 0 0 0 0 0| Word 0 _|__|__|________|____________|______|__|__|__|______|______|__|____|__________________| 1 1 4 6 3 1 1 1 3 3 1 2 9 .spb 0 3 0_______________________________________________________________________5__ | | | DCW RESIDUE | Word 1 _|________________________________________________________________________| 36 .spb 0 3 0_______________________________________________________________________5__ | | | HARDWARE DIAGNOSTIC INDICATORS | Word 2 _|________________________________________________________________________| 36 .spb (ALL ZEROS) Word 3 .spb 0 3 0_______________________________________________________________________5__ | | | HARDWARE DIAGNOSTIC INDICATORS | Word 4 _|________________________________________________________________________| 36 .ifi fig "Bulk Store DCB Status Block Format" .brp .fif 0 2 2 2 3 3 3 3 3 3 0_______________________________________________3__4__5__________0__1__2__3__4__5__ | | | | | | | | | | DCB ADDRESS |A|0 0 0 0 0 0|a|b|c|d|e| Word 0 _|________________________________________________|__|____________|__|__|__|__|__| 24 1 6 1 1 1 1 1 .ifi fig "Bulk Store Current Status Block (CSB) Format" .spb .srv draft "DU FORMATS" .fif 0 0 0 1 1 1 3 0_________________8__9__0__1__2______________________________________________5__ | | | | | | |0 0 0 0 0 0 0 0 0|Z|/O|0| CH TALLY | Word 0 1___________________|__|__|__|________________________________________________| 9 1 1 1 24 .spb (ALL ZEROS) Word 1 .spb 0 2 2 2 2 2 2 3 3 3 3 3 0_______________________________________________3__4__5__6__7____9__0__1__2__3____5__ | | | | | | | | | | D1 POINTER |0|TA |0 0 0|I|F|A|0 0 0| Word 2 _|________________________________________________|__|____|______|__|__|__|______| 24 1 2 3 1 1 1 3 .spb 0 0 1 1 1 3 0___________________9__0__1__2______________________________________________5__ | | | | | LEVEL |0 0| D1 RESIDUE | Word 3 _|____________________|____|________________________________________________| 10 2 24 .spb 0 2 2 2 2 2 2 3 3 3 3 3 3 0_______________________________________________3__4__5__6__7____9__0__1__2__3__4__5__ | | | | | | | | | | | | D2 POINTER |0|TA |0 0 0|R|f|A|0|F|D| Word 4 _|________________________________________________|__|____|______|__|__|__|__|__|__| 24 1 2 3 1 1 1 1 1 1 .spb 0 1 1 3 0_______________________1__2______________________________________________5__ | | | |0 0 0 0 0 0 0 0 0 0 0 0| D2 RESIDUE | Word 5 _|________________________|________________________________________________| 12 24 .spb 0 2 2 2 2 2 2 3 3 3 3 3 0_______________________________________________3__4__5__6__7____9__0__1__2__3____5__ | | | | | | | | | | D3 POINTER |0|TA |0 0 0|R|F|A| JMP | Word 6 _|________________________________________________|__|____|______|__|__|__|______| 24 1 2 3 1 1 1 3 .spb 0 1 1 3 0_______________________1__2______________________________________________5__ | | | |0 0 0 0 0 0 0 0 0 0 0 0| D3 RESIDUE | Word 7 _|________________________|________________________________________________| 12 24 .ifi fig "DU Pointers and Lengths Format" .brp .fif .srv draft "SCU DATA FORMAT" 0 0 0 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3 3 3 0_____2__3____________________________7__8__9__0__1__2__3__4__5__6__7__8__9__0__1__2______5__ | | | | | | | | | | | | | | | | | | | | PRR | PSR |a|b|c|d|e|f|g|h|i|j|k|l|m|n|o| FCT | Word 0 _|______|______________________________|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|______| 3 15 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3 .spb 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 3 3 3 0___1__2__3__4__5__6__7__8__9__0__1__2__3__4__5__6__7__8__9__0______3__4____6__7____9__0________4__5__ | | | | | | | | | | | | | | | | | | | | | | | | | | |a|b|c|d|e|f|g|h|i|j|k|l|m|n|o|p|q|r|s|t| IA |IACHN|CNCHN| F/I ADDR|u| Word 1 _|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|________|______|______|__________|__| 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 4 3 3 5 1 .spb 0 0 0 1 1 2 2 2 3 3 0_____2__3____________________________7__8__________________7__8__9__0__________5__ | | | | | | | TRR | TSR |0 0 0 0 0 0 0 0 0 0|CPU| DELTA | Word 2 _|______|________________________________|____________________|____|____________| 3 15 10 2 6 .spb 0 1 1 2 2 2 2 2 3 3 0___________________________________7__8______1__2______5__6______9__0__________5__ | | | | | | |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| TSNA | TSNB | TSNC | TEMP BIT | Word 3 _|____________________________________|________|________|________|____________| 18 4 4 4 6 .spb 0 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3 3 3 0___________________________________7__8__9__0__1__2__3__4__5__6__7__8__9__0__1__2______5__ | | | | | | | | | | | | | | | | | | ICT |a|b|c|d|e|f|g|h|i|j|k|l|m|n|0 0 0 0| Word 4 _|____________________________________|__|__|__|__|__|__|__|__|__|__|__|__|__|__|________| 18 1 1 1 1 1 1 1 1 1 1 1 1 1 1 4 .spb 0 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3 0___________________________________7__8__9__0__1__2__3__4__5__6__7__8__9__0__________5__ | | | | | | | | | | | | | | | | COMPUTED ADDRESS |a|b|c|d|e|f|g|h|i|j|k|l| CT HOLD | Word 5 _|____________________________________|__|__|__|__|__|__|__|__|__|__|__|__|____________| 18 1 1 1 1 1 1 1 1 1 1 1 1 1 6 .spb 0 1 1 2 2 2 3 3 0___________________________________7__8__________________7__8__9__0__________5__ | | | | | | | ADDRESS | OPCODE |I|P| TAG | Word 6 _|____________________________________|____________________|__|__|____________| 18 10 1 1 6 .spb 0 1 1 2 2 2 3 3 0___________________________________7__8__________________7__8__9__0__________5__ | | | | | | | ADDRESS | OPCODE |I|P| TAG | Word 7 _|____________________________________|____________________|__|__|____________| 18 10 1 1 6 .ifi fig "SCU Data Format" .fif .brp .srv draft "FAULT NUMBERS" .ifi tab "Processor Fault Numbers" .spb 2 .inl 5 F/I ADDR O__c_t D__e_c _i_n_S_C_U___d_a_t_a N__a_m_e M__n_e_m_o_n_i_c P__r_i_o_r_i_t_y G__r_o_u_p M__o_d_e .spb 0 0 01 Shutdown sdf 27 VII M/G 1 1 03 Store str 10 IV M/G 2 2 05 Master Mode Entry 1 mme1 11 V M/G 3 3 07 Fault Tag 1 ftg1 17 V M/G .spb 4 4 11 Timer Runout tro 26 VI M/G 5 5 13 Command cmd 9 IV M/G 6 6 15 Derail drl 15 V M/G 7 7 17 Lockup luf 5 IV M/G .spb 10 8 21 Connect con 25 VII M/G 11 9 23 Parity par 8 IV M/G 12 10 25 Illegal Procedure ipr 16 V M/G 13 11 27 Op Not Complete onc 4 II M/G .spb 14 12 31 Startup suf 1 I M/G 15 13 33 Overflow ofl 7 III M/G 16 14 35 Divide Check dvck 6 III M/G 17 15 37 Execute exc 2 I M/G .spb 20 16 41 Directed Fault 0 dft0 20 VI M 21 17 43 Directed Fault 1 dft1 21 VI M 22 18 45 Directed Fault 2 dft2 22 VI M 23 19 47 Directed Fault 3 dft3 23 VI M .spb 24 20 51 Access Violation acv 24 VI M 25 21 53 Master Mode Entry 2 mme2 12 V M 26 22 55 Master Mode Entry 3 mme3 13 V M 27 23 57 Master Mode Entry 4 mme4 14 V M .spb 30 24 61 Fault Tag 2 ftg2 18 V M 31 25 63 Fault Tag 3 ftg3 19 V M 32 26 65 Unassigned 33 27 67 Unassigned .spb 34 28 71 Unassigned 35 29 73 Unassigned 36 30 75 Unassigned 37 31 77 Trouble trb 3 II M .inl .fin .brp  appc.hsf.compin 10/22/84 1044.9r w 06/26/81 1057.1 749916 .ifi init_mpm "AN87" .srv section "C" .ifi l0h "Peripheral Status" This section describes the MAJOR and SUBSTATUS fields of the IOM channel status data shown in Figure 3-10. MAJOR and SUBSTSATUS in this section are given in octal form. .sr draft "CARD READER STATUS" .ifi l1h "Card Readers" If the device is a card reader, the MAJOR and SUBSTATUS fields are interpreted according to the list below. Substatuses marked with an asterisk (*) may be ORed within the same major status. .spb 2 .inl 20 .unl 20 MAJOR SUBSTATUS .spb .unl 20 40 CHANNEL READY. .spb .unl 10 00 channel ready. If received as an initiation interrupt (I = "1") in response to a reqs or ress command, the channel and device are ready to accept a new command. If received as a termination interrupt, the last command was executed error free and the channel and device are ready to accept a new command. .spb .unl 10 01 (CRU1050) 51-column cards. .brf As above except that the input card hopper contains 51-column cards. .spb .unl 20 41 DEVICE BUSY. .spb .unl 10 00 (CRZ201) one the following occurred: .inl +3 .unl 3 1. A "feed" or "stack" command was being executed and a reqs or ress command was received. .unl 3 2. A "feed" command was being executed and another feed command was received. .unl 3 3. A "stack" command was being executed and another stack command was received. .unl 3 4. A command was received with a card in the read head. .inl -3 .spb .unl 20 42 ATTENTION. .spb .unl 10 00 (CRU1050) offline (device power off). .brf The unit record controller (URC) MPC could not communicate with the device. The operational-in (OPI) line of the device adapter interface (DAI) is reset. .brp .spb .unl 10 01* (CRZ201) hopper/stacker alert. .brf One or more the followed occurred: .inl +3 .unl 3 1. The feed hopper was empty. .unl 3 2. One or both stackers were full. .unl 3 3. The 51- or 80-column card guides were not set alike or were not properly locked in place. .unl 3 4. A card should have been stacked in the auxiliary stacker but was not. .inl -3 .spb (CRU1050) hopper/stacker alert. .brf The input card hopper is empty and/or the output card stacker is full. .spb .unl 10 02* manual halt. .brf The MANUAL HALT switch has been pressed or a safety interlock is open. .spb .unl 10 05* (CRZ201) last batch. .brf The LAST BATCH switch has been pressed _a_n_d the input card hopper is empty. .spb .unl 10 10* feed alert. .brf The next card from the input hopper failed to feed properly. .spb .unl 10 20* card jam. .brf The trailing edge of a card failed to reach a photocell station in the card track within the specified time after the detection of the leading edge of the card at the station. .spb .unl 10 40* (CRZ201) read alert. .brf One or more of the following occurred: .inl +3 .unl 3 1. read photocell light current error. .unl 3 2. read photocell dark current error. .unl 3 3. read strobe count error. .unl 3 4. card-in-head error. .unl 3 5. internal parity error. .unl 3 6. read error test check failure. .inl -3 .spb (CRU1050) read alert. .brf One or more of the following occurred: .inl +3 .unl 3 1. read photocell light current error. .unl 3 2. read photocell dark current error. .unl 3 3. read strobe count error. .unl 3 4. card-in-head timing error. .inl -3 .spb .unl 10 50* (CRZ201) sneak feed. .brf Prior to receipt of the current command, one or more cards passed through the card reader without a command having been given. .spb .unl 20 43 DATA ALERT. .spb .unl 10 01 (CRZ201) transfer timing alert. .brf The IOM failed to accept (read) data characters at a rate compatible with the transfer rate of the card reader. .spb .unl 10 02* validity alert. .brf During execution of a "read card decimal" command, an invalid character was detected. An ignore character ("?" = 17(8)) is stored in the card image in place of each invalid character. .spb .unl 10 04* dual read failure. .brf A discrepancy was detected in the contents of a card column as read by the dual read head of the card reader. In decimal mode, an ignore character ("?" = 17(8)) is stored in the card image in place of the invalid column. In binary mode, _t_w_o ignore characters are stored in place of the invalid column. .spb .unl 10 10 (CRZ201) no read command. .brf A card fed by a "feed card" command entered the read station before a "read" command was received. The "read" command must be received within 9 milliseconds of the preceding "feed card" command. .spb .unl 20 45 COMMAND REJECT. .spb .unl 10 01 invalid command. .brf The device is unable to recognize the command code in the PCW or IDCW. .spb .unl 10 02 (CRZ201) no card committed. .brf A stack command was received at a time other than within 6 milliseconds after a card left the read head. .spb (CRU1050) invalid device code. .brf The device code specifies a device that is not configured. .spb .unl 10 04 (CRZ201) late read command. .brf A "read" command was received after a card entered the read station. Also see DATA ALERT, substatus 10, no "read" command described above. .spb (CRU1050) IDCW parity. .brf A parity error occurred on the logical channel number field in an IDCW from the IOM. .spb .unl 20 47 LOAD OPERATION COMPLETE. .spb .unl 10 00 (CRZ201) load complete. .brf A load card (boot) sequence has completed with no DATA ALERT or ATTENTION conditions. .spb .unl 20 52 MPC DEVICE ATTENTION. .spb .unl 10 01 (CRU1050) IAI error. .brf A parity error was detected on the internal adapter interface (IAI) between the multiplexer adapter and the URMPC. .spb .unl 10 02 (CRU1050) DAI error (no media movement). .brf One of the following was detected on the device adapter interface (DAI) between the URMPC and the device adapter (DA): .brf 1. Parity error detected by the DA. .brf 2. Parity error detected by the URMPC. .brf 3. Error timeout detected by the URMPC. .spb .unl 10 04 (CRU1050) DA transfer error. .brf A timing error was detected by the DA during device operation. .spb .unl 10 10 (CRU1050) invalid punch. .brf An invalid decimal punch combination (two or more punches in rows 1-7) was detected by the DA. No character substitution is made in the card image. .spb .unl 20 53 MPC DEVICE DATA ALERT. .spb .unl 10 01 (CRU1050) transmission parity error. .brf A parity error was detected by the peripheral subsystem interface (PSI) during transfer of data from the IOM to the URMPC. .spb .unl 10 05 (CRU1050) DAI error (with media movement). .brf One of the following was detected on the DAI between the URMPC and the DA: .brf 1. Parity error detected by the DA. .brf 2. Parity error detected by the URMPC. .brf 3. Error timeout detected by the URMPC. .spb .unl 20 55 MPC COMMAND REJECT. .spb .unl 10 01 (CRU1050) illegal procedure. .brf The URMPC is in suspend mode and will accept only special controller commands. .spb .unl 10 02 (CRU1050) illegal logical channel number. .brf The logical channel number sent with an IDCW was illegal (not 00-07 hexadecimal). .spb .unl 10 10 (CRU1050) device reserved. .brf The device requested is reserved to another PSI and is not available for use. .spb .unl 20 60 POWER OFF. .spb .unl 10 00 (CRZ201) power off. .brf The device is powered off or is not cabled to the CPI channel in the IOM. .spb (CRU1050) power off. .brf The URMPC is powered off, is not cabled to the PSI channel in the IOM, or has lost its personality firmware. .inl 0 .sr draft "CARD PUNCH STATUS" .ifi l1h "Card Punches" For a card punch, the MAJOR and SUBSTATUS fields are interpreted in the following manner. Substatuses marked with an asterisk (*) may be ORed within the same major status. .inl 20 .unl 20 .spb 2 MAJOR SUBSTATUS .spb .unl 20 40 CHANNEL READY. .spb .unl 10 00 channel ready. .brf If received as an initiation interrupt (I = "1") in response to a reqs or ress command, the channel and device are ready to accept a new command. If received as a termination interrupt, the last command was executed error free and the channel and device are ready to accept a new command. .spb .unl 20 42 ATTENTION. .spb .unl 10 00 (PCU0120) offline. .brf The unit record controller (URC) MPC could not communicate with the device. The operational-in (OPI) line of the device adapter interface (DAI) is reset. .spb .unl 10 01* hopper/stacker alert. .brf The input card hopper is empty and/or the output card stacker is full. .spb .unl 10 02* manual halt. .brf The MANUAL HALT switch has been pressed or a safety interlock is open. .spb .unl 10 04* chad box full. .brf The chad receptacle is full. .spb .unl 10 10* feed failure. .brf A card from the input hopper failed to feed into the punch mechanism. .spb .unl 10 20* card jam. .brf One or more cards were improperly loaded in the input hopper or a card failed to progress at the proper time from one station to the next in the card track. .spb .unl 20 43 DATA ALERT. .spb .unl 10 00 or 01* (CPZ201) transfer timing alert. .brf The IOM did not send (write) data characters at a rate compatible with the transfer rate of the card punch. .spb .unl 10 02* (CPZ201) transmission parity alert. .brf A parity error was detected on a data character received from the IOM. .spb .unl 10 04* (CPZ201) punch alert. .brf A count of holes punched in a card was compared with a calculated hole count and the counts did not agree. .spb .unl 10 10 (PCU0120) punch alert. .brf A count of holes punched in a card was compared with a calculated hole count and the counts did not agree. .spb .unl 20 45 COMMAND REJECTED. .spb .unl 10 01 invalid command. .brf The channel is unable to recognize the device command code in the PCW or IDCW. .spb .unl 20 52 MPC DEVICE ATTENTION. .spb .unl 10 01 (PCU0120) IAI error. .brf A parity error was detected on the internal adapter interface (IAI) between the multiplexer adapter and the URMPC. .spb .unl 10 02 (PCU0120) DAI error. .brf One of the following was detected on the device adapter interface (DAI) between the URMPC and the device adapter (DA): .brf 1. Parity error detected by the DA. .brf 2. Parity error detected by the URMPC. .brf 3. Error timeout detected by the URMPC. .spb .unl 10 04 (PCU0120) DA transfer error. .brf A timing error was detected by the DA during device operation. .spb .unl 20 53 MPC DEVICE DATA ALERT. .spb .unl 10 01 (PCU0120) transmission parity error. .brf A parity error was detected by the peripheral subsystem interface (PSI) during transfer of data from the IOM to the URMPC. .spb .unl 10 05 (PCU0120) DAI error. .brf One of the following was detected on the DAI between the URMPC and the DA: .brf 1. Parity error detected by the DA. .brf 2. Parity error detected by the URMPC. .brf 3. Error timeout detected by the URMPC. .spb .unl 10 06 (PCU0120) PSI data overflow. .brf More than 256 characters were received from the IOM. .spb .unl 20 55 MPC COMMAND REJECT. .spb .unl 10 01 (PCU0120) illegal procedure. .brf The URMPC is in suspend mode and will accept only special controller commands. .spb .unl 10 02 (PCU0120) invalid logical channel number. .brf The logical channel number sent with an IDCW was invalid (not 00-07 hexadecimal). .spb .unl 10 10 (PCU0120) device reserved. .brf The device requested is reserved to another PSI and is not available for use. .spb .unl 20 60 POWER OFF. .spb .unl 10 00 (CPZ201) power off. .brf The device is powered off or is not cabled to the CPI channel of the IOM. .spb (PCU0120) power off. .brf The URMPC is powered off, is not cabled to the PSI channel of the IOM, or has lost its personality firmware. .inl 0 .sr draft "PRINTER STATUS" .ifi l1h "Line Printers" For a line printer, the MAJOR and SUBSTATUS fields are interpreted in the following manner. Substatuses marked with an asterisk (*) may be ORed within the same major status. .spb 2 MAJOR SUBSTATUS .spb .inl 20 .unl 20 40 CHANNEL READY. .spb .unl 10 00 channel ready. .brf If received as an initiation interrupt (I = "1") in response to a reqs or ress command, the channel and device are ready to accept a new command. If received as a termination interrupt, the last command was executed error free and the channel and device are ready to accept a new command. .spb .unl 10 01 print one line. .brf Same as substatus 00; in addition printer control button 1 (PRINT 1 LINE) has been activated. .spb .unl 10 02 forward space. .brf Same as substatus 00; in addition printer control button 2 (FORWARD SPACE) has been activated. .spb .unl 10 03 forward to top of page. .brf Same as substatus 00; in addition printer control button 3 (FORWARD TOP) has been activated. .spb .unl 10 04 invalid line. .brf Same as substatus 00; in addition printer control button 4 (INVALID LINE) has been activated. .spb .unl 10 05 reverse/rewind. .brf Same as substatus 00; in addition printer control button 5 (REVERSE REWIND) has been activated. .spb .unl 10 06 backspace. .brf Same as substatus 00; in addition printer control button 6 (BACK SPACE) has been activated. .spb .unl 10 07 backspace top of page. .brf Same as substatus 00; in addition printer control button 7 (BACK SPACE TOP) has been activated. .spb .unl 20 42 ATTENTION. .spb .unl 10 00 (PRT300/301) power fault. .brf One of the following has occurred: .inl +4 .unl 4 1. A thermal fault. .unl 4 2. A printer power fault. .unl 4 3. A feed fault. .unl 4 4. A power ON/OFF sequence. .unl 4 5. The printer is powered off. .inl -4 .spb (PRT303) power fault. .brf One of the following has occurred: .inl +4 .unl 4 1. A thermal fault in the printer mechanism. .unl 4 2. Power not on in device electronics. .unl 4 3. Power fault in the 36 volt supply. .unl 4 4. Power fault in the printer mechanism. .unl 4 5. Power fault in the -5 or -12 volt supplies. .inl -4 .spb (PRU1200/PRU1600) power fault. .brf One of the following has occurred: .inl +4 .unl 4 1. A thermal fault in the printer mechanism .unl 4 2. Power not on in device electronics. .unl 4 3. Print power supply fault. .unl 4 4. Slew power supply fault. .unl 4 5. Phase fault on AC primary line. .unl 4 6. Short circuit fault on hammer drivers. .unl 4 7. Finger sensor fault. .unl 4 8. Breaker AC. .unl 4 9. Air flow check. .inl -4 .spb .unl 10 01* out of paper. .brf One of the following has occurred: .inl +4 .unl 4 1. The forms detectors failed to sense the presence of a form. .unl 4 2. A top-of-page occurred after a paper low condition. .inl -4 .spb .unl 10 02* manual halt. .brf One of the following has occurred: .brf .inl +4 .unl 4 1. The MANUAL HALT switch _o_r one of the printer control buttons has been activated. .unl 4 2. The POWER ON switch was activated while the printer was powered off. .unl 4 3. The printer yoke has been opened. .inl -4 .spb .unl 10 04* (PRT202, PRT300/301, PRT303) VFU tape alert. .brf One of the following has occurred: .inl +4 .unl 4 1. VFU tape horizontal parity error. .unl 4 2. VFU tape was not present. .unl 4 3. VFU tape was not properly installed. .unl 4 4. Holes were punched in both channel 5 (start automatic slew) and channel 6 (stop automatic slew) of the same vertical line position of the VFU tape. .inl -4 .spb .unl 10 10* check. .brf One or more of the following has occurred: .inl +4 .unl 4 1. Hammer driver fuse failure. .unl 4 2. Paper slew fuse failure. .unl 4 3. Incomplete printout; all characters received from the IOM were not printed. .unl 4 4. (PRT202) Print wheel out of sequence. .inl -4 .spb .unl 20 43 DATA ALERT. .spb .unl 10 00 (PRT300/301, PRT303) invalid character code or image buffer alert. .brf One of the following has occurred: .inl +4 .unl 4 1. An image load alert in which an invalid character was detected in the image _o_r less than 288 characters were received during image loading. .unl 4 2. An image buffer overflow condition in which more than 288 characters were received during image loading. .unl 4 3. A print incomplete condition in which one or more data characters failed to compare with an image character during a complete cycle of the print train. .inl -4 .spb (PRU1200/PRU1600) invalid character code or image buffer alert. .brf One of the following has occurred: .inl +4 .unl 4 1. An image load alert in which an invalid character was detected in the image _o_r less than 240 characters were received during image loading. .unl 4 2. An image buffer overflow condition in which more than 240 characters were received during image loading. .unl 4 3. A print incomplete condition in which one or more data characters failed to compare with an image character during a complete cycle of the print belt. .inl -4 .spb .unl 10 01* transfer timing alert. .brf The IOM did not send (write) data characters at a rate compatible with the transfer rate of the printer. .spb .unl 10 02* alert before printing started. .brf One of the following has occurred: .inl +4 .unl 4 1. A parity error was detected on a data character received by the printer. .unl 4 2. Print buffer overflow was sensed when more than 136 characters (160 FOR PRU1200/1600 with 160-character option) were received from the IOM before receipt of a slew character or end-data-transfer signal. .unl 4 3. A transfer timing alert condition exists. .unl 4 4. A top-of-page echo occurred while the printer was busy. .inl -4 .spb .unl 10 04* alert after printing started. .brf A parity error was detected on a data character in the print buffer. .spb .unl 10 10* paper low warning alert. .brf The last page of the form has passed the first forms detector and approximately 2.4 inches of form remains. .spb .unl 10 20* slew/paper motion alert. .brf More than two top-of-page indications were sensed within a single slew operation. .spb .unl 10 40* (PRT202, PRT300/301, PRT303) top-of-page echo. .brf The form has slewed to top-of-page as a result of a slew command other than the explicit slew-to-top-of-page. .spb .unl 20 45 COMMAND REJECTED. .spb .unl 10 00 (PRU1200/PRU1600) VFC image not loaded. .brf A print or slew command was issued before the VFC image of the printer was loaded. .spb .unl 10 01* invalid command. .brf The channel was unable to recognize the device command code in the PCW or IDCW. .spb .unl 10 02* (PRT300/301, PRT303, PRU1200/1600) invalid device code. .brf An invalid device was detected in an IDCW for the printer. .spb .unl 10 04* (PRT300/301) device/command code parity alert. .brf A parity error was caused by an incorrect device and/or command code. .pdl 103 .spb .unl 10 10 (PRU1200/PRU1600) train image not loaded. .brf A print or slew command was issued before the train image of the printer was loaded. .spb .unl 10 20* feed alert on last slew operation. .brf The previous operation resulted in a slew error. See also DATA ALERT, substatus 20 (slew/paper motion alert) above. .spb .unl 10 40* top-of-page echo on last slew operation. .brf The last command resulted in a termination interrupt with DATA ALERT, top-of-page echo (substatus 40, described above). .spb .unl 20 52 MPC DEVICE ATTENTION. .spb .unl 10 01 (PRT303, PRU1200/1600) IAI error. .brf A parity error was detected on the internal adapter interface (IAI) between the multiplexer adapter and the URMPC. .spb .unl 10 02 (PRT303, PRU1200/1600) DAI error. .brf One of the following was detected on the device adapter interface (DAI) between the URMPC and the device adapter (DA): .inl +4 .unl 4 1. Parity error detected by the DA. .unl 4 2. Parity error detected by the URMPC. .unl 4 3. Error timeout detected by the URMPC. .inl -4 .spb .unl 20 53 MPC DEVICE DATA ALERT. .spb .unl 10 01 (PRT303, PRU1200/1600) transmission parity error .brf A parity error was detected on the PSI during data transfer from the IOM to the URMPC. .spb .unl 10 05 (PRT303, PRU1200/1600) DAI error. .brf One of the following was detected on the DAI between the URMPC and the DA: .inl +4 .unl 4 1. Parity error detected by the URMPC. .unl 4 2. Error timeout detected by the URMPC. .inl -4 .spb .unl 10 06 (PRT303, PRU1200/1600) PSI data overflow. .brf More than 512 characters were received from the IOM. .spb .unl 20 55 MPC COMMAND REJECT. .spb .unl 10 01 (PRT303, PRU1200/1600) illegal procedure. .brf The URMPC was in suspend mode and will accept only special controller commands. .spb .unl 10 02 (PRT303, PRU1200/1600) invalid logical channel number .brf The logical channel number sent with the IDCW was invalid (not 00-07 hexadecimal). .spb .unl 10 10 (PRT303, PRU1200/1600) device reserved. .brf The DA is reserved to another PSI and is not available for use. .spb .unl 20 60 POWER OFF. .spb .unl 10 00 (PRT202, PRT300/301) power off. .brf The device is powered off or not cabled to the common peripheral interface (CPI). .spb (PRT303, PRU1200/1600) power off. .brf The URMPC is powered off, not cabled to the PSI of the IOM, or has lost its personality firmware. .inl 0 .brf .ifi l1h "Magnetic Tapes" .pdl 102 For a magnetic tape, the MAJOR and SUBSTATUS fields are interpreted in the following manner. Substatuses marked with an asterisk (*) may be ORed within the same major status. .sr draft "TAPE STATUS" .spb MAJOR SUBSTATUS .spb .inl 20 .unl 20 40 CHANNEL READY. .spb .unl 10 00 channel ready. .brf If received as an initiation interrupt (I = "1") in response to a reqs or ress command, the channel and device are ready to accept a new command. If received as a termination interrupt, the last command executed error free and the channel is ready to accept a new command (the device _m_a_y still be busy). .spb .unl 10 01* last tape unit write inhibited. .brf Same as substatus 00; in addition, the reel on the last tape drive addressed had no write-permit ring. .spb .unl 10 02* tape reel on load point. .brf Same as substatus 00; in addition, the last tape drive addressed was positioned at load point and is ready to process the first physical record. .spb .unl 10 04* ASA 9-track tape unit. .brf Same as substatus 00; in addition, the last tape drive addressed was an ASA 9-track unit. .spb .unl 10 14 (MTS500) ASCII alert. .brf The read-after-write check has detected an invalid EBCDIC character during a write ASCII/EBCDIC command. .spb .unl 10 20* (MTS500) 2-bit fill. .brf The final character from a 7-track read, a 9-track read ASCII, or a 9-track read EBCDIC has been padded with two low-order zero bits. .spb .unl 10 40* (MTS500) 4-bit fill. .brf The final character from a 7-track read, a 9-track read ASCII, or a 9-track read EBCDIC has been padded with four low-order zero bits. .spb .unl 10 60* (MTS500) 6-bit fill. .brf The final character from a 7-track read, a 9-track read ASCII, or a 9-track read EBCDIC has been padded with six low-order zero bits. .spb .unl 20 41 DEVICE BUSY. .spb .unl 10 01 (MTS500) in rewind. .brf The addressed tape drive is rewinding. .spb .unl 10 02 (MTS500) alternate channel in control. .brf The addressed tape drive is executing a command on the alternate channel. .spb .unl 10 04 (MTS500) device loading. .brf The addressed tape drive is in a tape loading cycle. .spb .unl 10 40 (MTS500) device reserved. .brf The addressed tape drive is reserved to the alternate channel as a result of a reserve device command. .spb .unl 20 42 ATTENTION. .spb .unl 10 01* tape write inhibited. .brf A write command was issued to a tape drive containing a reel without a write-permit ring _o_r to a tape drive that has been protected with the set file protect command. .spb .unl 10 02* no such tape unit. .brf A command was issued to a tape drive that is not configured or is in offline mode. .spb .unl 10 04* tape unit standby. .brf A command was issued to a tape drive that is in standby mode. .spb .unl 10 10* (MTS500) tape unit check. .brf A malfunction in the addressed tape drive has rendered it inoperable. .spb .unl 10 20* blank tape on write. .brf A write operation was started on the addressed tape drive, but the read-after-write check was unable to detect any characters. .spb .unl 20 43 DATA ALERT. .spb .unl 10 01 transfer timing alert. .brf The IOM did not send (write) or accept (read) data characters at a rate compatible with the transfer rate of the tape subsystem. .spb .unl 10 02* blank tape on read. .brf After receipt of a read command, 30 inches (25 feet for MTS500) of tape were passed over without detection of a data character. .spb .unl 10 03* bit detected during erase. .brf A bit was detected in the portion of the tape that should have been erased as a result of an erase or write end-of-file command. .spb .unl 10 04* transmission parity alert. .brf Incorrect parity was detected on a data character received from the IOM during a write operation. .spb .unl 10 10* lateral parity alert. .brf A missing data character or a lateral (character) parity error was detected. .spb .unl 10 20* longitudinal parity alert. .brf The calculated check character did not agree with the recorded check character. .spb .unl 10 40* end-of-tape mark. .brf The tape drive detected the reflective end-of-tape foil during a write operation. .spb .unl 20 44 END OF FILE. .spb .unl 10 (C) single data character "C". .brf The single character "C" was read as a valid record during a read, backspace, or forward space operation. .spb .unl 10 17 EOF marker (7 track). .brf A valid 7-track end-of-file mark was detected. .spb .unl 10 23 EOF marker (9 track). .brf A valid 9-track end-of-file mark was detected. .spb .unl 10 77 data alert. .brf A DATA ALERT condition was detected during reading of an end-of-file record. .spb .unl 20 45 COMMAND REJECTED. .spb .unl 10 01* invalid command. .brf The channel was unable to recognize the device command code in the PCW or IDCW. .spb .unl 10 02* invalid device code. .brf The channel was unable to recognize the device code in the PCW or IDCW. .spb .unl 10 04* parity alert on device/command code. .brf A parity error was detected in the command code and/or device code of the PCW or IDCW. .spb .unl 10 10* tape on load point. .brf A "backspace" or "backspace file" command was issued to a tape drive positioned at load point. .spb .unl 10 20* attempted read after write on same unit. .brf A "read" or "forward space" command was issued to a tape drive immediately after a "write" command. .spb .unl 10 40* 9-track alert. .brf A 9-track command was issued to a 7-track tape drive. .spb .unl 20 47 LOAD OPERATION COMPLETE. .spb .unl 10 00 (MTS400) load complete. .brf A program load (boot) operation was completed error free. .spb .unl 20 50 CHANNEL BUSY. .spb .unl 10 00 (MTS400) busy. .brf The command was accepted but execution will be delayed until current command sequences are complete because the command requires the entire subsystem. .spb .unl 20 52 MPC DEVICE ATTENTION. .spb .unl 10 01 (MTS500) configuration error. .brf The personality firmware (control program) loaded into the MPC does not agree with the settings of the MPC configuration switches. .spb .unl 10 02 (MTS500) multiple devices. .brf The MPC has detected at least two devices with the same logical ID number. .spb .unl 10 03 (MTS500) device number error. .brf The MPC has detected at least one device with a logical ID number outside the allowed range of ID numbers. .spb .unl 10 10 (MTS500) incompatible mode. .brf The tape drive mode (PE or NRZI) and the data mode recorded on the tape reel did not agree. .spb .unl 10 13 (MTS500) CA OPI down. .brf The controller adapter (CA) operational-in (OPI) line is reset. .spb .unl 10 14 (MTS500) TCA malfunction. .brf A fault was detected within one of the tape controller adapters (TCAs). The two low-order bits of the substatus indicate the internal adapter interface (IAI) port number to which the malfunctioning TCA is connected. .spb .unl 10 15 (MTS500) CA EN1 error. .brf An unexpected interrupt occurred during operation. .spb .unl 10 16 (MTS500) CA alert - no interrupt. .brf A CA alert occurred while a device number was being read during a select operation and the alert was not attributed to a cyclic code error on (read) status EN1. .spb .unl 10 20 (MTS500) MTH malfunction. .brf The MPC has detected an apparent malfunction in a tape drive and the drive did not signal a malfunction. .spb .unl 10 21 (MTS500) multiple beginning of tape. .brf Additional beginning-of-tape (BOT) reflective foils were detected after a tape was moved away from load point. .spb .unl 20 53 MPC DEVICE DATA ALERT. .spb .unl 10 01 (MTS500) transmission parity alert. .brf A parity error was detected during execution of a special controller command. .spb .unl 10 02 (MTS500) inconsistent command. .brf One of the following occurred during execution of a special controller command: .inl +4 .unl 4 1. Word count was zero for "read controller main memory," "write controller main memory," or write control store commands. .unl 4 2. Execution of "read controller main memory" or "write controller main memory" referenced nonexistent memory. .unl 4 3. Lock byte number specified was invalid. .unl 4 4. The continue bit was zero in the IDCW for a special controller command. .inl -4 .spb .unl 10 03 (MTS500) checksum error. .brf An error occurred in the checksum used by the "write control store" command. .spb .unl 10 04 (MTS500) byte locked out. .brf The lock byte referenced by the "conditional write lock byte" command was nonzero. .spb .unl 10 10 (MTS500) PE-burst write error. .brf The MPC was unable to write the PE-burst on the tape properly. .spb .unl 10 11 (MTS500) preamble error. .brf An error in a PE record preamble was detected _o_r there was apparently no data following a preamble. .spb .unl 10 12 (MTS500) T&D error. .brf This substatus is returned by the "device wraparound special controller" command to indicate an error byte and byte count. .spb .unl 10 20 (MTS500) multiple track error. .brf A data record contained errors in more than one recording track. .spb .unl 10 21 (MTS500) skew error. .brf Excessive skew was detected during a read or write operation in PE mode or during a write operation in NRZI mode. .spb .unl 10 22 (MTS500) postamble error. .brf The postamble of the PE record may have been in error. The error may have occurred in the data portion of the PE record such that a postamble appeared to be present. Also, errors may have occurred when entering the postamble so that the data appeared to continue past the data portion of the record. In either case, the postamble was not properly detected. .spb .unl 10 23 (MTS500) NRZI CCC error. .brf The 800-bpi, NRZI record just read contains correctable errors and may be reread. .spb .unl 10 24 (MTS500) code alert. .brf A character was detected that was not in the code translation tables. .spb .unl 10 40 (MTS500) marginal capstan speed. .brf Marginal capstan speed was detected during a write operation. .spb .unl 20 55 MPC COMMAND REJECT. .spb .unl 10 01 (MTS500) illegal procedure. .brf One of the following occurred: .inl +4 .unl 4 1. The MPC was not in suspend mode when "write controller main memory" and "write control store" commands were received. .unl 4 2. A special controller command did not precede an "initiate write data transfer" or "initiate read data transfer" command. .inl -4 .spb .unl 10 02 (MTS500. invalid logical channel number. .brf An invalid logical channel number was detected. .spb .unl 10 03 (MTS500) invalid suspend logical channel number. .brf The MPC is suspended and an IDCW was addressed to a logical channel other than the one over which the suspend controller command was received. .spb .unl 10 04 (MTS500) continue bit not set. .brf The first IDCW of a two-IDCW command (special controller command) did not have the continue bit set. .spb .unl 20 60 POWER OFF. .spb .unl 10 00 (MTS400) power off. .brf The tape controller is powered off or is not cabled to the CPI. .spb .inl 20 .unl 10 00 (MTS500) power off. .brf The MPC is powered off, is not cabled to the PSI, or has lost its personality firmware. .brp .inl 0 .sr draft "DISK STATUS" .ifi l1h "Disk Storage" For disk storage, the MAJOR and SUBSTATUS fields are interpreted in the following manner. Substatuses marked with an asterisk (*) may be ORed within the same major status. .spb 2 MAJOR SUBSTATUS .spb .inl 20 .unl 20 40 CHANNEL READY. .spb .unl 10 00 channel ready. .brf If received as an initiation interrupt (I = "1") in response to a reqs or ress command, the channel and device are ready to accept a new command. If received as a termination interrupt, the last command was executed error free and the channel is ready for a new command (the device _m_a_y still be busy). .spb .unl 10 0x* automatic retries. .brf When automatic retry is performed by the MPC, "x" is the count of retries performed. .spb .unl 10 10* device in T&D. .brf The device is in T&D mode. .spb .unl 10 20 (DSS191) error recovery - EDAC correct. .brf The MPC is attempting automatic retry, EDAC correction, and positioning offset to correct an error. .spb .unl 20 41 DEVICE BUSY. .spb .unl 10 00 file positioning. .brf The addressed device is busy positioning the actuator and could not accept a new command. .spb .unl 10 40 alternate channel in control. .brf The addressed device is busy executing a command on the alternate channel. .spb .unl 20 42 ATTENTION. .spb .unl 10 01* write inhibit. .brf A "write" command was issued to a device that had its write protect switch (PROTECT) in protect position. .spb .unl 10 02* seek incomplete. .brf The actuator mechanism of the addressed device failed to lock and/or unlock. .spb .unl 10 10 device inoperable. .brf The addressed device was online but did not respond correctly and requires maintenance attention. .spb .unl 10 20 device in standby. .brf The MPC detected a fatal error in the addressed device and continued operation would produce erroneous results. .spb .unl 10 40 device offline. .brf The addressed device is configured but is powered down or in offline mode. .spb .unl 20 43 DATA ALERT. .spb .unl 10 01 transfer timing alert. .brf The IOM did not send (write) or accept (read) data characters at a rate compatible with the transfer rate of the subsystem. .spb .unl 10 02 transmission parity alert. .brf A parity error was detected on a data character from the IOM during a write operation _o_r on a data character between the MPC and the device. .spb .unl 10 04 invalid seek address. .brf On a "seek disk address" command, an invalid control character was detected _o_r there were not exactly six control characters. .spb .unl 10 10* header verification failure. .brf The final position of the actuator did not correspond to the header address of the block being addressed by the current "seek disk address" command. .spb .unl 10 20* check character alert. .brf The check character generated by the MPC did not agree with the check character recorded on the disk. .spb .unl 10 40* data compare alert. .brf The data recorded on the disk did not compare with the data from the IOM during a "compare and verify" command. .spb .unl 20 44 END OF FILE. .spb .unl 10 00 good track detected. .brf A good track was detected at the specified sector address when a defective or alternate track was expected. .spb .unl 10 01* last consecutive block. .brf The last consecutive block available to the present actuator position was reached and the current command is incomplete. .spb .unl 10 02* sector count limit. .brf The sector count limit specified in the previous seek disk address command was reached. .spb .unl 10 04 defective track - alternate track assigned. .brf When an alternate track is assigned a read or write operation was attempted to a defective track _o_r an overflow was detected to or from an alternate track. .spb .unl 10 10 defective track - no alternate track assigned. .brf An alternate track is not assigned when a read or write operation was attempted to a defective track _o_r an overflow was detected to or from an alternate track. .spb .unl 10 20 alternate track detected. .brf A read or write operation was attempted to an alternate track when the track condition indicators from the previous "seek disk address" command did not indicate an alternate track operation. .spb .unl 20 45 COMMAND REJECTED. .spb .unl 10 01 invalid command. .brf The channel was unable to recognize the device command code in the PCW or IDCW. .spb .unl 10 02 invalid device code. .brf An invalid device code was received from the IOM _o_r no device with the given code is configured to the subsystem. .spb .unl 10 04 parity alert on IDCW. .brf The MPC detected a parity error on the device or command code from the IOM. .spb .unl 10 10 invalid command sequence. .brf .brf A data transfer command without a prior "seek disk address" command was received _o_r the "data transfer" command contained a device code different from that given in the "seek disk address" command. .spb .unl 20 50 CHANNEL BUSY. .spb .unl 10 00 busy. .brf The command was accepted but execution will be delayed until current command sequences are complete because the command requires the entire subsystem. .spb .unl 20 52 MPC DEVICE ATTENTION. .spb .unl 10 01 configuration error. .brf The personality firmware loaded into the MPC does not agree with the settings of the MPC configuration switches. .spb .unl 10 02 multiple devices. .brf The MPC has detected at least two devices with the same logical ID number. .spb .unl 10 03 device number error. .brf The MPC has detected at least one device with a logical ID number outside the allowed range of ID numbers. .spb .unl 10 13 CA OPI down. .brf The controller adapter (CA) operational-in (OPI) line is reset. .spb .unl 10 14 alert EN1 unexpected interrupt. .brf The CA detected an abnormal condition during operation. .spb .unl 10 15 CA EN1 error. .brf An unexpected interrupt occurred during operation. .spb .unl 10 16 CA alert - no interrupt. .brf A CA alert occurred while a device number was being read during a select operation and was not attributed to a cyclic code error on (read) status EN1. .spb .unl 20 53 MPC DEVICE DATA ALERT. .spb .unl 10 01 transmission parity. .brf A transmission parity error was detected during execution of a special controller command. .spb .unl 10 02 inconsistent command. .brf One of the following occurred during the execution of a special controller command: .inl +4 .unl 4 1. The word count was zero for "read controller main memory", "write controller main memory", or "write control store" commands. .unl 4 2. The execution of "read controller main memory" or "write controller main memory" referenced nonexistent memory. .unl 4 3. The lock byte number specified was invalid. .unl 4 4. The continue bit was zero in the IDCW for a special controller command. .inl -4 .unl 10 .spb 03 checksum error. .brf An error occurred in the checksum used by the "write control store" command. .spb .unl 10 04 byte locked out. .brf The lock byte referenced by the "conditional write lock byte" command was nonzero. .spb .unl 10 .cbn 10 (MSU0500, MSU0501) buffer parity. .brf A parity error occurred in the MPC's internal data buffer (MPCDP or MPCDQ). .spb .unl 10 11 (MSU0500, MSU0501) cyclic redundancy code error. .brf The MPC encountered a cyclic reduncadancy code (CRC) error in the data. The CRC check is performed in addition to EDAC to enhance data integrity. This status is indicative of a MPC hardware failure in the Controller Adapter (CA). .spb .unl 10 12 (MSU0500, MSU0501) count field uncorrectable. .brf The MPC encountered an uncorrectable EDAC error in the count field during a search operation. .spb .cbf .unl 10 16 (DSS190, DSS191) EDAC parity error. .brf An MPC hardware error was detected during EDAC generation. .spb .unl 10 21 sector size error. .brf The data field length read from the track was not as specified for the read function. .spb .unl 10 .cbn 22 (dsu181, dsu190) nonstandard sector size. .cbf .brf An attempt was made to read a sector that was not standard size. .spb .unl 10 .cbn 22 (MSU0500, MSU0501) defective sector. .brf Two defects found in the addressed sector. An alternate track must be assigned when this error coccurs. .spb .cbf .unl 10 23 (DSS190, DSS191) search alert on first search. .brf A double index was encountered on the first search of a "seek disk address" command and the MPC could not find a sector number. .spb .unl 10 24 (DSS190, DSS191) cyclic code error (not first search). .brf The MPC encountered a cyclic code error in the count field during a search that followed the initial search. .spb .unl 10 25 (DSS190, DSS191) search error (not first search). .brf The sector number did not compare on the second or subsequent search or the MPC encountered no count field on the track after head switching. .spb .unl 10 26 (DSS190, DSS191) sync byte error. .brf The MPC could not find the proper sync byte. .spb .unl 10 27 (DSS190, DSS191) error in automatic alternate track processing. .brf An error occurred in going to, processing, or returning from an alternate track. .spb .unl 10 31 (DSS190) EDAC correction - last sector. .brf An error was detected in the last sector transmitted, but the error was corrected and the transmission completed. .spb .unl 10 32 (DSS190) EDAC correction - not last sector. .brf An EDAC error was detected in a sector other than the last sector and was corrected. A new operation was generated by the MPC for the remaining sectors. .spb .unl 10 33 (DSS190) EDAC correction - block count limit. .brf An EDAC was detected and corrected on the last sector requested. .spb .unl 10 34 (DSS190) uncorrectable EDAC error. .brf An EDAC error was detected and found to be uncorrectable. .spb .unl 10 35 (DSS190) EDAC correction - short block. .brf One of the following conditions occurred: .inl +4 .unl 4 1. If an EDAC error was reported after the DCW exhausted (i.e., within a sector but outside that part of the sector transmitted), a CHANNEL READY status is returned. .unl 4 2. If an EDAC error was reported before the DCW exhausted, the EDAC correction for substatus 31(above) is applied. .unl 4 3. If the DCW exhausted at the end of a sector and an EDAC error is in the next sector, the subsystem recognizes that the DCW string is modulo 64 and returns a CHANNEL READY status. This occurs when the DCW exhausts on a sector boundary because the hardware, in terminating the operation, must read the sector even though the DCW exhausted and the EDAC error was encountered in the second sector. .inl -4 .cbn .spb .unl 10 41 (MSU0500, MSU0501) write buffer parity. .brf A parity error occurred when data was being written from the buffer to the disk, after an alter operation. .spb .unl 10 42 (MSU0500, MSU0501) uncorrectable read. .brf An uncorrectable read error occurred during the read portion of a read-alter-write operation. .spb .cbf .unl 20 45 MPC COMMAND REJECT. .spb .unl 10 01 illegal procedure. .brf One of the following occurred: .inl +4 .unl 4 1. The MPC was not in suspend mode when "write controller main memory" and "write control store" commands were received. .unl 4 2. A special controller command did not precede an "initiate write data transfer" or "initiate read data transfer" command. .inl -4 .spb .unl 10 02 invalid logical channel number. .brf An invalid logical channel number was detected. .spb .unl 10 03 invalid suspend command. .brf The MPC is suspended and an IDCW was addressed to a logical channel other than the one over which the "suspend controller" command was received. .spb .unl 10 04 continue bit not set. .brf The first IDCW of a two-IDCW command (special controller command) did not have the continue bit set. .spb .unl 20 60 POWER OFF. .spb .unl 10 00 power off. .brf The MPC is powered off, is not cabled to the PSI, or has lost its personality firmware. .inl 0 .sr draft "CONSOLE STATUS" .ifi l1h "System Consoles" For system consoles, the MAJOR and SUBSTATUS fields are interpreted in the following manner. Substatuses marked with an asterisk (*) may be ORed within the same major status. .spb 2 .inl 20 .unl 20 MAJOR SUBSTATUS .spb .unl 20 40 CHANNEL READY. .spb .unl 10 00 channel ready. .brf If received as an initiation interrupt (I ="1") in response to a reqs or ress command, the console is ready to accept a new command. If received as a termination interrupt, the last command was executed error free and the console is ready to accept a new command. .spb .unl 20 42 ATTENTION. .spb .unl 10 00 attention. .brf The console is unable to accept a command because of some inoperable condition. .spb .unl 20 43 DATA ALERT. .spb .unl 10 01 transfer timing alert. .brf The IOM did not receive (read) or send (write) data characters at a rate compatible with the transfer rate of the console. .spb .unl 10 02* transmission parity alert. .brf Incorrect parity was detected on a data character received from the IOM. This error can occur only during a write operation. .spb .unl 10 04 operator input error. .brf The operator has pressed the OPERATOR INPUT ERROR key on the console. .spb .unl 10 10 operator distracted. .brf An interval of 30 seconds has elapsed without input during a read operation. .spb .unl 10 20* incorrect format. .brf An escape character is followed by a invalid character in a message received from the IOM or a control character ("?" = 17(8), "!" = 77(8)) is not preceded by the proper number of escape characters. .spb .unl 10 40 message length alert. .brf The operator has entered more characters than were specified by the DCWs referenced by the "read" command. .spb .unl 20 45 COMMAND REJECTED. .spb .unl 10 01 invalid command. .brf The channel was unable to recognize the device command code in the PCW or IDCW. .spb .unl 10 03 command parity error. .brf A parity error was detected on the device command received from the IOM. .spb .unl 20 50 CHANNEL BUSY. .unl 10 .spb 00 channel busy. .spb .unl 20 60 POWER OFF. .spb .unl 10 00 power off. .brf The console is powered off or is not cabled to the IOM channel. .inl 0 .ifi l1h "MPC Extended Status" .fin The microprogrammed peripheral controller (MPC) maintains detailed, extended status for each device connected. This extended status is obtainable with the "read status register" (RSR) special controller command and is transmitted as a series of 8-bit bytes in binary data mode. .spb 2 Multics currently types the hexadecimal representation of these extended status bytes on the console for each disk error. .brf .ifi l2h "DSU181 Extended Status" .cbn PL/I Declaration (dsu181_det_stat_def.incl.pl1) .spb dcl 1 dsu181_detail_status unal, 2 d181_byte0, 3 device_reserved bit (1), 3 device_seized bit (1), 3 device_in_standby bit (1), 3 positioner_busy bit (1), 3 dli_fault bit (1), 3 write_protected bit (1), 3 device_fault bit (1), 3 diagnostic_mode bit (1), 2 d181_byte1, 3 cmd_parity_error bit (1), 3 bad_cmd_decode bit (1), 3 invalid_command bit (1), 3 state_violation bit (1), 3 protect_violation bit (1), 3 mbz1 bit (1), 3 data_parity_error bit (1), 3 mbz2 bit (1), 2 d181_byte2, 3 mbz3 bit (5), 3 spindle_speed_loss bit (1), 3 mbz4 bit (2), 2 d181_byte3, 3 seek_incomplete bit (1), 3 mbz5 bit (7), 2 d181_byte4, 3 erase_current_unsafe bit (1), 3 dc_write_unsafe bit (1), 3 ac_write_unsafe bit (1), 3 heads_unsafe bit (1), 3 erase_gate_and_busy bit (1), 3 write_gate_and_busy bit (1), 3 wrt_gate_no_erase_cur bit (1), 3 voltage_unsafe bit (1), 2 d181_byte5, 3 brush_at_stop bit (1), 3 pack_mounted bit (1), 3 lid_on bit (1), 3 index_block_in bit (1), 3 mbz6 bit (1), 3 heads_flying bit (1), 3 zero_speed bit (1), 3 on_line bit (1), 2 d181_byte6, 3 positioner_overtemp bit (1), 3 positioner_fast bit (1), 3 positioner_out_of_limits bit (1), 3 positioner_volt_out_of_limits bit (1), 3 mbz7 bit (4), 2 d181_byte7, 3 mbz9 bit (8), 2 d181_byte8, 3 mbz10 bit (8), 2 d181_byte9, 3 mbz11 bit (8), 2 d181_byte10, 3 mbz12 bit (7), 3 CA fixed bin (1) uns, 2 d181_byte11, 3 mbz15 bit (3), 3 PORT fixed bin (5) uns; .sr draft "DSU181 EXTENDED STATUS" .cbf .fif .inl 3 .spb | byte0 | byte1 | byte2 | byte3 | byte4 > |0 1 2 3 4 5 6 7|0 1 2 3 4 5 6 7|0 1 2 3 4 5 6 7|0 1 2 3 4 5 6 7|0 1 2 3> | | | | | > 0 0 0 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3 3 3 _0______________7__8______________5__6__7__8__9__0__1__2__3__4__5__6__7__8__9__0__1__2______5__ | | | | | | | | | | | | | | | | | | | | | DEVICE | (140)8 |a|b|c|d|e|f|g|h|i|j|k|l|m|n|0|o|0 0 0 0| _|________________|________________|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|________| 8 8 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 4 .spb < byte4 | byte5 | byte6 | byte7 | byte8 | <4 5 6 7|0 1 2 3 4 5 6 7|0 1 2 3 4 5 6 7|0 1 2 3 4 5 6 7|0 1 2 3 4 5 6 7| < | | | | | 0 0 0 0 0 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3 3 3 _0__1__2__3__4______________1__2__33__4__5__6__7__8__9__0__1__2__33__4__5__6__7__8__9__0__1__2______5__ | | | | | | | | | | | | | | | | | | | | | | | | | | | |0|p|0 0|q|0 0 0 0 0 0 0|r|s|t|u|v|w|x|y|z|A|B|C|D|E|F|G|H|I|J|K|0 0 0 0| _|__|__|____|__|______________|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|________| 1 1 2 1 7 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 4 .spb 2 .inl 0 .ifi fig "DSS181 Extended Status" Legend: .spb .fin .inl 10 .unl 10 F__i_e_l_d M__e_a_n_i_n_g .spb .unl 10 DEVICE the logical ID number of the drive. .spb .unl 10 (140)8 the octal value of the hexadecimal code for DSS181. .spb .inl 0 .vmh 0 .hla 1 |F__i_e_l_d M__e_a_n_i_n_g| .hla 2 || .inl 10 .unl 10 a device reserved. .unl 10 b device seized. .unl 10 c device in standby. .unl 10 d positioner busy. .unl 10 e DLI fault. .unl 10 f device protected. .unl 10 g device fault. .unl 10 h device in T&D mode. .spb .unl 10 i command parity error. .unl 10 j no or multiple command decode. .unl 10 k invalid command. .unl 10 l invalid command sequence. .unl 10 m state violation. .unl 10 n protection violation. .unl 10 o data parity error. .spb .unl 10 p spindle speed loss. .spb .unl 10 q seek incomplete. .unl 10 r erase current unsafe. .unl 10 s DC write unsafe. .unl 10 t AC write unsafe. .unl 10 u heads unsafe. .unl 10 v erase gate and busy. .unl 10 w write gate and busy. .unl 10 x write gate and no erase current. .unl 10 y voltage unsafe. .spb .unl 10 z brush at stop. .unl 10 A pack on. .unl 10 B lid on. .unl 10 C index block in. .unl 10 D attention latch. .unl 10 E heads flying. .unl 10 F zero speed. .unl 10 G online. .spb .unl 10 H positioner overtemperature. .unl 10 I positioner overvelocity. .unl 10 J position out of limits. .unl 10 K positioner voltage out of limits. .inl 0 .hla .sr draft "DSU190A EXTENDED STATUS" .brf .ifi l2h "DSU190A Extended Status" .inl 10 .unl 10 C_A_U_T_I_O_N_: The extended status formats for DSU190A and DSU190B devices are different. BE SURE YOU REFER TO THE FORMAT FOR YOUR DEVICES. .fif .inl 0 .spb .cbn PL/I Declaration (dsu190a_det_stat_def.incl.pl1) .spb dcl 1 dsu190a_detail_status unal, 2 d190a_byte0, 3 device_reserved bit (1), 3 device_seized bit (1), 3 device_in_standby bit (1), 3 positioner_busy bit (1), 3 dli_fault bit (1), 3 write_protected bit (1), 3 device_fault bit (1), 3 diagnostic_mode bit (1), 2 d190a_byte1, 3 cmd_parity_error bit (1), 3 mbz1 bit (1), 3 invalid_command bit (1), 3 invalid_cmd_seq bit (1), 3 state_violation bit (1), 3 protect_violation bit (1), 3 trans_timing_err bit (1), 3 data_parity_error bit (1), 2 d190a_byte2, 3 lost_write_cur bit (1), 3 wrt_cur_no_wrt_cmd bit (1), 3 lost_AC_wrt_cur bit (1), 3 bad_head_select bit (1), 3 mbz2 bit (1), 3 spindle_speed_loss bit (1), 3 pwr_supply_overtemp bit (1), 3 lost_dc_power bit (1), 2 d190a_byte3, 3 seek_incomplete bit (1), 3 positioner_overtravel bit (1), 3 mbz3 bit (2), 3 rps_error bit (1), 3 mbz4 bit (3), 2 d190a_byte4, 3 fine_servo bit (1), 3 tester_addr_error bit (1), 3 mbz5 bit (1), 3 brush_cycle_incomplete bit (1), 3 mbz6 bit (2), 3 forward_direction_set bit (1), 3 reverse_direction_set bit (1), 2 d190a_byte5, 3 mbz7 bit (4), 3 heads_retracted bit (1), 3 positioner_offset bit (1), 3 read_clock_offset bit (1), 3 write_and_read bit (1), 2 d190a_byte6, 3 mbz8 bit (3), 3 logic_overtemp bit (1), 3 read_amp_low bit (1), 3 mbz9 bit (3), 2 d190a_byte7, 3 mbz10 bit (8), 2 d190a_byte8, 3 mbz11 bit (8), 2 d190a_byte9, 3 mbz12 bit (8), 2 d190a_byte10, 3 mbz13 bit (7), 3 CA fixed bin (1) uns, 2 d190a_byte11, 3 mbz14 bit (3), 3 PORT fixed bin (5) uns; .cbf .spb .inl 3 | byte0 | byte1 | byte2 | byte3 | byte4 > |0 1 2 3 4 5 6 7|0 1 2 3 4 5 6 7|0 1 2 3 4 5 6 7|0 1 2 3 4 5 6 7|0 1 2 3> | | | | | > 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3 3 3 3 _0__1__2__3__4__5__6__7__8__9__0__1__2__3__4__5__6__7__8__9__0__1__2__3__4__5__6__7__8__9____1__2__3__4__5__ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |a|b|c|d|e|f|g|h|i|0|j|k|l|m|n|o|p|q|r|s|0|t|u|v|w|x|0 0|y|0 0 0|z|0 0|A| _|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|____|__|______|__|____|__| 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 1 3 1 2 1 .spb < byte4 | byte5 | byte6 | byte7 | byte8 | <4 5 6 7|0 1 2 3 4 5 6 7|0 1 2 3 4 5 6 7|0 1 2 3 4 5 6 7|0 1 2 3 4 5 6 7| < | | | | | 0 0 0 0 0 0 0 0 0 1 1 1 2 2 2 3 _0__1__2__3__4______6__7__8__9__0__1____________________0__1__2__3____________________5__ | | | | | | | | | | | | | |0 0|B|C|0 0 0 0|D|E|F|G|0 0 0 0 0 0 0 0 0 0 0|H|I|0 0 0 0 0 0 0 0 0 0 0| _|____|__|__|________|__|__|__|__|______________________|__|__|______________________| 2 1 1 4 1 1 1 1 11 1 1 11 .spb 2 .inl 0 .ifi fig "DSS190A Extended Status" Legend: .spb .fin .inl 10 .unl 10 F__i_e_l_d M__e_a_n_i_n_g .spb .inl 0 .vmh 0 .hla 1 |F__i_e_l_d M__e_a_n_i_n_g| .hla 2 || .inl 10 .unl 10 a device reserved. .unl 10 b device seized. .unl 10 c device in standby. .unl 10 d positioner busy. .unl 10 e DLI fault. .unl 10 f device protected. .unl 10 g device fault. .unl 10 h device in T&D mode. .spb .unl 10 i command parity error. .unl 10 j invalid command. .unl 10 k invalid command sequence. .unl 10 l state violation. .unl 10 m protection violation. .unl 10 n transfer timing error. .unl 10 o data parity error. .spb .unl 10 p loss of write current. .unl 10 q write current without write command. .unl 10 r loss of AC write current. .unl 10 s no or multiple head selection. .unl 10 t spindle speed loss. .unl 10 u overtemperature. .unl 10 v loss of voltage. .spb .unl 10 w seek incomplete. .unl 10 x positioner overtravel. .unl 10 y RPS error. .unl 10 z fine servo. .unl 10 A brush cycle incomplete. .unl 10 B forward set. .unl 10 C reverse set. .spb .unl 10 D heads retracted. .unl 10 E positioner offset. .unl 10 F read clock offset. .unl 10 G write and read. .spb .unl 10 H low air flow. .unl 10 I read amplitude low. .hla .fif .sr draft "DSU190B EXTENDED STATUS" .inl 0 .ifi l2h "DSU190B Extended Status" .fin .inl 10 .unl 10 C_A_U_T_I_O_N_: The extended status formats for DSU190A and DSU190B devices are different. BE SURE YOU REFER TO THE FORMAT FOR YOUR DEVICES. .spb 2 .inl 0 .cbn PL/I Declaration (dsu190b_def_stat_def.incl.pl1) .spb dcl 1 dsu190b_detail_status unal, 2 d190b_byte0, 3 device_reserved bit (1), 3 device_seized bit (1), 3 device_in_standby bit (1), 3 positioner_busy bit (1), 3 dli_fault bit (1), 3 write_protected bit (1), 3 device_fault bit (1), 3 diagnostic_mode bit (1), 2 d190b_byte1, 3 cmd_parity_error bit (1), 3 mbz1 bit (1), 3 invalid_command bit (1), 3 mbz2 bit (1), 3 state_violation bit (1), 3 protect_violation bit (1), 3 trans_timing_err bit (1), 3 data_parity_error bit (1), 2 d190b_byte2, 3 mbz3 bit (1), 3 wrt_cur_no_wrt_cmd bit (1), 3 lost_AC_wrt_cur bit (1), 3 bad_head_select bit (1), 3 incomplete_strt_cycle bit (1), 3 spindle_speed_loss bit (1), 3 positioner_overtemp bit (1), 3 lost_dc_power bit (1), 2 d190b_byte3, 3 seek_incomplete bit (1), 3 positioner_overtravel bit (1), 3 positioner_int_fault bit (1), 3 positioner_sense_fault bit (1), 3 rps_fault bit (1), 3 mbz4 bit (3), 2 d190b_byte4, 3 positioner_overspeed bit (1), 3 invalid_cyl_addr bit (1), 3 loss_of_index bit (1), 3 emergency_retract bit (1), 3 lost_positioner_speed bit (1), 3 positioner_off_track bit (1), 3 invalid_head_address bit (1), 3 positioner_offset bit (1), 2 d190b_byte5, 3 mbz5 bit (2), 3 read_wrt_ctr_error bit (1), 3 wrt_precomp_error bit (1), 3 MFM_decoder_error bit (1), 3 read_cmd_timing_fault bit (1), 3 mbz6 bit (1), 3 read_write_clock_fault bit (1), 2 d190b_byte6, 3 lost_read_signal bit (1), 3 bad_write_current bit (1), 3 loss_of_position_signal bit (1), 3 loss_of_positional_current bit (1), 3 loss_of_power_amp_input bit (1), 3 write_fault_sensed bit (1), 3 pos_motor_pack_hot bit (1), 3 loss_of_blower bit (1), 2 d190b_byte7, 3 mbz7 bit (8), 2 d190b_byte8, 3 mbz8 bit (8), 2 d190b_byte9, 3 mbz9 bit (8), 2 d190b_byte10, 3 mbz10 bit (7), 3 CA fixed bin (1) uns, 2 d190b_byte11, 3 mbz11 bit (3), 3 PORT fixed bin (5) uns; .cbf .fif .spb .inl 3 | byte0 | byte1 | byte2 | byte3 | byte4 > |0 1 2 3 4 5 6 7|0 1 2 3 4 5 6 7|0 1 2 3 4 5 6 7|0 1 2 3 4 5 6 7|0 1 2 3> | | | | | > 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3 3 3 3 _0__1__2__3__4__5__6__7__8__9__0__1__2__3__4__5__6__7__8__9__0__1__2__3__4__5__6__7__8__9____1__2__3__4__5__ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |a|b|c|d|e|f|g|h|i|0|j|0|k|l|m|n|0|o|p|q|r|s|t|u|v|w|x|y|z|0 0 0|A|B|C|D| _|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|______|__|__|__|__| 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3 1 1 1 1 .spb < byte4 | byte5 | byte6 | byte7 | byte8 | <4 5 6 7|0 1 2 3 4 5 6 7|0 1 2 3 4 5 6 7|0 1 2 3 4 5 6 7|0 1 2 3 4 5 6 7| < | | | | | 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 3 _0__1__2__3___4__5_6___7__8__9__0__1__2__3__4__5__6__7__8__9__0__1__1__3__4_____________________5__ | | | | | | | | | | | | | | | | | | | | | | | | |E|F|G|H|0 0|I|J|K|L|0|M|N|P|Q|R|S|T|U|V|0 0|W|X|0 0 0 0 0 0 0 0 0 0 0 0| _|__|__|__|__|____|__|__|__|__|__|__|__|__|__|__|__|__|__|__|____|__|__|________________________| 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 1 1 12 .spb 2 .inl 0 .ifi fig "DSS190B Extended Status" .hla Legend: .spb .fin .inl 10 .unl 10 F__i_e_l_d M__e_a_n_i_n_g .spb .inl 0 .vmh 0 .hla 1 | F__i_e_l_d M__e_a_n_i_n_g| .hla 2 || .inl 10 .unl 10 a device reserved. .unl 10 b device seized. .unl 10 c device in standby. .unl 10 d positioner busy. .unl 10 e DLI fault. .unl 10 f device protected. .unl 10 g device fault. .unl 10 h device in T&D mode. .spb .unl 10 i command parity error. .unl 10 j invalid command. .unl 10 k state violation. .unl 10 l protection violation. .unl 10 m transfer timing error. .unl 10 n data parity error. .spb .unl 10 o write current without write command. .unl 10 p loss of write current. .unl 10 q no or multiple head selection. .unl 10 r incomplete start cycle. .unl 10 s spindle speed loss. .unl 10 t positioner overtemperature. .unl 10 u DC power loss. .unl 10 .spb v seek incomplete. .unl 10 w positioner overtravel. .unl 10 x positioner internal fault. .unl 10 y positioner sense fault. .unl 10 z RPS fault. .unl 10 .spb A positioner overspeed. .unl 10 B invalid cylinder address. .unl 10 C loss of index. .unl 10 D emergency retract occurred. .unl 10 E loss of velocity. .unl 10 F positioner off track. .unl 10 G invalid head address. .unl 10 H positioner offset. .spb .unl 10 I read or write counter error. .unl 10 J write precompensation fault. .unl 10 K KFK decoder fault. .unl 10 L read command timing fault. .unl 10 M read or write clock fault. .spb .unl 10 N loss of read signal. .unl 10 P incorrect write current. .unl 10 Q loss of position signal. .unl 10 R loss of positioner current. .unl 10 S loss of power amplifier input. .unl 10 T write fault sense. .unl 10 U position motor/pack overtemperature. .unl 10 V loss of blower. .spb .unl 10 W clogged coarse filter. .unl 10 X clogged fine filter. .hla .inl 0 .ifi l2h "MSU0451 Extended Status" .sr draft "MSU0451 EXTENDED STATUS" .cbn PL/I Declaration (dsu451_det_stat_def.incl.pl1) .spb 2 d451_byte0, 3 device_reserved bit (1), 3 device_seized bit (1), 3 device_in_standby bit (1), 3 positioner_busy bit (1), 3 dli_fault bit (1), 3 write_protected bit (1), 3 device_fault bit (1), 3 diagnostic_mode bit (1), 2 d451_byte1, 3 cmd_parity_error bit (1), 3 mbz1 bit (1), 3 invalid_command bit (1), 3 invalid_cmd_seq bit (1), 3 state_violation bit (1), 3 protect_violation bit (1), 3 trans_timing_err bit (1), 3 data_parity_error bit (1), 2 d451_byte2, 3 loss_of_write_cur bit (1), 3 wrt_cur_no_wrt_cmd bit (1), 3 lost_AC_wrt_cur bit (1), 3 bad_head_select bit (1), 3 mbz2 bit (1), 3 spindle_speed_loss bit (1), 3 mbz3 bit (1), 3 lost_dc_power bit (1), 2 d451_byte3, 3 seek_incomplete bit (1), 3 positioner_overtravel bit (1), 3 mbz4 bit (2), 3 rps_fault bit (1), 3 mbz5 bit (3), 2 d451_byte4, 3 fine_servo bit (1), 3 tester_addr_error bit (1), 3 mbz6 bit (1), 3 first_seek_incomplete bit (1), 3 mbz7 bit (1), 3 loss_of_cooling bit (1), 3 fwd_direction_set bit (1), 3 rev_direction_set bit (1), 2 d451_byte5, 3 mbz8 bit (4), 3 heads_retracted bit (1), 3 positioner_offset bit (1), 3 read_clock_offset bit (1), 3 write_and_read bit (1), 2 d451_byte6, 3 mbz9 bit (8), 2 d451_byte7, 3 mbz10 bit (8), 2 d451_byte8, 3 mbz11 bit (8), 2 d451_byte9, 3 mbz12 bit (8), 2 d451_byte10, 3 mbz13 bit (7), 3 CA fixed bin (1) uns, 2 d451_byte11, 3 mbz14 bit (3), 3 PORT fixed bin (5) uns; .cbf .fif .inl 3 .inl .hla |F__i_e_l_d M__e_a_n_i_n_g|| .hla 2 || .spb | byte0 | byte1 | byte2 | byte3 | byte4 > |0 1 2 3 4 5 6 7|0 1 2 3 4 5 6 7|0 1 2 3 4 5 6 7|0 1 2 3 4 5 6 7|0 1 2 3> | | | | | > 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 3 3 3 3 3 _0__1__2__3__4__5__6__7__8__9__0__1__2__3__4__5__6__7__8__9__0__1__2__3__4__5__6__7__8______1__2__3__4__5__ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |a|b|c|d|e|f|g|h|i|0|j|k|l|m|n|o|p|q|r|s|0|t|0|u|v|w|0|x|0 0 0 0|y|z|0|A| _|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|________|__|__|__|__| .spb < byte4 | byte5 | byte6 | byte7 | byte8 | <4 5 6 7|0 1 2 3 4 5 6 7|0 1 2 3 4 5 6 7|0 1 2 3 4 5 6 7|0 1 2 3 4 5 6 7| < | | | | | 0 0 0 0 0 0 0 0 1 1 1 3 _0__1__2__3__4______7__8__9__0__1__2______________________________________________5__ | | | | | | | | | | | |0|B|C|D|0 0 0 0|E|F|G|H|0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| _|__|__|__|__|________|__|__|__|__|________________________________________________| .spb 2 .inl 0 .bbe 1 ||Figure C-4. MSU0451 Extended Status|| .spb 2 Legend: .spb F__i_e_l_d M__e_a_n_i_n_g .spb .inl 10 .unl a device reserved. .unl b device seized. .unl c device in standby. .unl d positioner busy. .unl e DLI fault. .unl f device protected. .unl g device failure. .unl h device in diagnostic mode. .spb .unl i command parity error. .unl j invalid command. .unl k invalid command sequence. .unl l state violation. .unl m protect violation. .unl n transfer timing error. .unl o data parity error. .spb .unl p write command without write current. .unl q write current without write command. .unl r loss of AC write current. .unl s no or multiple head selection. .unl t spindle speed loss. .unl u loss of voltage. .spb .unl v seek incomplete. .unl w positioner overtravel. .unl x rotational position sensing fault. .spb .unl y fine servo status. .unl z tester address error. .unl A first seek interlock cycle incomplete. .unl B restricted air flow. .unl C forward FF set. .unl D reverse FF set. .unl .spb E heads retracted. .unl F positioner offset. .unl G read clock offset. .unl H write and read. .unl .cbn I controller adapter (CA) 0=CA-0, 1=CA-1. .unl J controller adapter port number. .cbf .inl 0 .spb PL/I Declaration (mth500_det_status_def.inl.pl1) .fif .spb dcl 1 mth500_detail_status unal, 2 mth500_byte0, 3 dev_fault bit (1), 3 cmd_code_err bit (1), 3 wrt_echo_err bit (1), 3 mult_bot_stat bit (1), 3 BOT_storage bit (1), 3 EOT_storage bit (1), 3 standby bit (1), 3 margin_condition bit (1), 2 mth500_byte1, 3 load_complete bit (1), 3 lst_cmd_wrt bit (1), 3 lst_cmd_fwd bit (1), 3 rewind_tape bit (1), 3 wrt_ring_pres bit (1), 3 write_permit bit (1), 3 diag_mode bit (1), 3 cmd_evn_par bit (1), 2 mth500_byte2, 3 current_density bit (3), 3 low_thresh bit (1), 3 density_capability bit (4), 2 mth500_byte3, 3 mbz1 bit (1), 3 tracks bit (1), 3 mth500_bit bit (1), 3 dev_speed bit (5), 2 mth500_byte4, 3 mbz2 bit (1), 3 deskew_window bit (1), 3 mbz3 bit (1), 3 dev_address fixed bin (5) uns, 2 mth500_byte5, 3 chg_volt_mode bit (1), 3 reduce_wrt_curr bit (1), 3 reduce_erase_curr bit (1), 3 rd_deskew_wrap bit (1), 3 mbz4 bit (3), 3 50_herz bit (1), 2 mth500_byte6, 3 load_air_fail bit (1), 3 file_hub_eng bit (1), 3 window_not_shut bit (1), 3 vac_start_up_failure bit (1), 3 file_hub_open bit (1), 3 can_open_failure bit (1), 3 semi-auto_wrap_fail bit (1), 3 auto_wrap_failure bit (1), 2 mth500_byte7, 3 mach_col_not_loaded bit (1), 3 file_col_not_loaded bit (1), 3 door_intlk_open bit (1), 3 window_intlk_open bit (1), 3 file_col_hi_tape bit (1), 3 mach_col_hi_tape bit (1), 3 file_col_lo_tape bit (1), 3 mach_col_lo_tape bit (1), 2 mth500_byte8, 3 vac_loss bit (1), 3 col_vac_marginal bit (1), 3 LTOR_lamp_out bit (1), 3 BOT_EOT_lamp_out bit (1), 3 can_shut_failure bit (1), 3 file_hub_released bit (1), 3 erase_cur_failure bit (1), 3 window_safety_bar bit (1), 2 mth500_byte9, 3 logic_overtemp bit (1), 3 capstan_overtemp bit (1), 3 dc_breaker_open bit (1), 3 plus_5v_failure bit (1), 3 neg_24v_failure bit (1), 3 plus_12v_failure bit (1), 3 neg_12v_failure bit (1), 3 plus_24v_failure bit (1), 2 mth500_byte10, 3 capstan_over_speed bit (1), 3 capstan_under_speed bit (1), 3 not_used1 bit (1), 3 not_used2 bit (1), 3 plus_5v_marginal bit (1), 3 neg_24v_marginal bit (1), 3 plus_12v_marginal bit (1), 3 neg_12v_marginal bit (1), 2 mth500_byte11, 3 start_stop bit (1), 3 stop bit (1), 3 prev_direction_fwd bit (1), 3 reverse_direction bit (1), 3 bidirection_sequence bit (1), 3 write_permit bit (1), 3 wrt_amp_enable bit (1), 3 wrt_curr_enable bit (1), 2 mth500_byte12, 3 unload_tape bit (1), 3 rewind_search_time bit (1), 3 high_spd_drive bit (1), 3 deskew_ctr_enable bit (1), 3 BOT_marker_detected bit (1), 3 EOT_marker_detected bit (1), 3 LTOR_marker_detected bit (1), 3 LTOR_storage bit (1), 2 mth500_byte13, 3 capstan_run_cmd bit (1), 3 capstan_cw bit (1), 3 capstan_rewind_cmd bit (1), 3 capstan_run bit (1), 3 capstan_direction_ccw bit (1), 3 capstan_rewind bit (1), 3 capstan_speed_low bit (1), 3 capstan_rewinding bit (1), 2 mth500_byte14, 3 drive_file_reel_cw_cmd bit (1), 3 drive_file_reel_ccw_cmd bit (1), 3 drive_file_reel_cw bit (1), 3 drive_file_reel_ccw bit (1), 3 file_col_hi_sensor bit (1), 3 file_col_lo_sensor bit (1), 3 brake_file_reel bit (1), 3 file_reel_bias bit (1), 2 mth500_byte15, 3 file_reel_cont_rwd bit (1), 3 file_reel_inhib bit (1), 3 file_reel_control_malf bit (1), 3 file_reel_rewind bit (1), 3 file_reel_inhib_sensor bit (1), 3 file_cont_malf_status bit (1), 3 file_hub_sw bit (1), 3 malfunction_cleared bit (1), 2 mth500_byte16, 3 tape_in_file_col bit (1), 3 not_used1 bit (1), 3 not_used2 bit (1), 3 lo_tape_file_col bit (1), 3 tape_in_mach_col bit (1), 3 not_used3 bit (1), 3 not_used4 bit (1), 3 lo_tape_mach_col bit (1), 2 mth500_byte17, 3 drive_mach_reel_cw_cmd bit (1), 3 drive_mach_reel_ccw_cmd bit (1), 3 mach_reel_cw_drive bit (1), 3 mach_reel_ccw_drive bit (1), 3 mach_col_hi_sensor bit (1), 3 mach_col_lo_sensor bit (1), 3 mach_reel_brake bit (1), 3 mach_reel_bias bit (1), 2 mth500_byte18, 3 mach_reel_cont_rewind bit (1), 3 mach_inhib_sensors bit (1), 3 mach_reel_control_malf bit (1), 3 mach_reel_rewind bit (1), 3 mach_reel_inhib_sensor bit (1), 3 mach_reel_cont_malf bit (1), 3 tape_on_mach_reel bit (1), 3 enable_use_time_meter bit (1), 2 mth500_byte19, 3 enable_head_movement bit (1), 3 head_retracted bit (1), 3 tape_tip_sensed bit (1), 3 drive_cannister_open bit (1), 3 drive_cannister_shut bit (1), 3 cannister_open bit (1), 3 cannister_shut bit (1), 3 cannister_load bit (1), 2 mth500_byte20, 3 count_by bit (6), 3 start_load_seq bit (1), 3 manual_load bit (1), 2 mth500_byte21, 3 ena_xport_air_vac bit (1), 3 ena_mach_reel_hub_vac bit (1), 3 ena_hold_vac_sw bit (1), 3 ena_cannister_air bit (1), 3 ena_ramp_air_vac bit (1), 3 ena_file_hub_pressure bit (1), 3 ena_load_air_vac bit (1), 3 ena_col_air_open_hub bit (1), 2 mth500_byte22, 3 vacuum_available bit (1), 3 col_vac_above_margin bit (1), 3 load_air_avail bit (1), 3 enable_window_drive bit (1), 3 ena_window_direction bit (1), 3 window_up bit (1), 3 window_down bit (1), 3 door_intlk_closed bit (1), 2 mth500_byte23, 3 inhib_motion_and_wrt_cur bit (1), 3 ena_wrt_amp_to_rd_amp bit (1), 3 ena_wrt_data_to_rd_line bit (1), 3 wrt_wrap_to_rd_lines bit (1), 3 bypass_deskew bit (1), 3 load_single_clk_mode bit (1), 3 run_capstan_underspd bit (1), 3 run_capstan_overspd bit (1), 2 mth500_byte24, 3 not_used5 bit (8), 2 mth500_byte25, 3 not_used6 bit (8); .spb .fin PL/I Declaration (mth600_det_stat_def.incl.pl1) .fif .spb dcl 1 mth600_detail_status unal, 2 mth600_byte0, 3 dev_fault bit (1), 3 cmd_code_err bit (1), 3 wrt_echo_err bit (1), 3 mult_bot_stat bit (1), 3 BOT_storage bit (1), 3 EOT_storage bit (1), 3 standby bit (1), 3 margin_condition bit (1), 2 mth600_byte1, 3 load_complete bit (1), 3 lst_cmd_wrt bit (1), 3 lst_cmd_fwd bit (1), 3 rewind_tape bit (1), 3 wrt_ring_pres bit (1), 3 write_permit bit (1), 3 cmd_evn_par bit (1), 2 mth600_byte2, 3 current_density bit (3), 3 low_thresh bit (1), 3 density_capability bit (4), 2 mth600_byte3, 3 mbz1 bit (1), 3 tracks bit (1), 3 ON bit (1), 3 dev_speed bit (5), 2 mth600_byte4, 3 dev_addr_err bit (1), 3 increased_deskew bit (1), 3 dev_address fixed bin (6) uns, 2 mth600_byte5, 3 thresh_select bit (3), 3 revision_status bit (5), 2 mth600_byte6, 3 column_vac_fail bit (1), 3 main_blower_fail bit (1), 3 over_temp_deck bit (1), 3 TMC_ROM_error bit (1), 3 device_model bit (4), 2 mth600_byte7, 3 malfunction_codes bit (5), 3 voltage_faults bit (2), 3 circuit_bkr_tripped bit (1), 2 mth600_byte8, 3 erase_cur_fail bit (1), 3 door_open bit (1), 3 capstan_blower_fail bit (1), 3 air_bearing_fail bit (1), 3 multi_rin_det bit (1), 3 wiring_pwb_in bit (1), 3 wiring_spd_det bit (1), 3 marginal_gap bit (1), 2 mth600_byte9, 3 mach_servo_tach bit (1), 3 mach_quad_tach1 bit (1), 3 mach_quad_tach2 bit (1), 3 file_servo_tach bit (1), 3 file_quad_tach1 bit (1), 3 file_quad_tach2 bit (1), 3 capstan_servo_tach bit (1), 3 duty_cycle_exceeded bit (1), 2 mth600_byte10, 3 mach_reel_cw bit (1), 3 mach_reel_ccw bit (1), 3 mach_reel_driving bit (1), 3 mach_reel_braking bit (1), 3 file_reel_cw bit (1), 3 file_reel_ccw bit (1), 3 file_reel_driving bit (1), 3 file_reel_braking bit (1), 2 mth600_byte11, 3 ena_thrd_air_valve bit (1), 3 ena_ramp_air_valve bit (1), 3 ena_retry_air_valve bit (1), 3 cannister_present bit (1), 3 file_or_mach_reel_malf bit (1), 3 inhib_file_mach_sensors bit (1), 3 mbz2 bit (2), 2 mth600_byte12, 3 cannister_drive_on bit (1), 3 cannister_open bit (1), 3 drive_window bit (1), 3 window_up bit (1), 3 drive_hub_motor bit (1), 3 hub_cam_position bit (1), 3 hub_engaged bit (1), 3 cleaner_vacuum_valve bit (1), 2 mth600_byte13, 3 run bit (1), 3 forward bit (1), 3 read_enable bit (1), 3 degauss_time bit (1), 3 go_hi_speed bit (1), 3 check_speed bit (1), 3 tape_on_mach_reel bit (1), 3 LTOR_sensed bit (1), 2 mth600_byte14, 3 NRZI_current_detect bit (1), 3 fwd_hitch_required bit (1), 3 clear_write_amps bit (1), 3 capstan_rewinding bit (1), 3 BOT_sensor bit (1), 3 EOT_sensor bit (1), 3 mach_col_hi_tape_dark bit (1), 3 file_col_hi_tape_dark bit (1), 2 mth600_byte15, 3 data_wrap_mode bit (1), 3 data_security_erase bit (1), 3 mbz4 bit (4), 3 exercisor_present bit (1), 3 semi_auto_sw_on bit (1); dcl 1 chart_1, 2 plus5v_marginal bit (1), 2 plus5v_fault bit (1), 2 plus_or_minus12v_marginal bit (1), 2 plus_12v_fault bit (1), 2 plus_24v_fault bit (1); .spb .fin PL/I Declaration (mtp601_det_stat_def.incl.pl1) .spb .fif dcl 1 mtp601_detail_status unal, 2 mtp610_byte16, 3 track_in_error_reg bit (9), 2 mtp601_byte17, 3 byte_18_par_bit bit (1), 3 byte_19_par_bit bit (1), 3 mbz1 bit (1), 3 TCA_port_num bit (4), 2 mtp601_byte18, 3 nrzi_lo_clip_char bit (8), 2 mtp601_byte19, 3 nrzi_hi_clip_char bit (8), 2 mtp601_byte20, 3 lateral_par_err bit (1), 3 transfer_timing_err bit (1), 3 illegal_char bit (1), 3 multi_trk_err bit (1), 3 skew_error bit (1), 3 postamble_error bit (1), 3 read_hw_error bit (1), 3 selected_mth_den bit (1), 2 mtp601_byte21, 3 hi_clip_parity_err bit (1), 3 lo_clip_par_err bit (1), 3 hi_lo_clip_no_compare bit (1), 3 err_corrected_pe_recd bit (1), 3 mbz2 bit (2), 3 write_hw_error bit (1), 3 mbz3 bit (1), 2 mtp601_byte22, 3 hw_error_loc bit (8), 2 mtp601_byte23, 3 fw_err_loc_code bit (8), 2 mtp601_byte24, 3 fw_err_reg1 bit (8), 2 mtp601_byte25, 3 fw_err_reg2 bit (8), .fin .spb PL/I Declaration mth610_det_stat_def.incl.pl1 .spb .fif dcl 1 mth610_detail_status unal, 2 mth610_byte0, 3 dev_fault bit (1), 3 cmd_code_err bit (1), 3 signal_fault bit (1), 3 multi_bot_stat bit (1), 3 BOT_storage bit (1), 3 EOT_storage bit (1), 3 standby bit (1), 3 margin_condition bit (1), 2 mth610_byte1, 3 load_complete bit (1), 3 lst_cmd_wrt bit (1), 3 lst_cmd_fwd bit (1), 3 rewinding bit (1), 3 wrt_ring_pres bit (1), 3 write_permit bit (1), 3 diag_mode bit (1), 3 cmd_evn_par bit (1), 2 mth610_byte2, 3 current_density bit (3), 3 low_thresh bit (1), 3 dens_capability bit (4), 2 mth610_byte3, 3 mbz1 bit (1), 3 tracks bit (1), 3 ONE bit (1), 3 dev_speed bit (5), 2 mth610_byte4, 3 mbz2 bit (1), 3 increased_deskew bit (1), 3 mbz3 bit (1), 3 dev_address fixed bin (5) uns, 2 mth610_byte5, 3 thresh_select bit (3), 3 revision_status bit (4), 3 cartridge_option bit (1), 2 mth610_byte6, 3 incorrect_spd_det bit (1), 3 main_blower_fail bit (1), 3 over_temp bit (1), 3 lo_air_bearing_press bit (1), 3 device_model bit (4), 2 mth610_byte7, 3 erase_cur_fail bit (1), 3 door_open bit (1), 3 wrt_curr_fail bit (1), 3 auto_hub_air_fail bit (1), 3 fibre_optics_fail bit (1), 3 voltage_fail bit (1), 3 col_vac_fail bit (1), 3 load_unload_fail bit (1), 2 mth610_byte8, 3 drive_cart_open bit (1), 3 cart_open_sw bit (1), 3 drive_cart_closed bit (1), 3 cart_closed_sw bit (1), 3 drive_window_up bit (1), 3 window_up_sw bit (1), 3 drive_window_down bit (1), 3 window_down_sw bit (1), 2 mth610_byte9, 3 ena_diverter_valve bit (1), 3 ena_head_cleaner bit (1), 3 ena_pneumatics bit (1), 3 cartridge_present bit (1), 3 tape_present_sensor bit (1), 3 tape_tension_sensor bit (1), 3 reels_loaded bit (1), 3 columns_loaded bit (1), 2 mth610_byte10, 3 thread_mach_reel bit (1), 3 wrap_mach_reel bit (1), 3 unload_mach_reel bit (1), 3 brake_mach_reel bit (1), 3 drive_mach_reel_cw bit (1), 3 drive_mach_reel_ccw bit (1), 3 ena_mach_reel bit (1), 3 mach_reel_status bit (1), 2 mth610_byte11, 3 thread_file_reel bit (1), 3 always_one bit (1), 3 unload_file_reel bit (1), 3 brake_file_reel bit (1), 3 drive_file_reel_cw bit (1), 3 drive_file_reel_ccw bit (1), 3 ena_file_reel bit (1), 3 file_reel_status bit (1), 2 mth610_byte12, 3 mach_reel_tape_tach bit (1), 3 file_reel_tape_tach bit (1), 3 capstan_tach_A bit (1), 3 capstan_tach_B bit (1), 3 not_unload_fault bit (1), 3 mbz4 bit (1), 3 speed_status bit (1), 3 BOT_sensor bit (1), 2 mth610_byte13, 3 run bit (1), 3 forward bit (1), 3 capstan_go bit (1), 3 hitch bit (1), 3 hi_speed_rewind bit (1), 3 hi_speed_control bit (1), 3 semi_load_sw bit (1), 3 parked bit (1), 2 mth610_byte14, 3 high_current bit (1), 3 degauss_time bit (1), 3 data_security_erase bit (1), 3 erase bit (1), 3 data_wrap bit (1), 3 read_amp_fault bit (1), 3 lo_tape_sensor bit (1), 3 EOT_sensor bit (1), 2 mth610_byte15, 3 ibg_counter bit (8); .fin .spb PL/I Declaration (mtp610_det_stat_def.inl.pl1) .spb .fif dcl 1 mtp610_detail_status unal, 2 mtp610_byte16, 3 track_in_error_reg bit (9), 2 mtp610_byte17, 3 byte_18_par_bit bit (1), 3 byte_19_par_bit bit (1), 3 mbz1 bit (1), 3 TCA_port_num fixed bin (4) uns, 2 mtp610_byte18, 3 multi_use1 bit (8), 2 mtp610_byte19, 3 multi_use2 bit (8), 2 mtp610_byte20, 3 DOS OK bit (1), 3 gcr_underspeed bit (1), 3 DOS_drop bit (1), 3 gcr_trans_timing_err bit (1), 3 operational_in bit (1), 3 raw_dos bit (1), 3 data_out_par_err bit (1), 3 mbz2 bit (1), 2 mtp610_byte21, 3 ac_parity_error bit (1), 3 mbz3 bit (1), 3 envelopes_up bit (1), 3 selected_dev bit (1), 3 request_accepted bit (1), 3 CB_interrupt bit (1), 3 drop_out bit (1), 3 had_data bit (1), 2 mtp610_byte22, 3 mth_status_reg_full bit (1), 3 mth_stat_par_err bit (1), 3 pe_nrzi_par_err bit (1), 3 e3_reg_par_bit bit (1), 3 e2_reg_par_bit bit (1), 3 ac_trans_timing_err bit (1), 3 pe_multi_trk_err bit (1), 3 pe_overload bit (1), 2 mtp610_byte23, 3 c2_1 bit (1), 3 c2_0 bit (1), 3 ill_cod_conv_char bit (1), 3 mod_4_len_err bit (1), 3 lateral_parity_error bit (1), 3 R3_parity_error bit (1), 3 R4_parity_error bit (1), 3 data_out_par_err bit (1), 2 mtp610_byte24, 3 mbz4 bit (4), 3 cb_board bit (1), 3 rc_board bit (1), 3 fx_board bit (1), 3 wd_board bit (1), 2 mtp610_byte25, 3 psi_port_select bit (1), 3 mbz5 bit (1), 3 ac_parity_error bit (1), 3 data_out_parity_error bit (1), 3 OPO_zero_changed bit (1), 3 OPO_one_changed bit (1), 3 wrt_buff_par_err bit (1), 3 reg_zero_par_err bit (1), .fin .brp .hla .inl 0 .fin  s5.hsf.compin 10/22/84 1045.0r w 04/23/82 1024.4 535554 .ifi init_mpm "AN87-01" .srv draft "FNP PROCESSOR" .srv section 5 .ifi l0h "DATANET 6600 Front-End Network Processor" This section gives information on the formats of the status and control words for the DATANET 6600 Front-End Network Processor (FNP). .ifi l1h "FNP Processor Data" The following paragraphs describe the processor instruction formats and instruction opcodes. .ifi l2h "Instruction Word Formats" The FNP instruction word has three formats: .spb Store Reference Instructions .brf Nonstore Reference Instructions - Group 1 .brf Nonstore Reference Instructions - Group 2 .spb .inl 10 .fif 0 0 0 0 0 0 1 _0__1__2__3__________8__9________________7__ | | | | | |I|TAG| OP CODE | DELTA | _|__|____|____________|__________________| 1 2 6 9 .inl 0 .ifi fig "FNP Store Reference Instruction Format" .spb Legend: .spb .inl 10 .unl 10 I indirect addressing flag. .spb .unl 10 TAG index to be used in address preparation. .spb .unl 10 OP CODE instruction operation code. .spb .unl 10 DELTA offset to be used in address preparation. .brp .fif .inl 20 0 0 0 1 _0________________8__9________________7__ | | | | OP CODE | DATA | _|__________________|__________________| 9 9 .inl 0 .ifi fig "FNP Nonstore Reference Instruction Format - Group 1" .spb Legend: .spb .inl 10 .unl 10 OP CODE instruction operation code. .spb .unl 10 DATA data for instruction execution. .fif .inl 0 .inl 20 0 1 1 1 _0______________________1__2__________7__ | | | | OP CODE | DATA | _|________________________|____________| 12 6 .inl 0 .ifi fig "FNP Nonstore Reference Instruction Format - Group 2" .spb Legend: .spb .inl 10 .unl 10 OP CODE instruction operation code. .spb .unl 10 DATA data for instruction execution. .inl 0 .ifi l2h "FNP Operation Code Charts" .ifi tab "Store Reference Instruction Opcodes" .fin .spb 2 .inl 5 ____0________1________2________3________4________5________6________7_____ 0 | | mpf | adcx2 | ldx2 | ldaq | | ada | lda | 1 | tsy | | (grp1)| stx2 | staq | adaq | asa | sta | 2 | szn | dvf | (grp1)| cmpx2 | sbaq | | sba | cmpa | 3 _|__l_d_e_x___|__c_a_n_a___|__a_n_s_a___|_(__g_r_p2_)__|__a_n_a____|__e_r_a____|__s_s_a____|__o_r_a____| 4 | adcx3 | ldx3 | adcx1 | ldx1 | ldi | tnc | adq | ldq | 5 | stx3 | | (grp1)| stx1 | sti | tov | stz | stq | 6 | cioc | cmpx3 | ersa | cmpx1 | tnz | tpl | sbq | cmpq | 7 _|__s_t_e_x___|__t_r_a____|__o_r_s_a___|_(__g_r_p1_)__|__t_z_e____|__t_m_i____|__a_o_s____|________| .ifi tab "Nonstore Reference Instruction Opcodes (Group 1)" .spb .inl 5 .spb 2 _x_=__0________1________2________3________4________5________6________7_____ x12 | rier | | | | ria | | | | x22 | iana | iora | icana | iera | icmpa | | | | x52 | sier | | | | sic | | | | x73 _|__s_e_l____|__i_a_c_x1___|__i_a_c_x2___|__i_a_c_x3___|__i_l_q____|__i_a_q____|__i_l_a____|__i_a_a____| .ifi tab "Nonstore Reference Instruction Opcodes (Group 2)" .inl 5 .spb 2 ____0________1________2________3________4________5________6________7_____ 033 | | | cax2 | | lls | lrs | als | ars | 133 | | | | | nrml | | nrm | | 233 | | nop | cx1a | | llr | lrl | alr | arl | 333 _|________|__i_n_h____|__c_x2__a___|__c_x3__a___|________|________|__a_l_p____|________| 433 | | dis | cax1 | cax3 | | | qls | qrs | 533 | | | | | | | | | 633 | | | | caq | | | qlr | qrl | 733 _|________|__e_n_i____|________|__c_q_a____|________|________|__q_l_p____|________| .ifi tab "Alphabetic Listing of FNP Instruction Opcodes" .spb 2 .fif M__n_e_m_o_n_i_c C__o_d_e M__e_a_n_i_n_g .spb .fin ada 06 Add to A register adaq 15 Add to AQ register adcx1 42 Add character address to index1 adcx2 02 Add character address to index2 adcx3 40 Add character address to index3 .spb adq 46 Add to Q register alp 3336 A register left parity rotate alr 2336 A register left rotate als 0336 A register left shift ana 34 AND to A register .spb ansa 32 AND to storage from A register aos 76 Add one to storage arl 2337 A register right shift logical ars 0337 A register right shift asa 16 Add stored to A register .spb cana 31 Comparative AND with A register caq 6333 Copy A register into Q register cax1 4332 Copy A register into index1 cax2 0332 Copy A register into index2 cax3 4333 Copy A register into index3 .spb cioc 60 Connect I/O channel cmpa 27 Compare with A register cmpq 67 Compare with Q register cmpx1 63 Compare with index1 cmpx2 23 Compare with index2 .spb cmpx3 61 Compare with index3 cqa 7333 Copy Q register into A register cx1a 2332 Copy index1 into A register cx2a 3332 Copy index2 into A register cx3a 3333 Copy index3 into A register .brp .inl 0 .alc Table 6-4 (cont). Alphabetic Listing of FNP Instruction Opcodes .spb .alb .fif M__n_e_m_o_n_i_c C__o_d_e M__e_a_n_i_n_g dis 4331 Delay until interrupt dvf 21 Divide fraction eni 7331 Enable interrupts era 35 EXCLUSIVE OR to A register ersa 62 EXCLUSIVE OR to storage from A register .spb iaa 773 Immediate add to A register iacx1 173 Immediate add character address to index1 iacx2 273 Immediate add character address to index2 iacx3 373 Immediate add character address to index3 iana 022 Immediate AND to A register .spb iaq 573 Immediate add to Q register icana 222 Immediate comparative AND with A register icmpa 422 Immediate compare with A register iera 322 Immediate EXCLUSIVE OR to A register ila 673 Immediate load A register .spb ilq 473 Immediate load Q register inh 3331 Inhibit interrupts iora 122 Immediate OR to A register lda 07 Load A register ldaq 04 Load AQ register .spb ldex 30 Load external channel ldi 44 Load indicators ldq 47 Load Q register ldx1 43 Load index1 ldx2 03 Load index2 .spb ldx3 41 Load index3 llr 2334 Long left rotate lls 0334 Long left shift lrl 2335 Long right shift logical lrs 0335 Long right shift .spb mpf 01 Multiply fraction nop 2331 No operation nrm 1336 Normalize nrml 1334 Normalize long ora 37 OR to A register .spb orsa 72 OR to storage from A register qlp 7336 Q register left parity rotate qlr 6336 Q register left rotate qls 4336 Q register left shift qrl 6337 Q register right shift logical .spb qrs 4337 Q register right shift ria 412 Read interrupt address rier 012 Read interrupt enable register sba 26 Subtract from A register sbaq 24 Subtract from AQ register .spb sbq 66 Subtract from Q register sel 073 Select I/O channel sic 452 Set interrupt cells sier 052 Set interrupt enable register ssa 36 Subtract stored from A register sta 17 Store A register staq 14 Store AQ register stex 70 Store external channel sti 54 Store indicators stq 57 Store Q register .brp .inl 0 .alc Table 6-4 (cont). Alphabetic Listing of FNP Instruction Opcodes .spb .alb .fif M__n_e_m_o_n_i_c C__o_d_e M__e_a_n_i_n_g stx1 53 Store index1 stx2 13 Store index2 stx3 50 Store index3 stz 56 Store zero szn 20 Set zero and negative indicators tmi 75 Transfer on minus tnc 45 Transfer on no carry tnz 64 Transfer on not zero tov 55 Transfer on overflow tpl 65 Transfer on plus tra 71 Transfer unconditionally tsy 10 Transfer and store IC tze 74 Transfer on zero .inl 0 .spb FNP IOM Data .ifi l1toc "FNP IOM Data" .ifi l2toc "IOM Hardware Communications Region Layout" IOM Hardware Communications Region Layout .spb .srv draft "FNP IOM" .fif .inl 18 __________________________________________ .unl 4 450 | | | Interval Timer | _|_________________________________________| .unl 4 451 | | | Elapsed Timer | _|_________________________________________| .unl 4 452 | | | unassigned | _|_________________________________________| .unl 4 454 | | | DIA Peripheral Control Word (PCW) | _|_________________________________________| .unl 4 456 | | | DIA Status ICW | _|_________________________________________| .unl 4 460 | | | Console Status ICW | _|_________________________________________| .unl 4 462 | | | Console Data ICW | _|_________________________________________| .unl 4 464 | | | Card Reader Status ICW | _|_________________________________________| .unl 4 466 | | | Card Reader Data ICW | _|_________________________________________| .unl 4 470 | | | Line Printer Status ICW | _|_________________________________________| .unl 4 472 | | | Line Printer Data ICW | _|_________________________________________| .unl 4 474 | | | unassigned | _|_________________________________________| .unl 4 500 | | | LSLA/HSLA Control Word Areas | | | .inl 0 .bbl . . . .bel .ifi fig "FNP IOM Hardware Communications Region Layout" .fin .brp .ifi l1h "IOM Status Format for DN6670 FNP" .fif 0 6 7 8 9 10 15 16 17 --------------------------------------------------- | | | | | | | | | | | | -------------------------------------------------- | | | | | | | | | | System Bus Faults---- | | | | | | | | IOM Internal Faults--------------- | | | | | | Channel Specific Fault----------------- | | | | I/O Bus Fault----------------------------------- | | Fault Origination--------------------------------------- .fin .ifi l2h "System Bus Faults" .inl 12 .unl 7 mask .unl 7 400000 .brf when one, the IOM detected an uncorrectable error indication (red) from the HNP main storage unit. .spb .unl 7 200000 .brf when one, the IOM received an illegal function code from a component on the system bus. .spb .unl 7 100000 .brf when one, the IOM detected a parity error on data bus lines A and 0 through 7 (left byte). .spb .unl 7 040000 .brf when one, the IOM detected a parity error on data bus lines B and 8 through 15 (right byte). .spb .unl 7 020000 .brf when one, the IOM detected a parity error on the address bus lines. .spb .unl 7 010000 .brf when one, the IOM performed a dead main timeout on the system bus. .spb .unl 7 004000 .brf when one, the IOM detected a bus logic test error or a bus continuity error on the sytem bus. This condition will never initiate the fault reporting sequence but will only be set as an HNP system status indication. .inl 0 .ifi l2h "IOM Internal Faults" .inl 12 .unl 7 mask .unl 7 002000 .brf when one, the IOM detected a read-only storage (ROS) parity error. Any ROS parity error detected while attempting to report any fault halts the I/O processor. .spb .unl 7 001000 .brf when one, the IOM page table unit has indicated a fault. .inl 0 .ifi l2h "Channel Specific Fault" .inl 12 .unl 7 mask .unl 7 000400 .brf Not used. .inl 0 .ifi l2h "I/O Bus Faults" .inl 12 .unl 7 mask .unl 7 000200 .brf when one, the IOM received an illegal function code from a channel on the I/O bus. .spb .unl 7 Bit 11 .unl 7 000100 .brf when one, the IOM detected a parity error on data bus lines A and 0 through 7 (left byte). .spb .unl 7 Bit 12 .unl 7 000040 .brf when one, the IOM detected a parity error on data bus lines B and 8 through 15 (right byte). .spb .unl 7 Bit 13 .unl 7 000020 .brf when one, the IOM detected a parity error on the address bus bits (0 through 7) signal lines. .spb .unl 7 Bit 14 .unl 7 000010 .brf when one, the IOM received an illegal NAK response on the I/O bus. .spb .unl 7 Bit 15 .unl 7 000004 .brf when one, the I/O bus has failed the bus logic text or the IOM has detected an I/O bus continuity error. This condition will never initiate the fault reporting sequence but will only be set as an HNP system status indication. .inl 0 .ifi l2h "Fault Origination" .inl 12 .unl 7 mask .unl 7 000003 .brf when one, the IOM detected the fault and originated this fault status word. .fin .inl 0 .ifi l2h "IOM Fault Status Format" Whenever the FNP IOM detects a channel fault, it stores a fault status word at 420(8) + and interrupts on level 0 for that channel. .brp .fif .inl 20 0 0 0 1 1 1 1 1 1 1 _0______________7__8____0__1____3__4__5__6__7__ | | | | | | | |0 0 0 0 0 0 0 0| OPC | SIC |FLT|A|B| _|________________|______|______|____|__|__| 8 3 3 2 1 1 .inl 0 .ifi fig "FNP IOM Fault Status Word Format" .spb Legend: .spb .inl 10 .unl 10 OPC channel data operation code. .inl +3 .unl 3 0 no data cycle. .unl 3 1 load. .unl 3 2 store. .unl 3 3 add to store. .unl 3 4 subtract from store. .unl 3 5 AND to store. .unl 3 6 OR to store. .unl 3 7 invalid. .spb .unl 13 SIC set interrupt cell operation code. .unl 3 0 none. .unl 3 1 unconditional. .unl 3 2 tally = 0 (TY0). .unl 3 3 tally = 1 (TY1). .unl 3 4 negative. .unl 3 5 zero. .unl 3 6 overflow. .unl 3 7 invalid. .spb .unl 13 FLT fault type code. .unl 3 0 none. .unl 3 1 all other memory illegal actions. .unl 3 2 parity error. .unl 3 3 invalid channel request. .spb .inl -3 .unl 10 A parity error in IOM channel logic. .spb .unl 10 B parity error in IOM central logic. .spb 2 .inl 0 .fin .alb The following combinations of OPC and SIC will cause an invalid channel request fault. .spb .fif .inl 30 O_P_C_ S_I_C_ 7 any any 7 0 0 0 2 0 3 0 4 0 5 0 6 .inl 0 .brp .ifi l2h "Indirect Control Word Formats" .fin .alb The indirect control word (ICW) is used consistently throughout the FNP I/O to control the transmission of data to and from channels of the FNP IOM. Individual channels expect particular conditions in their ICWs and will fault if unexpected conditions are found. .spb 2 .fif .inl 3 0 0 0 1 1 2 2 2 3 _0____2__3____________________________7__8________2__3__4______________________5__ | | | | | | | C | Y |0 0 0 0 0|E| TALLY | _|______|______________________________|__________|__|________________________| 3 15 5 1 12 .inl 0 .ifi fig "FNP IOM ICW Format" .spb Legend: .spb .inl 10 .fin .alb .unl 10 C character control. .inl +4 .unl 4 0 = treat data as 18-bit words. .unl 4 1 = treat data as 36-bit words. .unl 4 2 = treat data as 9-bit bytes starting with byte 0 of Y. .unl 4 3 = treat data as 9-bit bytes starting with byte 1 of Y. .unl 4 4 = treat data as 6-bit bytes starting with byte 0 of Y. .unl 4 5 = treat data as 6-bit bytes starting with byte 1 of Y. .unl 4 6 = treat data as 6-bit bytes starting with byte 2 of Y. .unl 4 7 = indirect idle, no data transmission. .inl -4 .spb .unl 10 Y FNP data address. .brf Some channels will force the LSB of this address to zero in order to ensure access to word pairs. .spb .unl 10 E tally runout. .brf This bit is set when a tally runout condition is detected. If the bit is intentionally set by the software, tallying and address incrementing are suppressed. .spb .unl 10 TALLY count of memory accesses needed for data transfer. .inl 0 .ifi l1h "Peripheral Status/Control Word Formats" Formats of the status words and control words for peripherals are described in the following paragraphs. .ifi l2h "Direct Interface Adapter" .srv draft "FNP DIA" Direct Interface Adapter (DIA) Peripheral Control Word (PCW) - (454-455): .spb 2 The location of the DIA PCW (454) is normally specified as the effective Y-address of the CIOC instruction, i.e., the CIOC operand word and the PCW are the same word. .brp .fif .inl 3 0 1 1 2 2 2 2 2 2 2 3 3 _0__________________________________7__8____0__1__2__3__4__5________9__0__________5__ | | | | | | | | | | ADDRESS |0 0 0|U|L|M|0| LEVEL | OP CODE | _|____________________________________|______|__|__|__|__|__________|____________| 18 3 1 1 1 1 5 6 .inl 0 .ifi fig "FNP DIA PCW Format" .spb Legend: .spb .inl 10 .unl 10 .fin .alb ADDRESS address of a "list ICW" in FNP pointing to a list of "command DCWs". .spb .unl 10 U parity bit for 0-17 giving odd parity for the even FNP word. .spb .unl 10 L parity bit for 18-35 giving odd parity for the odd FNP word. .spb .unl 10 M channel mask bit. .spb .unl 10 LEVEL interrupt level to be sent to the Multics IOM. .spb .unl 10 OP CODE DIA operation code. .inl +4 .unl 4 73 signal an interrupt at LEVEL to the Multics IOM. .unl 4 __ .unl 4 73 with DIA _n_o_t busy -- fetch command DCWs using list ICW at ADDRESS. .brf with DIA busy -- invalid connect. .spb 2 .inl -4 .inl DIA Command Data Control Words (DCWs): .spb 2 The DIA data control words are located at the address specified in the list ICW. The list ICW is located at the address given in the address field of the PCW (see Figure 6-7 above). The list ICW used to access the DIA DCWs must specify 36-bit addressing. .spb 2 .inl 0 First Word Pair .spb 2 .fif .inl 3 0 1 1 2 2 2 2 2 2 3 3 _0__________________________________7__8____0__1__2__3__4__________9__0__________5__ | | | | | | | | | MAIN MEMORY ADDRESS |0 0 0|U|L|0| LEV/ADREXT| OP CODE | _|____________________________________|______|__|__|__|____________|____________| 18 3 1 1 1 6 6 .spb 2 .unl 3 Second Word Pair .spb 2 0 0 0 1 1 2 2 2 2 2 3 _0____2__3____________________________7__8____0__1__2__3__4______________________5__ | | | | | | | | |0 0 1| FNP ADDRESS |0 0 0|U|L|0| TALLY | _|______|______________________________|______|__|__|__|________________________| 3 15 3 1 1 1 12 .inl 0 .ifi fig "FNP DIA DCW Format" .brp Legend: .spb .inl 10 .fin .unl 10 MAIN MEMORY ADDRESS .brf 18 low-order bits of 24-bit Multics absolute main memory address for data. .spb .unl 10 U parity bit for 0-17 giving odd parity for the even FNP word. .spb .unl 10 L parity bit for 18-35 giving odd parity for the odd FNP word. .spb .unl 10 LEV/ADREXT .brf interrupt level for Multics IOM interrupt _o_r six high-order bits of Multics absolute main memory address for data. .spb .unl 10 .fif OP CODE DIA operation code. 65 = read and clear 6180; OR to storage FNP. 70 = disconnect and interrupt FNP. 71 = interrupt FNP. 72 = jump (similar to IOM TDCW). 73 = interrupt Multics at LEV. 74 = report configuration status. 75 = data transfer; FNP to Multics. 76 = data transfer; Multics to FNP. .spb .unl 10 FNP ADDRESS .brf FNP store address for data. .spb .unl 10 TALLY .brf count of memory accesses needed for data transfer. .inl 0 .fin .spb 2 DIA Status Word: .spb 2 The DIA status word location is controlled by the DIA status ICW at (456-457). .spb 2 .fif .inl 3 0 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 _0__________________________3__4__5__6__7__8__9__0__1__2__3__4__5__6__7__8__99__0__1__2__3__4__5__ | | | | | | | | | | | | | | | | | | | | | | | |0 0 0 0 0 0 0 0 0 0 0 0 0 0|a|b|0|c|0 0|d|e|f|g|h|i|j|k|l|m|n|o|p|q|r|s| _|____________________________|__|__|__|__|____|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__| 14 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 .inl 0 .ifi fig "FNP DIA Status Word Format" .spb Legend: .spb .inl 20 .unl 20 M__a_s_k K__e_y M__e_a_n_i_n_g .spb .unl 20 000010 a DIA internal parity error. .unl 20 000004 b FNP software parity error. .unl 20 000001 c Multics IOM/DIA ready. .unl 20 100000 d invalid connect from FNP. .unl 20 040000 e invalid command from FNP. .spb .unl 20 020000 f list ICW tally runout. .unl 20 .inl 0 .vmh 0 .hla 1 |M__a_s_k K__e_y M__e_a_n_i_n_g| .hla 2 |||| .inl 20 .unl 20 010000 g data DCW not direct-36. .unl 20 004000 h Multics main memory address less than lower bound. .unl 20 002000 i Multics main memory address greater than upper bound. .fin .unl 20 .fin 001000 j while inhibited by the restricted cycle switches, an attempt was made to perform a read and clear on main memory and OR to FNP storage; a read interrupt cells; or a data transfer command (FNP to Multics). .brp .unl 20 000400 k test command received while busy. .unl 20 000200 l invalid command from Multics. .unl 20 000100 m no answer from Multics. .unl 20 000040 n List ICW accessed with bit 23 on. .unl 20 000020 o Multics IOM parity error. .spb .unl 20 000010 p command error in Multics IOM. .unl 20 000004 q U-bus error in Multics IOM. .unl 20 000002 r data parity error in Multics IOM. .unl 20 000001 s Multics IOM system fault. .inl 0 .hla .srv draft "FNP CONSOLE" .ifi l2h "Console" Console Peripheral Control Word (PCW): .spb 2 This word is located at the effective Y-address specified by the CIOC instruction. .spb 2 .fif .inl 3 0 2 2 2 2 3 3 _0____________________________________________2__3__4__________9__0__________5__ | | | | | |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0|M|0 0 0 0 0 0| OP CODE | _|______________________________________________|__|____________|____________| 23 1 6 6 .inl 0 .ifi fig "FNP Console PCW Format" .spb Legend: .spb .inl 10 .unl 10 M channel mask bit. .spb .unl 10 OP CODE channel operation code. .inl +4 .unl 4 00 = request status. .unl 4 44 = write. .unl 4 50 = read. .fin .unl 4 54 = wraparound mode. .inl 0 .fin .inl 0 .ifi l2h "Console Data Format" Data is transmitted as 9-bit characters under control of the data ICW at (462-463). .brp .ifi l2h "Console Status Word Format" Status is stored as a 9-bit byte under control of the status ICW at (460-461). .fif .spb 2 .inl 20 _b_i_t _n_a_m_e 0 device ready. 1 timer runout. 2 tally runout. 3 pre-tally runout. 4 transfer timing error. 5 control character. 6 connect while busy. 7 invalid PCW. 8 parity on read. .fin .inl 0 .srv draft "FNP CARD READER" .ifi l2h "Card Reader" Card Reader Peripheral Control Word (PCW): .spb 2 This word is located at the effective Y-address specified by the CIOC instruction. .spb 2 .fif .inl 3 0 2 2 2 2 3 3 _0____________________________________________2__3__4__________9__0__________5__ | | | | | |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0|M|0 0 0 0 0 0| OP CODE | _|______________________________________________|__|____________|____________| 23 1 6 6 .fin .inl 0 .ifi fig "FNP Card Reader PCW Format" .fif .spb Legend: .spb .inl 10 .unl 10 M channel mask bit. .spb .fif .unl 10 OP CODE channel operation code. 00 = request status. 01 = read card binary. 02 = read card decimal. 03 = read card mixed. 40 = reset status. .fin .inl 0 .ifi l2h "Card Reader Data Format" Data is read as 6-bit characters under control of the data ICW at (466-467). .brp .ifi l2h "Card Reader Status Word Format" Status is stored as a 36-bit peripheral status word under control of the status ICW at (464-465). See "Channel Status" in Section!3 for format and "Card Readers" in Section!5 or Appendix C for a description of the appropriate fields. .spb 2 .inl 12 .unl 7 NOTE: The FNP does not support the CRU1050. The older CR10 and CR20 sometimes used for the FNP store the same status as the CRZ201. .inl 0 .srv draft "FNP LINE PRINTER" .ifi l2h "Line Printer" .fin Line Printer Peripheral Control Word (PCW): .spb 2 This word is located at the effective Y-address specified by the CIOC instruction. .spb 2 .fif .inl 3 0 2 2 2 2 3 3 _0____________________________________________2__3__4__________9__0__________5__ | | | | | |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0|M|0 0 0 0 0 0| OP CODE | _|______________________________________________|__|____________|____________| 23 1 6 6 .inl 0 .ifi fig "FNP Line Printer PCW Format" .spb Legend: .spb .inl 10 .unl 10 M channel mask bit. .spb .unl 10 .fif OP CODE channel operation code. 00 = request status. 10 = write nonedited, no slew. 11 = write nonedited, slew one line. 12 = write nonedited, slew two lines. 13 = write nonedited, slew to top. 30 = write edited, no slew. 31 = write edited, slew one line. 32 = write edited, slew two lines. 33 = write edited, slew to top. 40 = reset status. 61 = slew one line. 62 = slew two lines. 63 = slew to top. .inl 0 .fin .ifi l2h "Line Printer Data Format" Data is written as 6-bit characters under control of the data ICW at (472-473). .brp .ifi l2h "Line Printer Status Word Format" Status is stored as a 36-bit peripheral status word under control of the status ICW at (470-471). See "Channel Status" in Section!3 for format and "Line Printers" in Section!5 or Appendix C for a description of the appropriate fields. .spb 2 .inl 12 .unl 7 NOTE: The FNP does not support the PRU1200 or PRU1600. .inl 0 .srv draft "FNP LSLA" .ifi l2h "Low-Speed Line Adapter" Low-Speed Line Adapter (LSLA) Peripheral Control Words (PCWs): .spb 2 This word is located at the effective Y-address specified by the CIOC instruction. .spb .fif P_C_W_0_ .spb 2 .inl 3 0 0 0 0 0 2 2 2 3 _0__1__2______5__6________________________________2__3__4______________________5__ | | | | | | |0 0| COMND |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0|M|0 0 0 0 0 0 0 0 0 0 0 0| _|____|________|__________________________________|__|________________________| 2 4 17 1 12 .ifi fig "FNP LSLA PCW0 Format" .spb Legend: .spb .inl 10 .unl 10 COMND channel command. (See "LSLA PCW Commands" below.) .spb .unl 10 M channel mask bit. .inl 0 .spb 1 P_C_W_1_ .spb 2 .inl 3 .fif 0 0 0 0 0 2 2 2 2 2 2 2 3 3 3 3 _0__1__2______5__6________________________________2__3__4____6__7__8__9__0__1__2______5__ | | | | | | | | | | | | |0 1| COMND |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0|M|0 0 0|a|b|c|d|e|0 0 0 0| _|____|________|__________________________________|__|______|__|__|__|__|__|________| 2 4 17 1 3 1 1 1 1 1 4 .inl 0 .ifi fig "FNP LSLA PCW1 Format" .brp Legend: .spb .inl 30 .unl 30 M__a_s_k K__e_y F__i_e_l_d M__e_a_n_i_n_g .spb .unl 30 170000 COMND channel command. (See "LSLA PCW Commands" below.) .spb .unl 30 010000 M channel mask bit. .spb .inl 0 .vmh 0 .hla 1 |M__a_s_k K__e_y F__i_e_l_d M__e_a_n_i_n_g| .hla 2 || .inl 30 .unl 30 000400 a set receive mode. .spb .unl 30 000200 b set send mode. .spb .unl 30 000100 c set wraparound mode. .spb .unl 30 000040 d set data terminal ready. .spb .unl 30 000020 e set request to send. .fin .inl 0 .ifi l2h "LSLA PCW Commands" .inl 10 COMND Command 00 no command (needed for broadside channel commands). 01 input status request. 02 output status request. 03 configuration status request. 06 switch receive ICW. 07 switch send ICW. 10 initialize. 14 resynchronize. .inl 0 .alb .fin .ifi l2h "LSLA Control Word Area" Each LSLA has a dedicated 16-word control area. See "FNP Store Map" later in this section for area locations. .spb 2 .fif .inl 5 relative _a_r_e_a__a_d_d_r _f_u_n_c_t_i_o_n .spb 0-1 primary receive ICW 2-3 secondary receive ICW 4-5 primary send ICW 6-7 secondary send ICW 10-11 not used 12-13 not used 14-15 active status ICW 16-17 configuration status mailbox .spb 2 .inl 12 NOTE: All data ICWs specify 9-bit characters. .inl 0 .brp .hla .ifi l2h "LSLA Active Status Word Format" .fin Active status is stored as one 36-bit word under control of the status ICW at |14. .spb 2 .fif .inl 3 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 2 2 2 2 2 2 3 3 3 3 _0__1____3__4__5__6__7__8__9__0__1__2__3________7__8__9__0__1__________6__7__8__9__0__1__2______5__ | | | | | | | | | | | | | | | | | | | | | | |a|0 0 0|b|c|d|e|0 0|f|0|g|0 0 0 0 0|h|i|j|0 0 0 0 0 0|k|l|m|n|o|0 0 0 0| _|__|______|__|__|__|__|____|__|__|__|__________|__|__|__|____________|__|__|__|__|__|________| 1 3 1 1 1 1 2 1 1 1 5 1 1 1 6 1 1 1 1 1 4 .inl 0 .ifi fig "FNP LSLA Active Status Word Format" .spb Legend: .spb .inl 20 .unl 20 M__a_s_k K__e_y M__e_a_n_i_n_g .spb .fif .unl 20 400000 a status type. .brf 0 = send status. 1 = receive status. .brf .unl 20 020000 b active buffer. 0 = primary buffer (ICW) in use. .brf 1 = secondary buffer (ICW) in use. .brf .unl 20 010000 c 1 = buffers (ICWs) switched after status store. .brf .unl 20 004000 d 1 = TY0 tally condition. .brf .unl 20 002000 e 1 = TY1 tally condition. .fin .spb .unl 20 000200 f data set status change (receive only). .fin .alb .brf If data set ready changes state or if a data terminal ready PCW is sent and either clear to send or carrier detect (i or j below) changes state, an active status interrupt occurs and receive status is stored with this bit set. .brf .unl 20 000040 g transfer timing error. .brf .unl 20 400000 h data set ready. .brf .unl 20 200000 i clear to send. .brf .unl 20 100000 j carrier detect. .spb .unl 20 000400 k receive mode. .brf .unl 20 000200 l send mode. .brf .unl 20 000100 m wraparound mode. .brf .unl 20 000040 n data terminal ready. .brf .unl 20 000020 o request to send. .inl 0 .brf .ifi l2h "LSLA Configuration Status Word Format" .fin Configuration status is stored as one 36-bit word into the configuration status mailbox at |16. .fif .spb 2 .inl 3 0 0 0 0 0 1 1 1 2 2 2 2 2 3 _0__1__2____________8__9__________4__5__6____________2__3__4______7__8______________5__ | | | | | | | | | | |1|a| (06)8 |0 0 0 0 0 0|b|0 0 0 0 0 0 0|c|0 0 0 0| (026)8 | _|__|__|______________|____________|__|______________|__|________|________________| 1 1 6 6 1 7 1 4 8 .inl 0 .ifi fig "FNP LSLA Configuration Status Word" .spb Legend: .spb .inl 20 .unl 20 K__e_y F__i_e_l_d M__e_a_n_i_n_g .spb .unl 20 a 1 = synchronous. .spb .unl 10 (06)8 subchannel type (always 06 for LSLA). .spb .unl 20 b 1 = two send ICWs being used. .spb .unl 20 c 1 = 8-bit characters. .spb .unl 10 (026)8 line synchronizing character. .inl 0 .ifi l2h "LSLA Device Command Characters" .fin .alb The LSLA is able to send device commands to the modems on its subchannels and to exercise the T&D subchannel by means of command character sequences transmitted as data. Device status returned from the modems and the T&D subchannel are recognized by a similar character sequence. The character sequence consists of an ESC character with odd parity (233)8, followed by any number (including zero) of fill characters (037)8, followed by one of the command/status characters below. .spb 2 .fif .inl 3 Device Control Device Control Special Control (without ACU) (with ACU) .spb 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 _0__1__2__3__4__5__6__7__8__ _0__1__2__3______6__7__8__ _0__1__2__3__________8__ | | | | | | | | | | | | | | | | | | | | | | |0|P|1|a|b|c|d|e|f| |0|P|1| DIGIT |g|h| |0|P|0| OP CODE | _|__|__|__|__|__|__|__|__|__| _|__|__|__|________|__|__| _|__|__|__|____________| 1 1 1 1 1 1 1 1 1 1 1 1 4 1 1 1 1 1 6 .inl 0 .ifi fig "FNP LSLA Device Control Characters" .spb .brp Legend: .spb .inl 30 .unl 30 M__a_s_k K__e_y F__i_e_l_d M__e_a_n_i_n_g .spb .unl 30 200 P parity bit giving odd parity to the character. .brf .unl 30 040 a frequency select. .brf .unl 30 020 b answer control for Bell 103E modem. .brf .unl 30 010 c busy. .brf .unl 30 004 d data terminal ready. .unl 30 .brf 002 e request to send. .brf .unl 30 001 f line break transmit. .spb .unl 30 074 DIGIT binary value of next digit to be dialed. .brf .unl 30 002 g call request. .brf .unl 30 001 h digit present. .fif .spb .unl 30 077 OP CODE special channel command. 40 = error count command. 41 = unused. 44 = low-speed wraparound reset. 45 = low-speed wraparound set. 50 = high-speed wraparound. 51 = configuration mode command. 54 = disable protect. 55 = channel status request. .fin .brf .inl 0 .ifi l2h "LSLA Device Status Characters" .inl 3 .fif Device Status Device Status Special Status (without ACU) (with ACU) (via T&D channel) .spb 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 _0__1__2__3__4__5__6__7__8__ _0__1__2__3__4__5__6__7__8__ _0__1__2__3______6__7__8__ | | | | | | | | | | | | | | | | | | | | | | | | | | | |0|P|1|a|b|c|d|e|f| |0|P|1|g|h|i|j|k|l| |0|P|0| CNT |0|0| _|__|__|__|__|__|__|__|__|__| _|__|__|__|__|__|__|__|__|__| _|__|__|__|________|__|__| 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 4 1 1 .inl 0 .ifi fig "FNP LSLA Device Status Character Formats" .spb Legend: .spb .inl 30 .unl 30 M__a_s_k K__e_y F__i_e_l_d M__e_a_n_i_n_g .spb .unl 10 P parity bit giving odd parity to the character. .brf .unl 30 040 a data set ready. .brf .unl 30 020 b restraint. .brf .unl 30 010 c clear to send. .brf .unl 30 004 d ring. .brf .unl 30 002 e carrier detect. .brf .unl 30 001 f line break. .spb .unl 30 040 g power indicator. .brf .unl 30 020 h data set status. .brf .unl 30 010 i present (send) next digit. .brf .unl 30 004 j data line occupied. .brf .unl 30 002 k abandon call and retry. .brf .unl 30 001 l used only by T&D. .spb .unl 10 CNT binary error count. .inl 0 .fin .srv draft "FNP HSLA" .ifi l2h "High-Speed Line Adapter" .fin High-Speed Line Adapter (HSLA) Peripheral Control Word (PCW) Formats: .spb 2 This word is located at the effective Y-address specified by the CIOC instruction. .spb 1 .fif .inl 0 P_C_W_0_ .spb 2 .inl 3 0 0 0 0 0 0 1 1 3 _0__1__2______5__6__7________1__2______________________________________________5__ | | | | | | | |0|0| COMND |0| SUBCHAN |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| _|__|__|________|__|__________|________________________________________________| 1 1 4 1 5 24 .inl 0 .ifi fig "FNP HSLA PCW0 Format" .spb Legend: .spb COMND subchannel command. (See "HSLA PCW Commands" below.) .spb SUBCHAN subchannel number. .spb 1 .inl 0 P_C_W_1_ .fif .spb 2 .fif .inl 3 0 0 0 0 0 0 1 1 2 2 2 2 2 2 3 3 3 3 3 3 _0__1__2______5__6__7________1__2______________________3__4____6__7__8__9__0__1__2__3__4__5__ | | | | | | | | | | | | | | | | | |0|1| COMND |0| SUBCHAN |0 0 0 0 0 0 0 0 0 0 0 0| RES |a|b|c|d|e|f|g|h|i| _|__|__|________|__|__________|________________________|______|__|__|__|__|__|__|__|__|__| 1 1 4 1 5 12 3 1 1 1 1 1 1 1 1 1 .inl 0 .ifi fig "FNP HSLA PCW1 Format" .fin .brp Legend: .spb .inl 30 .unl 30 .fin M__a_s_k K__e_y F__i_e_l_d M__e_a_n_i_n_g .spb .unl 30 170000 COMND subchannel command. (See "HSLA PCW Commands" below.) .unl 30 003700 SUBCHAN subchannel number. .spb .unl 30 007000 RES unassigned, reserved for broadside commands. .spb .unl 30 000400 a set receive mode. .unl 30 000200 b set send mode. .brf .unl 30 000100 c set wraparound mode. .unl 30 000040 d set data terminal ready. .unl 30 .unl 30 .unl 30 000004 g supervisory send. .brf .unl 30 000002 h ACU call request. .brf .unl 30 000001 i spare. .spb 1 .inl 0 P_C_W_2_ .fif .spb 2 .inl 3 0 0 0 0 0 0 1 1 1 1 1 1 1 1 2 2 2 2 2 2 3 3 3 3 3 3 _0__1__2______5__6__7________1__2__3__4__5__6__7__8__________3__4__5____7__8__9__0__1__2__3__4__5__ | | | | | | | | | | | | | | | | | | | | | | | |1|0| COMND |0| SUBCHAN |a|b|c|d|e|f|0 0 0 0 0 0|g|0 0 0|h|i|j|k|l|m|n|o| _|__|__|________|__|__________|__|__|__|__|__|__|____________|__|______|__|__|__|__|__|__|__|__| 1 1 4 1 5 1 1 1 1 1 1 6 1 3 1 1 1 1 1 1 1 1 .fin .inl 0 .ifi fig "FNP HSLA PCW2 Format" .spb Legend: .fin .spb .inl 30 .unl 30 M__a_s_k K__e_y F__i_e_l_d M__e_a_n_i_n_g .spb .unl 30 170000 COMND subchannel command. (See "HSLA PCW Commands" below.) .unl 30 037000 SUBCHAN subchannel number. .spb .inl 0 .vmh 0 .hla 1 |M__a_s_k K__e_y F__i_e_l_d M__e_a_n_i_n_g| .hla 2 || .inl 30 .unl 30 000040 a receive data has parity. .unl 30 000020 b send data has parity. .brf .unl 30 000010 c use odd parity. .brf .unl 30 000004 d use two send ICWs. .unl 30 000002 e enable character control table (CCT). .unl 30 000001 f spare. .spb .unl 30 004000 g 0 = one stop bit. .brf 1 = two stop bits. .unl 30 000200 h set 110 baud. .brf .unl 30 000100 i set 134.5 baud. .unl 30 000040 j set 150 baud. .unl 30 000020 k set 300 baud. .unl 30 000010 l set 1050 baud. .unl 30 000004 m set 1200 baud. .brf .unl 30 000002 n set 1800 baud. .unl 30 000001 o set optional baud rate (e.g., 75 or 600). .inl 0 .hla .brp P_C_W_3_ .fif .spb 2 .inl 3 0 0 0 0 0 0 1 1 1 1 1 1 1 1 2 2 2 2 3 _0__1__2______5__6__7________1__2__3__4__5__6__7__8__________3__4______7__8______________5__ | | | | | | | | | | | | | | | |1|1| COMND |0| SUBCHAN |a|b|c|d|e|f|0 0 0 0 0 0| RES | SYNC CHAR | _|__|__|________|__|__________|__|__|__|__|__|__|____________|________|________________| 1 1 4 1 5 1 1 1 1 1 1 6 4 8 .inl 0 .fin .ifi fig "FNP HSLA PCW3 Format" .spb Legend: .spb .inl 30 .unl 30 M__a_s_k K__e_y F__i_e_l_d M__e_a_n_i_n_g .spb .unl 30 170000 COMND subchannel command. (See "HSLA PCW Commands" below.) .spb .unl 30 003700 SUBCHAN subchannel number. .spb .unl 30 000040 a receive data has parity. .brf .unl 30 000020 b send data has parity. .brf .unl 30 000010 c use odd parity. .brf .unl 30 000004 d use two send ICWs. .brf .unl 30 000002 e enable character control table (CCT). .brf .unl 30 000001 f spare. .spb .unl 30 007400 RES reserved for subchannel use. .spb .unl 30 000377 SYNC CHAR subchannel synchronizing character. .inl 0 .hla .ifi l2h "HSLA PCW Commands" .inl 10 .unl 10 .fif PCW0,1 COMND Command .alb 00 no command (needed for broadside commands). 01 subchannel input status request. 02 subchannel output status request. 03 subchannel configuration status request. 04 set subchannel mask register bit. 05 reset subchannel mask register bit. 06 switch subchannel receive data buffers (ICWs). 07 switch subchannel send data buffers (ICWs). 10 initialize (all subchannels). 11 store mask register (into subchannel 0 control word area). 12 not used. 13 not used. 14 resynchronize subchannel. 15 transmit line break. 16 not used. 17 not used. .spb 2 .unl 10 PCW2,3 COMND Command 00-07 reserved. 10-13 not used. 14 set 5-bit character (asynchronous). 15 set 6-bit character. 16 set 7-bit character. 17 set 8-bit character. .alb .fin .inl 0 .brp .ifi l2h "HSLA Control Word Areas" Each HSLA subchannel has a dedicated 16-word control word subarea located at 16 * SUBCHAN within the control word area for the HSLA. See "FNP Store Map" later in this section for HSLA control word area locations. .fif .spb 2 .inl 5 relative _a_r_e_a__a_d_d_r _f_u_n_c_t_i_o_n .spb 1 0-1 primary receive ICW. 2-3 secondary receive ICW. 4-5 primary send ICW. 6-7 secondary send ICW. 10 base address word. 11 unused. 12-13 mask register (subchannel 0 only) 14-15 active status ICW 16-17 configuration status mailbox. .inl 0 .brf .ifi l2h "Base Address Word Format" .fin .alb The base address word (BAW) is used by the character control feature of the HSLA to prepare addresses for referencing of the character control table (CCT). .spb 2 .fif .inl 21 0 0 0 1 1 1 1 1 1 _0________________8__9__0__1__2____4__5____7__ | | | | | | | BA | M |S|0 0 0| TSF | _|__________________|____|__|______|______| 9 2 1 3 3 .inl 0 .ifi fig "FNP HSLA BAW Format" .spb Legend: .spb BA base address of character control table (CCT). .spb M modifier (used for CCT packing). .spb S short table indicator. .spb TSF table switch field. .inl 0 .ifi l2h "Character Control" .fin .alb The character control feature of the HSLA allows each subchannel to employ its own arbitrary set of control characters. If character control is enabled (see Figures 6-21 and 6-22 above), a reference is made for each data character received to a character control table (CCT) that specifies the action to be taken for that character. .brp Character control characters are stored as 9-bit characters in the CCT and are selected by the following addressing algorithm: .spb 2 .fif L(CCC) = 00 || B1 || (BAW.BA + BAW.TSF) || (BAW.M | (B7 || B6)) .brf || (B5 || B4 || B3 || B2) .fin .spb 2 .fif where: .inl 5 .spb "||" -> concatenation. "|" -> logical OR. B_n -> _nth bit of data character (B1 = LSB). "." -> PL/I structure qualifier flag. .spb 2 .fin .alb .inl 0 BAW.M is used to pack CCTs for short (5-, 6-, 7-bit) codes and BAW.TSF is a dynamic offset, which may be changed by a reference to a character control character (CCC). .ifi l2h "Character Control Character Format" .fif .inl 30 0 0 0 0 0 0 0 _0____2__3__4__5__6____8__ | | | | | | | TSF |R|S|P| CMD | _|______|__|__|__|______| 3 1 1 1 3 .inl 0 .ifi fig "FNP HSLA CCC Format" .spb Legend: .spb .inl 10 .unl 10 TSF table switch field for next CCT reference. .spb .unl 10 R resynchronize. .spb .unl 10 S switch buffers. .spb .unl 10 P inhibit parity. .spb .unl 10 CMD command field. (All codes, except 6, store character.) .fif 0 = no special action. 1 = terminate after next character. 2 = terminate after second character. 3 = terminate now. 4 = set marker status bit only. 5 = marker interrupt after next character. 6 = do not store character. 7 = marker interrupt now. .inl 0 .brp .ifi l2h "Mask Register Word Format for DN355 or DN6632 FNPs" (This word is stored for subchannel 0 only.) .fif .spb 2 .inl 3 0 3 3 3 3 _0______________________________________________________________1__2____4__5__ | | | | | Subchannel mask bits, channel 0-31 | PRI |1| _|________________________________________________________________|______|__| 32 3 1 .inl 0 .ifi fig "FNP HSLA Mask Register Word Format" .spb Legend: .spb .inl 10 .unl 10 PRI indicates which subchannels will receive priority service from the HSLA central. .spb P_R_I_ M__e_a_n_i_n_g .brf 000 No high priority scan .brf 001 Subchannels 0 and 1 .brf 010 Subchannels 0 through 3 .brf 011 Subchannels 0 through 7 .brf 100 Subchannels 0 through 15 .ifi l2h "Mark Register Word for DN6670 FNPs" (This word is stored for subchannels 0, 8, 16 and 24.) .spb 2 .inl 5 .fif ----------------------------------------------------- | 0 | 1 ---------------> 8 | 9 --------------> 17 | ----------------------------------------------------- | | SUBCHANNELS | | | | 0 thru 7 | NOT USED | ----------------------------------------------------- | INDICATES |--------UPDATE .ifi fig "DN6670 Mask Status Word" .spb .inl .fin .ifi l2h "HSLA Active Status Word Format" .fin .alb Active status from subchannels is stored under control of the status ICW at (14-15) in the subchannel control word area. .fif .spb 2 .fif .inl 3 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 _0__1__2__3__4__5__6__7__8__9__0__1__2__3__4__5__6__7__8__9__0__1__2__3__4__5__6__7__8__9__0__1__2__3__4__5__ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |a|b|c|d|e|f|g|h|i|j|k|0|l|0 0|m|n|o|p|q|r|s|t|u|v|w|0|x|y|z|A|B|C|D|E|0| _|__|__|__|__|__|__|__|__|__|__|__|__|__|____|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__| 1 1 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 .inl 0 .ifi fig "FNP HSLA Active Status Word Format" .brp Legend: .spb .inl 20 .unl 20 M__a_s_k K__e_y M__e_a_n_i_n_g .spb .unl 20 400000 a status type. .brf .fif 0 = send status. 1 = receive status. .fin .unl 20 200000 b normal marker character received. .unl 20 100000 c delayed marker character received. .unl 20 040000 d terminate character received. .unl 20 020000 e secondary buffer (ICW) is active. .spb .inl 0 .hla 1 |M__a_s_k K__e_y M__e_a_n_i_n_g| .hla 2 || .vmh 0 .inl 20 .unl 20 010000 f switch buffers (ICWs) after status store. .*TR12920 documented below 4/23/82 .unl 20 .cbn 004000 g TY0 tally condition. (tally runout) .unl 20 002000 h TY1 tally condition. (pre-tally runout) .cbf .unl 20 001000 i received character parity error. .unl 20 000400 j command to unimplemented subchannel. .brp .spb .unl 20 000200 k change in data set status occurred. .unl 20 000040 l transfer timing error. .unl 20 000004 m no stop bit received. .unl 20 000002 n data line occupied (ACU). .unl 20 000001 o power (ACU). .unl 20 .spb 400000 p data set ready. .unl 20 200000 q clear to send. .unl 20 100000 r carrier detect. .unl 20 040000 s supervisory receive. .unl 20 020000 t abandon call and retry (ACU). .spb .unl 20 010000 u data set status (ACU). .unl 20 004000 v ring indicator. .unl 20 002000 w line break. .unl 20 000400 x receive mode. .unl 20 000200 y send mode. .spb .unl 20 000100 z wraparound mode. .unl 20 000040 A data terminal ready. .unl 20 000020 B request to send. .unl 20 000010 C make busy. .unl 20 000004 D supervisory send. .unl 20 000002 E call request (ACU). .hla .inl 0 .brf .ifi l2h "HSLA Configuration Status Word Format" .fin .alb .fin Subchannel configuration status is stored directly into the configuration status mailbox at (16-17) in the subchannel control word area. .spb 2 .fif .fif .inl 3 0 0 0 0 0 0 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 _0__1__2__3__________8__9____1__2__3__4__5__6__7____9__0__1__2__3__4__5____7__8__9__0__1__2__3__4__5__ | | | | | | | | | | | | | | | | | | | | | | | | | | |1|a|0| TYPE |0 0 0|b|c|d|e|f|0 0 0|g|h|i|j|k|0 0 0|l|m|n|o|p|q|r|s| _|__|__|__|____________|______|__|__|__|__|__|______|__|__|__|__|__|______|___S_Y_N_C__C_H_A_R____|_ 1 1 1 6 3 1 1 1 1 1 3 1 1 1 1 1 3 1 1 1 1 1 1 1 1 (8) .inl 0 .ifi fig "FNP HSLA Configuration Status Word Format" .spb Legend: .spb .inl 20 .unl 20 M__a_s_k K__e_y M__e_a_n_i_n_g .spb .unl 20 200000 a 0 = asynchronous subchannel. .brf 1 = synchronous subchannel. .spb .inl 0 .hla 1 |M__a_s_k K__e_y M__e_a_n_i_n_g| .hla 2 || .vmh 0 .inl 20 .unl 20 077000 TYPE subchannel type. .brf 00 = invalid. .brf 01 = general purpose. .brf 02 = general purpose with ACU. .brf 03 = dual synchronous. .brf 04 = dual synchronous with ACU. .brf 05 = dual asynchronous (EIA). .brf 06 = reserved for synchronous line adapter. .brf 07 = dual asynchronous (direct). .brf 10-77 = unassigned. .spb .unl 20 000040 b check parity on receive. .brf .unl 20 000020 c generate parity on send. .brf .unl 20 000010 d 0 = use even parity. .brf 1 = use odd parity. .brf .unl 20 000004 e use two send ICWs. .brf .unl 20 000002 f use BAW (enable character control). .spb .unl 20 100000 g 5-bit characters if asynchronous. .brf .unl 20 040000 h 6-bit characters. .brf .unl 20 020000 i 7-bit characters. .brf .unl 20 010000 j 8-bit characters. .brf .unl 20 004000 k two stop bits. .spb .unl 20 000200 l 110 baud if asynchronous. .brf .unl 20 000100 m 134.5 baud if asynchronous. .brf .unl 20 000040 n 150 baud if asynchronous. .brf .unl 20 000020 o 300 baud if asynchronous. .brf .unl 20 000010 p 1050 baud if asynchronous. .brf .unl 20 000004 q 1200 baud if asynchronous. .brf .unl 20 000002 r 1800 baud if asynchronous. .brf .unl 20 000001 s optional baud rate (e.g., 75 or 600) if asynchronous. .spb .unl 20 000377 SYNC CHAR synchronizing character if synchronous. .fin .hla .inl 0 .fin .alb .srv draft "FNP ENVIRONMENT" .ifi l1h "FNP Environment" The following paragraphs explain the hardware environment in which the FNP code executes. .ifi l2h "Interrupt Assignments" .fin The FNP has 256 interrupts organized into 16 levels of 16 interrupts each. Each interrupt within a level corresponds to a bit in the interrupt cell word for that level. When an interrupt occurs, a tsy instruction is forced that makes an indirect reference to location 20(8)*(bit position) + (level). .brf .ifi tab "FNP Interrupt Assignment Map" .fif .spb 2 .fif .inl 5 ___0_0_0______0_0_1______0_0_2______0_0_3______0_0_4______0_0_5______0_0_6______0_0_7____ 0 | cnsF | cnsS | cnsT | diaS00| H0A00 | H0A16 | H0C00 | H0C16 | 10 | H1A00 | H1A16 | H1C00 | H1C16 | H2A00 | H2A16 | H2C00 | H2C16 | 20 | cdrF | cdrS | cdrT | diaS01| H0A01 | H0A17 | H0C01 | H0C17 | 30 _|_H_1_A_0_1___|_H_1_A_1_7___|_H_1_C_0_1___|_H_1_C_1_7___|_H_2_A_0_1___|_H_2_A_1_7___|_H_2_C_0_1___|_H_2_C_1_7___| 40 | prtF | prtS | prtT | diaS02| H0A02 | H0A18 | H0C02 | H0C18 | 50 | H1A02 | H1A18 | H1C02 | H1C18 | H2C02 | H2A18 | H2C02 | H2C18 | 60 | | | | diaS03| H0A03 | H0A19 | H0C03 | H0C19 | 70 _|_H_1_A_0_3___|_H_1_A_1_9___|_H_1_C_0_3___|_H_1_C_1_9___|_H_2_A_0_3___|_H_2_A_1_9___|_H_2_C_0_3___|_H_2_C_1_9___| 100 | diaF | | diaT | diaS04| H0A04 | H0A20 | H0C04 | H0C20 | 110 | H1A04 | H1A20 | H1C04 | H1C20 | H2A04 | H2A20 | H2C04 | H2C20 | 120 | | | | diaS05| H0A05 | H0A21 | H0C05 | H0C21 | 130 _|_H_1_A_0_5___|_H_1_A_2_1___|_H_1_C_0_5___|_H_1_C_2_1___|_H_2_A_0_5___|_H_2_A_2_1___|_H_2_C_0_5___|_H_2_C_2_1___| 140 | H0F | | | diaS06| H0A06 | H0A22 | H0C06 | H0C22 | 150 | H1A06 | H1A22 | H1C06 | H1C22 | H2A06 | H2A22 | H2C06 | H2C22 | 160 | H1F | | | diaS07| H0A07 | H0A23 | H0C07 | H0C23 | 170 _|_H_1_A_0_7___|_H_1_A_2_3___|_H_1_C_0_7___|_H_1_C_2_3___|_H_2_A_0_7___|_H_2_A_2_3___|_H_2_C_0_7___|_H_2_C_2_3___| 200 | H2F | | | diaS08| H0A08 | H0A24 | H0C08 | H0C24 | 210 | H1A08 | H1A24 | H1C08 | H1C24 | H2A08 | H2A24 | H2C08 | H2C24 | 220 | L0F | L0A | L0C | diaS09| H0A09 | H0A25 | H0C09 | H0C25 | 230 _|_H_1_A_0_9___|_H_1_A_2_5___|_H_1_C_0_9___|_H_1_C_2_5___|_H_2_A_0_9___|_H_2_A_2_5___|_H_2_C_0_9___|_H_2_C_2_5___| 240 | L1F | L1A | L1C | diaS10| H0A10 | H0A26 | H0C10 | H0C26 | 250 | H1A10 | H1A26 | H1C10 | H1C26 | H2A10 | H2A26 | H2C10 | H2C26 | 260 | L2F | L2A | L2C | diaS11| H0A11 | H0A27 | H0C11 | H0C27 | 270 _|_H_1_A_1_1___|_H_1_A_2_7___|_H_1_C_1_1___|_H_1_C_2_7___|_H_2_A_1_1___|_H_2_A_2_7___|_H_2_C_1_1___|_H_2_C_2_7___| 300 | L3F | L3A | L3C | diaS12| H0A12 | H0A28 | H0C12 | H0C28 | 310 | H1A12 | H1A28 | H1C12 | H1C28 | H2A12 | H2A28 | H2C12 | H2C28 | 320 | L4F | L4A | L4C | diaS13| H0A13 | H0A29 | H0C13 | H0C29 | 330 _|_H_1_A_1_3___|_H_1_A_2_9___|_H_1_C_1_3___|_H_1_C_2_9___|_H_2_A_1_3___|_H_2_A_2_9___|_H_2_C_1_3___|_H_2_C_2_9___| 340 | L5F | L5A | L5C | diaS14| H0A14 | H0A30 | H0C14 | H0C30 | 350 | H1A14 | H1A30 | H1C14 | H1C30 | H2A14 | H2A30 | H2C14 | H2C30 | 360 | tmrF | itr | etr | diaS15| H0A15 | H0A31 | H0C15 | H0C31 | 370 _|_H_1_A_1_5___|_H_1_A_3_1___|_H_1_C_1_5___|_H_1_C_3_1___|_H_2_A_1_5___|_H_2_A_3_1___|_H_2_C_1_5___|_H_2_C_3_1___| .spb 2 .inl 0 Legend: .spb .inl 5 .fif A_c_c active data interrupt, subchannel _c_c C_c_c configuration data interrupt, subchannel _c_c cdr card reader cns FNP console dia direct interface adapter etr elapsed time rollover interrupt F fault interrupt H_n high-speed line adapter _n itr interval timer runout interrupt L_n low-speed line adapter _n prt printer S special interrupt S_x_x special interrupt from DIA mailbox _x_x T terminate interrupt tmr timer channel .fin .inl 0 .brf .ifi l2h "Interrupt Cells" .ifi tab "FNP Interrupt Cells" .spb 2 .fif .inl 9 abs | bit position _l_e_v_e_l__a_d_d_r__|_0___1___2___3___4___5___6___7___8___9__1_0__1_1__1_2__1_3__1_4__1_5__1_6__1_7__ 0 400 | IOM channel fault interrupts | | 1 401 | IOM channel special interrupts | | 2 402 | IOM channel terminate interrupts | | 3 403 | DIA special interrupts | n | 4 404 | HSLA#0 subchannels 0-15, active | o | 5 405 | HSLA#0 subchannels 16-31, active | t | 6 406 | HSLA#0 subchannels 0-15, configuration | | 7 407 | HSLA#0 subchannels 16-31, configuration | | 10 410 | HSLA#1 subchannels 0-15, active | | 11 411 | HSLA#1 subchannels 16-31, active | u | 12 412 | HSLA#1 subchannels 0-15, configuration | s | 13 413 | HSLA#1 subchannels 16-31, configuration | e | 14 414 | HSLA#2 subchannels 0-15, active | d | 15 415 | HSLA#2 subchannels 16-31, active | | 16 416 | HSLA#2 subchannels 0-15, configuration | | _1_7_____4_1_7___|_H_S_L_A_#_2___s_u_b_c_h_a_n_n_e_l_s_1_6_-_3_1_,___c_o_n_f_i_g_u_r_a_t_i_o_n________|______| .inl 0 .ifi l1h "Fault Vectors" .fin .alb .fin The processor fault vector base in the FNP is 440(8), and there are eight hardware faults defined. .spb 2 .fif .inl 15 .unl 2 Address Fault 440 power off. 441 power on. 442 memory parity. 443 invalid operation code. 444 overflow. 445 invalid memory operation. 446 divide check. 447 invalid program interrupt. .spb 2 .fin .alb .inl 0 In addition to these eight hardware faults, there are two simulated faults that are set by the software for the condition specified. There are no "fault vector" locations associated with the simulated faults. .fif .inl 10 .spb 2 1. unexpected interrupt. 2. console abort command. .brp .inl 0 .ifi l2h "FNP Store Map" .inl 19 .fif __________________________________________ .unl 2 0 | | | I/O Interrupt Vectors | |________________________________________| .unl 4 400 | | | I/O Interrupt Cells | |________________________________________| .unl 4 420 | | | IOM Fault Status Words | |________________________________________| .unl 4 440 | | | Processor Fault Vectors | |________________________________________| .unl 4 450 | | | I/O Communications Region | |________________________________________| .unl 4 500 | | | LSLA#0 Control Word Area | _|_________________________________________| .unl 4 520 | | | LSLA#1 Control Word Area | _|_________________________________________| .unl 4 540 | | | LSLA#2 Control Word Area | _|_________________________________________| .unl 4 560 | | | LSLA#3 Control Word Area | _|_________________________________________| .unl 4 600 | | | LSLA#4 Control Word Area | _|_________________________________________| .unl 4 620 | | | LSLA#5 Control Word Area | _|_________________________________________| .unl 4 640 | | | unassigned | _|_________________________________________| .unl 5 1000 | | | HSLA#0 Control Word Area | |________________________________________| .unl 5 2000 | | | HSLA#1 Control Word Area | |________________________________________| .unl 5 3000 | | | HSLA#2 Control Word Area | |________________________________________| .unl 5 4000 | | | Program Modules and Data Buffers | | | .brf . .brf . .brf . .brf . .inl 0 .ifi fig "FNP Store Map" .inl 0 .fin .brp ----------------------------------------------------------- Historical Background This edition of the Multics software materials and documentation is provided and donated to Massachusetts Institute of Technology by Group BULL including BULL HN Information Systems Inc. as a contribution to computer science knowledge. This donation is made also to give evidence of the common contributions of Massachusetts Institute of Technology, Bell Laboratories, General Electric, Honeywell Information Systems Inc., Honeywell BULL Inc., Groupe BULL and BULL HN Information Systems Inc. to the development of this operating system. Multics development was initiated by Massachusetts Institute of Technology Project MAC (1963-1970), renamed the MIT Laboratory for Computer Science and Artificial Intelligence in the mid 1970s, under the leadership of Professor Fernando Jose Corbato. Users consider that Multics provided the best software architecture for managing computer hardware properly and for executing programs. Many subsequent operating systems incorporated Multics principles. Multics was distributed in 1975 to 2000 by Group Bull in Europe , and in the U.S. by Bull HN Information Systems Inc., as successor in interest by change in name only to Honeywell Bull Inc. and Honeywell Information Systems Inc. . ----------------------------------------------------------- Permission to use, copy, modify, and distribute these programs and their documentation for any purpose and without fee is hereby granted,provided that the below copyright notice and historical background appear in all copies and that both the copyright notice and historical background and this permission notice appear in supporting documentation, and that the names of MIT, HIS, BULL or BULL HN not be used in advertising or publicity pertaining to distribution of the programs without specific prior written permission. Copyright 1972 by Massachusetts Institute of Technology and Honeywell Information Systems Inc. Copyright 2006 by BULL HN Information Systems Inc. Copyright 2006 by Bull SAS All Rights Reserved