s1.rec.compin 10/22/84 1116.2r w 10/22/84 1115.5 12699 ..init_photo "AN71-01" .srv section 1 .ifi l0h "Introduction" This document describes the implementation and design of the Multics dynamic reconfiguration software for the major hardware modules of the system. This document is limited to processor, system controller and bulk store memory reconfiguration although there are many more hardware and software switchable modules in the system. .spb 2 Dynamic reconfiguring, on a per-module basis, is done only in response to explicit operator request. The facility of the system that automatically deconfigures selected subregions of main memory or bulk store when hardware problems arise uses the same basic mechanism as module deconfiguration where appropriate. There is currently no way the system will automatically deconfigure a faulty processor. The software to automatically deconfigure main memory is incomplete. The software to automatically deconfigure a faulty record of the bulk store is operational. .spb 2 Two types of system controller can be used for Multics operation: the 6000 system controller (MC6000) and the four mqegaword system controller unit (SCU003). These system controllers can be intermixed in any way in a Multics configuration. They are hereafter referred to as the 6000 SC and the 4MW SCU, respectively. Basic differences between the 6000 SC and the 4MW SCU are described in the next section. .brp .fin .inl 0  s2.rec.compin 10/22/84 1116.2r w 10/22/84 1115.5 130068 ..init_photo "AN71-01" .srv section 2 .ifi l0h "Terminology" Terms and phrases frequently used in discussions of dynamic reconfiguration are defined on the following pages in logical order. They are listed below in alphabetical order for convenience. .spb .fif .inl 5 BOS processor 2-4 abs_usable 2-6 abs_wired 2-7 active module port 2-2 bootload controller 2-4 bootload processor 2-4 controller 2-2 core map 2-6 external interlace 2-5 internal interlace 2-5 interrupt cell 2-3 interrupt mask 2-3 interrupt mechanism 2-3 interrupt processor 2-4 interrupt register 2-3 main memory frame 2-6 main memory map 2-6 main memory used list 2-6 memory 2-2 memory controller 2-2 page 2-6 paging device map 2-7 pdmap 2-7 port enable register 2-2 processor 2-2 processor tag 2-5 read/write sequence 2-7 record 2-6 rws 2-7 system controller 2-2 system controller port 2-2 system interrupt 2-4 used list 2-6 .fin .spb .inl 10 .unl 5 system controller .ifi l1toc "system controller" .brf A passive hardware module that interfaces active modules to the main memory of the configuration. The system controller manages system interrupts, passes connect signals from one active module to another, contains the system calendar clock, and provides main memory functions to its active users. A system controller may be either an 6000 SC or a 4MW SCU. .spb .unl 5 .ifi l1toc "memory controller" memory controller .brf See system controller above. .spb .unl 5 .ifi l1toc "memory" memory .brf See system controller above. .spb .unl 5 .ifi l1toc "controller" controller .brf See system controller above. .spb .unl 5 .ifi l1toc "processor" processor .brf One of the three types of active modules. (The other two are the IOM and bulk store controller.) The processor is the major processing unit (CPU). .spb .unl 5 .ifi l1toc "system controller port" system controller port .brf A point on a system controller for connection to an active module. There are eight ports on a system controller. Each system controller contains hardware to enable or disable requests over each of its ports. Only active modules connected to enabled system controller ports can interact with that system controller. .spb .unl 5 .ifi l1toc "active module port" active module port .brf A point on an active module for connection to a system controller. Each active module has eight ports controlled by port logic. The port logic maps an absolute address generated by an active module into a port number and an address within the memory associated with a system controller. .spb .unl 5 .ifi l1toc "port enable register" port enable register .brf An eight-bit mask register associated with each system controller that contains one bit for each controller port. If a bit is on, the active module on the corresponding controller port can use the system controller. If it is off, the active module will receive a fault condition if it attempts to access the system controller. .spb On a 6000 SC, port enable register bits can be forced on or off by eight configuration panel switches. These switches have three positions: ENABLE, DISABLE, and PROG CONTROL. If a switch is in PROG CONTROL position, the corresponding port enable register bit can be turned on or off by system software. For normal Multics operation, all eight switches are usually set to the PROG CONTROL position. .spb The 4MW SCU configuration panel contains eight two-position switches. These switches are read into the port enable register only when the system controller is initialized. At all other times, port enable register bits must be set by system software. .spb .unl 5 .ifi l1toc "interrupt register" interrupt register .brf A 32-bit register associated with each system controller. Active modules can instruct the system controller to set any of these bits. When one or more bits in the interrupt register are set, the system controller will attempt to notify one or more active modules that an execute interrupt is present (XIP). This is described in more detail below. .spb .unl 5 .ifi l1toc "interrupt cell" interrupt cell .brf A single bit of the interrupt register. Interrupt cells are numbered from 0 to 31. .spb .unl 5 .ifi l1toc "interrupt mask" interrupt mask .brf Interrupt masks are used to allow or prevent the receipt of XIP signals by processors. (See interrupt mechanism.) .spb Each 6000 SC contains four 32-bit interrupt mask registers. Each 4MW SCU contains only two. Each interrupt mask register is assigned to a particular controller port through the use of the execute interrupt mask assignment (EIMA) switches. On the 4MW SCU, the EIMA switches are read into internal mask assignment registers when the system controller is initialized. Interrupt mask register assignments can be changed by system software. On the 6000 SC, no software changes can be made to the mask assignments. .spb A processor can read or set an interrupt mask register assigned to its system controller port through the use of the RMCM and SMCM instructions. Processors can also read and set interrupt mask registers assigned to other ports through the use of the RSCR and SSCR instructions. On the 6000 SC, a processor may change other interrupt mask registers only if it has a mask register assigned to its own controller port. .spb .unl 5 .ifi l1toc "interrupt mechanism" interrupt mechanism .brf When one or more bits are set in a system controller's interrupt register, the controller examines all interrupt mask registers for matching bits. (When a bit is on in an interrupt mask register, the active module to which the mask is assigned is said to have the corresponding interrupt "unmasked".) The system controller will send an XIP signal to all active modules with unmasked interrupts set in the interrupt register. .spb Active modules respond to the XIP signal by interrogating the system controller about the interrupt. The system controller will find the highest priority (lowest cell number) unmasked interrupt set and return the interrupt cell number to the requesting active module. The system controller will clear the interrupt cell at that time. If more than one active module responds to an XIP signal, only one will receive information pertaining to a particular interrupt cell. If a set interrupt is not unmasked by any active module, the interrupt will be retained until some active module unmasks that interrupt. .spb .unl 5 .ifi l1toc "bootload controller" bootload controller .brf The system controller containing low-order main memory in a system configuration. All interrupts sent by active modules are sent via the interrupt register in the bootload controller. No other system controllers convey interrupts to active modules. The bootload system controller cannot be removed while the system is running since it contains fault and interrupt vectors, IOM, bulk store, and DataNet 6600 FNP mailboxes, and unpaged segments. .spb .unl 5 .ifi l1toc "system interrupt" system interrupt .brf An interrupt required by the system in order to carry out its orderly functions of communicating between I/O devices and Multics processes. (In addition, there is one interrupt which is sent by a processor to start up a new processor.) All I/O interrupts are set in the bootload system controller. I/O interrupts will be sent to processors selected by the EIMA switches on the bootload system controller. .spb .unl 5 .ifi l1toc "bootload processor" .ifi l1toc "BOS processor" bootload processor (or BOS processor) .brf The central processor used to initialize Multics and to shutdown and return to BOS at the end of Multics operation. It is also the processor used to enter BOS after a system crash. The bootload processor may be dynamically deconfigured, at which time another processor will be made the new bootload processor. .spb .unl 5 .ifi l1toc "interrupt processor" interrupt processor .brf Processors that can receive interrupts (i.e. that have assigned interrupt masks in the bootload system controller). When a 6000 SC is used as the bootload controller, four interrupt masks are available; hence, all four processors in such a Multics configuration are interrupt processors. When a 4MW SCU is the bootload controller, only two processors can receive interrupts. System software will reassign the interrupt mask register of an interrupt processor which is being dynamically removed to a processor which is not an interrupt processor. .spb .unl 5 .ifi l1toc "processor tag" processor tag .brf A processor identification corresponding directly to the processor number. Processors have two switches on their configuration panels which allow the setting of a two-bit processor number. This number can be read by the RSW instruction. Each processor in a Multics configuration must have a different processor number. The processor number corresponds to the processor tag on the configuration card for that processor. .spb .fif .inl 10 Processor Processor Number Tag .spb 00 A 01 B 10 C 11 D .spb .fin .inl 5 A maximum of four processors can be configured to a Multics system. .spb .unl 5 .ifi l1toc "internal interlace" internal interlace .brf A system controller feature which allows interleaving of double-words between the low-order and high-order store units connected to the controller. Except for timing changes, internal interlace is invisible to all active modules. Only system controllers with low-order and high-order store units of the same size can be internally interlaced. .spb .unl 5 .ifi l1toc "external interlace" external interlace .brf The port logic of each active module allows the main memory of two system controllers on even/odd active module port pairs to be interlaced. Interlacing may be done at either two words at a time or four words at a time. Only system controllers containing stores of the same size can be externally interlaced. Four word external interlace may be combined with internal interlace to provide a four-way interlace mechanism. Of necessity, all active modules must have their interlace switches set in the same positions. .spb .unl 5 .ifi l1toc "main memory frame" main memory frame .brf A contiguous region of main memory that is one page in length and starts on a page boundary. All of main memory is thus divided into fixed length regions the size of a page. Some main memory frames contain pages which are permanently wired. These frames can never contain paged data. Other main memory frames contain data or code which is "temp wired" (i.e., is temporarily forced to remain in main memory). A temp wired main memory frame may later be freed up and reused for some other page. The term "wired" applies to anything which must remain in main memory for some time for some reason. The terms "latched", "locked" and "core resident" are also used in the literature for what is here called wired. .spb .unl 5 .ifi l1toc "main memory map" .ifi l1toc "core map" main memory map (or core map) .brf An array of entries for all main memory frames that can ever be configured into the system. The main memory map is indexed by absolute main memory frame numbers. A main memory map entry (often called a core map entry or CME) describes which page, if any, is currently occupying the associated main memory frame. .spb .unl 5 .ifi l1toc "main memory used list" .ifi l1toc "used list" main memory used list (or used list) .brf A threaded list of main memory map entries for the main memory frames in the paging pool. .spb .unl 5 .ifi l1toc "page" page .brf A 1024-word extent of data beginning at a 1024-word boundary of a segment. Pages belong to segments; they can reside in main memory frames, secondary storage records, or both. .spb .unl 5 .ifi l1toc "record " record .brf A contiguous region of a secondary storage device that begins on a page boundary and is one page long. Satisfying a page fault, for example, consists in moving the data of a page from a given record of secondary storage to a given frame of main memory and performing the necessary connections. .spb .unl 5 .ifi l1toc "abs_usable" abs_usable .brf That attribute of a main memory frame which permits the main memory to be used for I/O. This concept is needed by several hardcore I/O procedures since they must set up DCW lists which have absolute addresses in them. The main memory frames of the bootload controller can not be dynamically deconfigured (for several unrelated reasons), and therefore, all main memory frames of the bootload controller which are part of the paging pool are marked as abs_usable. In addition, main memory frames of other system controllers will also be so marked if there are not enough abs_usable frames in the bootload controller. .spb .unl 5 .ifi l1toc "abs_wired" abs_wired .brf A frame of main memory that contains a page that is wired down because it may contain locations that are absolutely addressed. Such a page cannot be moved, either to make room for another abs_wired page or to deconfigure the controller. Any controller that contains one abs_wired page can not be dynamically deconfigured until that page is no longer required to be abs_wired. .spb .unl 5 .ifi l1toc "paging device map" .ifi l1toc "pdmap" paging device map (or pdmap) .brf A map, analogous to the main memory map, used as part of the bulk store management algorithms. The paging device map is ordered according to time of recent reference and hence is the key to the bulk store replacement algorithm. .spb .unl 5 .ifi l1toc "read/write sequence" .ifi l1toc "rws" read/write sequence (or rws) .brf The mechanism used to move a modified page from the bulk store to secondary storage. This mechanism consists of finding a frame of main memory, reading in the page from the bulk store, and then writing the page out to secondary storage. .brp .fin .inl 0  s3.rec.compin 10/22/84 1116.2r w 10/22/84 1115.5 153630 ..init_photo "AN71-01" .srv section 3 .ifi l0h "Data Structures" The several key data structures used by the reconfiguration software are kept in the segments SCS and SST. These are initialized as described in Section IV and modified as described in Sections VI, VII and VIII. .ifi l1h "Processor and System Controller Reconfiguration Structures" The following declarations of data structures describe structures that are used both during processor and system controller reconfiguration: .spb .fif .inl 5 declare 1 scs$controller_data (0: 7) aligned ext, 2 size fixed bin(17) unaligned, 2 base fixed bin(17) unaligned, 2 eima_data (4) unaligned, 3 mask_available bit(1) unaligned, 3 mask_assigned bit(1) unaligned, 3 mbz bit(3) unaligned, 3 mask_assignment fixed bin(3) unaligned, 2 info aligned, 3 online bit(1) unaligned, 3 offline bit(1) unaligned, 3 store_a_online bit(1) unaligned, 3 store_a1_online bit(1) unaligned, 3 store_b_online bit(1) unaligned, 3 store_b1_online bit(1) unaligned, 3 store_b_is_lower bit(1) unaligned, 3 ext_interlaced bit(1) unaligned, 3 int_interlaced bit(1) unaligned, 3 four_word bit(1) unaligned, 3 cyclic_priority (7) bit(1) unaligned, 3 type bit(4) unaligned, 3 abs_wired bit(1) unaligned, 3 program bit(1) unaligned, 3 pad bit(13) unaligned, 2 lower_store_size fixed bin(17) uanligned, 2 upper_store_size fixed bin(17) unaligned; declare scs$reconfig_lock bit(36) aligned ext; declare scs$reconfig_locker_id char(32) aligned ext; declare scs$interrupt_controller fixed bin(3) ext; declare scs$port_addressing_word (0: 7) bit(3) aligned ext; .spb 2 .fin .inl 0 The variables declared above have the following meanings: .spb .inl 5 .unh 1. controller_data .brf .inl 10 is an array, indexed by system controller tag, containing information for each system controller. .spb .inl 5 .unh 5 2. controller_data.size .brf .inl 10 is the size, in 1024-word frames, of the main memory contained in each system controller. .spb .inl 5 .unh 5 3. controller_data.base .brf .inl 10 is the base address, modulo 1024 words, of the main memory contained in each system controller. .spb .inl 5 .unh 5 4. controller_data.eima_data .brf .inl 10 is an array containing the execute interrupt mask assignment (EIMA) switch settings for each system controller. .spb .inl 5 .unh 5 5. eima_data.mask_available .brf .inl 10 is set to "1"b if the corresponding interrupt mask is available on a system controller. .spb .inl 5 .unh 5 6. eima_data.mask_assigned .brf .inl 10 is set to "1"b if the corresponding interrupt mask is assigned to a processor port. .spb .inl 5 .unh 5 7. eima_data.mask_assignment .brf .inl 10 is the system controller port to which the interrupt mask is assigned. .spb .inl 5 .unh 5 8. controller_data.online .brf .inl 10 if equal to "1"b, indicates that the corresponding system controller is online and in use. .spb .inl 5 .unh 5 9. controller_data.offline .brf .inl 10 if equal to "1"b, indicates that the corresponding system controller is offline, but could be dynamically added at a later time. .spb .inl 5 .unh 5 10. controller_data.store_a_online .brf .inl 10 is equal to "1"b if store "A" of the corresponding system controller is online and in use. .spb .inl 5 .unh 5 11. controller_data.store_a1_online .brf .inl 10 is equal to "1"b if store "A1" of the corresponding system controller is online and in use. .spb .inl 5 .unh 5 12. controller_data.store_b_online .brf .inl 10 is equal to "1"b if store "B" of the corresponding system controller is online and in use. .spb .inl 5 .unh 5 13. controller_data.store_b1_online .brf .inl 10 is equal to "1"b if store "B1" of the corresponding system controller is online and in use. .spb .inl 5 .unh 5 14. controller_data.store_b_is_lower .brf .inl 10 is equal to "1"b if store "B" (and store "B1", if present) is the lower order store for a given system controller. .spb .inl 5 .unh 5 15. controller_data.ext_interlaced .brf .inl 10 is set to "1"b if the corresponding system controller is interlaced with a system controller on an adjacent active module port. .spb .inl 5 .unh 5 16. controller_data.int_interlaced .brf .inl 10 is set to "1"b if the two stores of the corresponding system controller are internally interlaced. .spb .inl 5 .unh 5 17. controller_data.four_word .brf .inl 10 is set to "1"b if two adjacent system controllers are interlaced every four words. It is set to "0"b if they are interlaced every two words. If controller_data.ext_interlaced is equal to "0"b, this bit is meaningless. .spb .inl 5 .unh 5 18. controller_data.cyclic_priority .brf .inl 10 is an array of bits giving the cyclic port priority ("anti-hogging") switch settings for each system controller. .spb .inl 5 .unh 5 19. controller_data.type .brf .inl 10 is a code giving the type of system controller. If it is greater than or equal to "0010"b, the controller is a 4MW SCU. Otherwise, it is a 6000 SC. .spb .inl 5 .unh 5 20. controller_data.abs_wired .brf .inl 10 is set to "1"b if abs wired pages are contained in the main memory associated with the corresponding system controller. .spb .inl 5 .unh 5 21. controller_data.program .brf .inl 10 is "1"b if the controller is a 4MW SCU and is in programmable mode. Multics requires this bit to be on. .spb .inl 5 .unh 5 22. controller_data.lower_store_size .brf .inl 10 is the size, in 1024-word frames, of the lower of the two stores connected to the corresponding system controller. .spb .inl 5 .unh 5 23. controller_data.upper_store_size .brf .inl 10 is the size, in 1024-word frames, of the upper of the two stores connected to the corresponding system controller. .spb .inl 5 .unh 5 24. reconfig_lock .brf .inl 10 is the lock used to prevent simultaneous attempts by several processes to perform dynamic reconfiguration. .spb .inl 5 .unh 5 25. reconfig_locker_id .brf .inl 10 is the process group ID of the process which has set the reconfig_lock. .spb .inl 5 .unh 5 26. interrupt_controller .brf .inl 10 is the tag of the bootload system controller. All interrupts go through this system controller. .spb .inl 5 .unh 5 27. port_addressing_word .brf .inl 10 is an indirect word needed to access a given processor port (and thus a given system controller) by certain processor instructions such as RMCM, SMCM, and RCCL. .inl 0 .ifi l1h "Processor Reconfiguration Structures" The following declarations of data structures describe structures that are primarily used during processor reconfiguration: .spb .fif .inl 5 declare 1 scs$processor_data (0: 3) ext aligned, 2 online bit(1) unaligned, 2 offline bit(1) unaligned, 2 pad1 bit(2) unaligned, 2 delete_cpu bit(1) unaligned, 2 interrupt_cpu bit(1) unaligned, 2 halted_cpu bit(1) unaligned, 2 pad2 bit(27) unaligned, 2 controller_port fixed bin(3) unaligned; declare scs$processor_start_int_no fixed bin(5) ext; declare scs$processor_start_pattern bit(36) aligned; declare scs$processor_start_mask bit(72) aligned ext; declare scs$set_mask (0: 3) bit(36) aligned ext; declare scs$read_mask (0: 3) bit(36) aligned ext; declare scs$mask_ptr (0: 3) ptr unaligned ext; declare scs$nprocessors fixed bin ext; declare scs$bos_processor_tag fixed bin(2) ext; declare scs$processor bit(4) aligned ext; declare scs$processor_switch_template (4) bit(36) aligned ext; declare scs$processor_switch_compare (4) bit(36) aligned ext; declare scs$processor_switch_mask (4) bit(36) aligned ext; .spb 2 .inl 0 .fin The variables declared above have the following meanings: .spb .inl 5 .unh 5 1. proc essor_data .brf .inl 10 is an array, indexed by processor tag, of information for each possible processor that can be configured in a Multics system. .spb .inl 5 .unh 5 2. processor_data.online .brf .inl 10 if equal to "1"b, indicates that the corresponding processor is online and running. .spb .inl 5 .unh 5 3. processor_data.offline .brf .inl 10 if equal to "1"b, indicates that the corresponding processor is offline, but could be dynamically added at a later time. .spb .inl 5 .unh 5 4. processor_data.delete_cpu .brf .inl 10 is set to "1"b by the processor reconfiguration software when it is desired to dynamically remove the corresponding processor. .spb .inl 5 .unh 5 5. processor_data.interrupt_cpu .brf .inl 10 is set to "1"b if the corresponding processor has an interrupt mask assigned to it in the bootload system controller. .spb .inl 5 .unh 5 6. processor_data.halted_cpu .brf .inl 10 is set to "1"b after the corresponding processor has been successfully dynamically removed. This bit is also set to "1"b for all processors at the beginning of Multics system initialization. .spb .inl 5 .unh 5 7. processor_data.controller_port .brf .inl 10 is the system controller port to which the corresponding processor is connected. Note that the port number occupies bits 33 through 35 of the word containing processor_data. This enables the entire word to be used as a Connect Operand Word (COW) when sending connects to a particular processor. .spb .inl 5 .unh 5 8. processor_start_int_no .brf .inl 10 is the interrupt cell number used to start up a processor that is being dynamically added. This interrupt cell number is assigned by the system initialization software. .spb .inl 5 .unh 5 9. processor_start_pattern .brf .inl 10 is the bit pattern used to set the processor start interrupt with a SMIC instruction. .spb .inl 5 .unh 5 10. processor_start_mask .brf .inl 10 is the system controller interrupt mask used to allow a processor to take the processor start interrupt but to mask all other interrupts. .spb .inl 5 .unh 5 11. set_mask .brf .inl 10 is an array of instructions used to set interrupt masks for corresponding processors. If a processor has an assigned mask, the corresponding element of set_mask will contain an SMCM instruction. Otherwise, it will contain an STAQ instruction into a software simulated mask register. .spb .inl 5 .unh 5 12. read_mask .brf .inl 10 is an array of instructions used to read interrupt masks for corresponding processors. If a processor has an assigned mask, the corresponding element of read_mask will contain an RMCM instruction. Otherwise, it will contain an LDAQ instruction from a software simulated mask register. .spb .inl 5 .unh 5 13. mask_ptr .brf .inl 10 is an array of packed pointers used to set and read interrupt masks for corresponding processors. If a processor has an assigned mask, the corresponding element of mask_ptr will point to scs$port_addressing_word for the bootload system controller. Otherwise, it will point to the simulated mask register located at prds$simulated_mask. .spb .inl 5 .unh 5 14. nprocessors .brf .inl 10 is the number of processors currently online and running. .spb .inl 5 .unh 5 15. bos_processor_tag .brf .inl 10 is the processor tag of the processor that was the bootload processor when Multics was bootloaded. If the original bootload processor has been dynamically removed, bos_processor_tag will be set to the tag of a processor which will be used to return to BOS when Multics is shut down. .spb .inl 5 .unh 5 16. processor .brf .inl 10 contains one bit for each processor. The bit corresponding to a processor will be equal to "1"b if that processor is online and running. .spb .inl 5 .unh 5 17. processor_switch_template .brf .inl 10 is an array containing template values for the processor switches read by the RSW 1 through RSW 4 instructions. This array is used to verify the configuration switch settings of a processor when attempting to dynamically add that processor. .spb .inl 5 .unh 5 18. processor_switch_compare .brf .inl 10 is an array containing discrepancies between the expected and actual data read by the RSW 1 through RSW 4 instructions. .spb .inl 5 .unh 5 19. processor_switch_mask .brf .inl 10 is an array containing masks for the processor switches read by the RSW 1 through RSW 4 instructions. The processor_switch_compare data is produced by exclusive ORing the processor_switch_template data with the actual configuration switch settings and ANDing the result with the processor_switch_mask data. .spb 2 .inl 0 In addition to the structures described above, there are several structures contained in the procedure "init_processor" which are set, examined, or used during processor reconfiguration. Note that init_processor is an impure procedure. .spb .fif .inl 5 declare init_processor$wait_flag fixed bin(35) ext; declare init_processor$new_dbr bit(72) aligned ext; declare init_processor$first_tra bit(36) aligned ext; declare init_processor$trouble_tra bit(36) aligned ext; declare init_processor$startup_tra bit(36) aligned ext; declare init_processor$lockup_tra bit(36) aligned ext; declare init_processor$onc_tra bit(36) aligned ext; declare init_processor$controller_data (0:7) bit(1) unaligned ext; .spb 2 .inl 0 .fin The variables declared above are used in the following ways: .spb .inl 5 .unh 5 1. wait_flag .brf .inl 10 is a cell that is used to contain an error code if trouble is experienced in starting up a new processor. If the processor is started successfully, wait_flag will contain zero. .spb .inl 5 .unh 5 2. new_dbr .brf .inl 10 is the descriptor segment base register value for a new processor. It is filled in by reconfiguration software before starting up a new processor. It is loaded by a new processor just before that processor enters appending mode. .spb .inl 5 .unh 5 3. first_tra .brf .inl 10 is an inhibited TRA instruction to be placed in the interrupt vector entry for the processor start interrupt. This instruction is executed when a new processor takes a processor start interrupt. .spb .inl 5 .unh 5 4. trouble_tra .brf .inl 10 is an inhibited TRA instruction to be placed in the fault vector for the trouble fault. This instruction is executed if a new processor takes an unexpected trouble fault. .spb .inl 5 .unh 5 5. startup_tra .brf .inl 10 is an inhibited TRA instruction to be placed in the fault vector for the startup fault. This instruction is executed if a new processor takes an unexpected startup fault. .spb .inl 5 .unh 5 6. lockup_tra .brf .inl 10 is an inhibited TRA instruction to be placed in the fault vector for the lockup fault. This instruction is executed if a new processor takes an unexpected lockup fault. .spb .inl 5 .unh 5 7. onc_tra .brf .inl 10 is an inhibited TRA instruction to be placed in the fault vector for the op-not-complete fault. This instruction is executed if a new processor takes an unexpected op-not-complete fault. .spb .inl 5 .unh 5 8. controller_data .brf .inl 10 is an array of bits, one for each active module port. If a system controller is currently configured and in use, the bit corresponding to its active module port is turned on. Otherwise, it is turned off. This array is used by a new processor to test for the presence of each configured system controller. .inl 0 .ifi l1h "System Controller Addressing Segment" The system controller addressing segment (SCAS) is a specialized data base that is used to read and set certain registers in system controllers and their associated store units. The SCAS is essentially a segment composed of a page in each store unit of each configured system controller. It may be up to 32 pages in length. The actual content of the pages is not of importance and in general changes as pages are moved in and out of the particular regions contained in the SCAS. .spb 2 The SCAS is used to generate the correct final (absolute) address needed by the RSCR and SSCR instructions. (These instructions operate on the system controller or store unit that contains the final absolute address generated by the address preparation logic of the processor.) .spb 2 Page 0 of the SCAS is located in the first main memory frame of the lower store unit connected to the system controller on port 0 of active modules; page 1 is located in the system controller on port 1; and so forth. Pages 8 through 15 are located in the first memory frame of the upper store units connected to the system controllers on ports 0 through 7. Pages 16 through 24 of the SCAS are used to reference auxiliary lower store units, if configured; pages 25 through 31 are used to reference auxiliary upper store units. Note that there may be "holes" in the SCAS due to certain system controllers or store units not being configured. .ifi l1h "Main Memory and Paging Device Maps" The main memory map consists of entries threaded into a circular list. Entries that correspond to unused frames of main memory are not threaded into the list. The paging device map is analogous to the main memory map. Both are described in detail in S__t_o_r_a_g_e_S__y_s_t_e_m, Order No. AN61. .brp .fin .inl 0  s4.rec.compin 10/22/84 1116.2r w 10/22/84 1115.5 46215 ..init_photo "AN71-01" .srv section 4 .ifi l0h "Data Base Initialization" This section describes the initialization of the data bases used by the reconfiguration software. Some of these data bases will not be changed after the bootload, others will be changed all the time, and still others will be changed only when reconfiguration is explicitly requested. (S__y_s_t_e_m I__n_i_t_i_a_l_i_z_a_t_i_o_n, Order No. AN70, should be consulted for a much more thorough discussion of system initialization than can be provided here.) .ifi l1h "SCS Initialization" The system communication segment (SCS) described in Section!III is initialized primarily by the programs scs_init, scs_and_clock_init, init_scu, scr_util, and scas_init. .spb 2 The contents of scs$bos_processor_tag and scs$interrupt_controller are set at the very beginning of system initialization. At this time, the clock reading mechanism is initialized. This mechanism consists of a pointer at sys_info$clock_ pointing to scs$port_addressing_word (scs$interrupt_controller). The high-order three bits of this word contain the port number of the bootload system controller. Clock initialization must be performed early in initialization since the clock reading facility is needed by the Multics error message facility. .spb 2 Elements of scs$controller_data are filled in in stages as various programs learn more about the configuration. The processor switches are read to determine the base and size of each system controller. An RSCR-CFG instruction is then issued to the controller. This CFG data is read into the appropriate element of scs$cfg_data and is interpreted and placed in the appropriate members of the scs$controller_data structure. .spb 2 The scs$processor_data structure is initialized to mark all processors (including the BOS processor) as offline and halted. The controller port number is filled in from the configuration deck. The interrupt_cpu bit is set on if an interrupt mask on the bootload system controller has been assigned to that processor. .spb 2 As scs$processor_data is initialized, the interrupt mask pointers and masking instructions for each processor at scs$mask_ptr, scs$set_mask, and scs$read_mask are filled in. At this time, system controller interrupt mask assignments are checked to make sure that they are correct. .spb 2 As the interrupt handling mechanism is initialized, an unused interrupt cell is selected by the system initialization software and assigned as the interrupt to be used for starting a new processor. This interrupt cell number is saved in scs$processor_start_int_no. A SMIC pattern to generate this interrupt is placed in scs$processor_start_pattern, and an interrupt mask setting to allow the interrupt is saved in scs$processor_start_mask. .ifi l1h "SCAS Initialization" The program "init_scu" is called during initialization and during system controller reconfiguration. It is responsible for filling in the SCAS page table for a system controller. Based on the processor switch settings, init_scu determines the base address of the memory in a controller and sets a page of SCAS to point to that address. init_scu then calls out to read configuration information pertaining to the number and size of the store units connected to the system controller. This data is used by init_scu to set up to three additional pages at the base of each additional store unit. These pages are needed to issue RSCR instructions directed to a particular store unit rather than to the system controller. This function is used primarily by error analysis and logging programs. .ifi l1h "SST Initialization" Before the paging mechanism can be enabled, the main memory map in the SST must be initialized. Since the main memory map cannot be grown, it is required that any system controllers that will ever be configured to the system for a given bootload be specified in the configuration deck and correctly assigned in the configuration switches of the bootload processor. Main memory frames in online system controllers are threaded into the used list. Main memory frames for system controllers not yet placed online are threaded into no list. When a system controller and its main memory are dynamically added, the main memory frames for that controller can then be threaded into the main memory used list. The abs_usable bits for each main memory frame in the bootload system controller are turned on in the main memory map. This action will prevent the removal of any main memory frames contained in the bootload system controller. .spb 2 The bulk store (paging device) map is also contained in the SST. It is initialized as described on the "page" configuration card. .ifi l1h "Other Data Base Initialization" The initialization of the PRDS, done mainly by prds_init, tc_data, tc_init and start_cpu, is straightforward and simple. The primary interaction between the traffic controller and reconfiguration consists in the creation, running and deletion of the _i_d_l_e__p_r_o_c_e_s_s_e_s. .brp .fin .inl 0  s5.rec.compin 10/22/84 1116.2r w 10/22/84 1115.9 70902 ..init_photo "AN71-01" .srv section 5 .ifi l0h "Hardcore Reconfiguration Entries" Processor, system controller, and main memory reconfiguration is split into two main parts: a user ring command interface and hardcore ring procedures. The user ring command interface, contained in the procedure reconfigure, is responsible for validating reconfiguration command arguments, passing them to the hardcore ring procedures, and analyzing returned error information. .spb 2 The hardcore portion of processor, system controller, and main memory reconfiguration is located in the procedure reconfig and the many procedures called by it. reconfig is called through the highly privileged hardcore gate "hphcs_". .ifi l1h "Reconfiguration Entries" .ifi l2toc "hphcs_$add_cpu" Name: hphcs_$add_cpu .spb 2 This entry is called to add a processor to the system. .spb Usage .all .spb .inl 10 .unl 5 declare hphcs_$add_cpu entry (fixed bin(3), (4) bit(36) aligned, fixed bin(35)); .spb .unl 5 call hphcs_$add_cpu (tag, switches, code); .spb .alb .inl 5 .unh 5 1. tag .brf is the processor tag or processor number of the processor to be added. (Input) .spb .unh 5 2. switches .brf are the processor switches which are in error if an attempt was made to add an improperly configured processor. (Output) .spb .unh 5 3. code .brf is a reconfiguration error code. The following values are possible: .inl +5 .spb .unh 5 1 = no response from processor. .unh 5 2 = processor configuration switches set improperly. .unh 5 3 = trouble fault attempting to start processor. .unh 5 4 = startup fault attempting to start processor. .unh 5 5 = lockup fault attempting to start processor. .unh 5 6 = processor not in Multics mode. .unh 5 7 = PTW associative memory and/or SDW associative memory not enabled on processor. .unh 5 8 = some system controller could not be accessed by processor. (Output) .inl 0 .spb 2 .ifi l2toc "hphcs_$del_cpu" Name: hphcs_$del_cpu .spb This entry is called to remove a running processor. .spb Usage .spb .all .inl 10 .unl 5 declare hphcs_$del_cpu entry (fixed bin(3), fixed bin(35)); .spb .unl 5 call hphcs_$del_cpu entry (tag, code); .spb .alb .inl 5 .unh 5 1. tag .brf is as described above. (Input) .spb .unh 5 2. code .brf is an error code. The following values are possible: .spb .inl +5 .unh 5 1 = processor did not stop. .unh 5 2 = only one remaining processor configured. (Output) .inl 0 .spb 2 .ifi l2toc "hphcs_$add_mem" Name: hphcs_$add_mem .spb This entry is called to add a system controller and its associated main memory. If the system controller to be added is interlaced with a controller on an adjacent active module port, both system controllers are added. .spb Usage .spb .all .inl 10 .unl 5 declare hphcs_$add_mem entry (fixed bin(3), bit(1) aligned, fixed bin(3), fixed bin(35)); .spb .unl 5 call hphcs_$add_mem (tag, interlace, error_tag, code); .spb .inl 5 .unh 5 1. tag .brf is the tag of the system controller to be added. (Input) .spb .unh 5 2. interlace .brf is set to "1"b if the system controller to be added is interlaced with a system controller on an adjacent active module port. In this case, both system controllers are added. (Output) .spb .unh 5 3. error_tag .brf is the tag of a processor which has the system controller to be added incorrectly configured. (Output) .spb .unh 5 4. code .brf is an error code. The following values are possible: .spb .inl +5 .unh 5 1 = actual memory size is smaller than the size found on the configuration card for the system controller. .unh 5 2 = two interrupt masks are assigned to one processor on the system controller. .unh 5 3 = no mask is assigned to a processor on the system controller. .unh 5 4 = a mask is assigned to a system controller port which is not connected to a processor. .unh 5 5 = some active module has incorrect configuration switch settings for the system controller. .unh 5 6 = some active module is not enabled by the system controller. .unh 5 7 = 4MW SCU is not in PROGRAM mode. (Output) .inl 0 .spb 2 .ifi l2toc "hphcs_$del_mem" Name: hphcs_$del_mem .spb This entry is called to remove a system controller and its associated main memory. If the system controller to be removed is interlaced with a controller on an adjacent active module port, both system controllers are removed. .spb Usage .all .inl 10 .spb .unl 5 declare hphcs_$del_mem entry (fixed bin(3), bit(1) aligned, fixed bin(35)); .spb .unl 5 call hphcs_$del_mem (tag, interlace, code); .spb .alb .inl 5 .unh 5 1. tag .brf is as described above. (Input) .spb .unh 5 2. interlace .brf is as described above. (Input) .spb .unh 5 3. code .brf is an error code which can take on the following value: .spb .inl +5 .unh 5 1 = system controller contains abs wired pages in its memory and cannot be removed. (Output) .inl 0 .spb 2 .ifi l2toc "hphcs_$add_main" Name: hphcs_$add_main .spb This entry is called to add a region of main memory for use by Multics pages. .spb Usage .spb .all .inl 10 .unl 5 declare hphcs_$add_main entry (fixed bin(18), fixed bin(18), fixed bin(35)); .spb .unl 5 call hphcs_$add_main (first_frame, n_frames, code); .alb .inl 5 .spb .unh 5 1. first_frame .brf is the number of the first 1024-word main memory frame to be added. (Input) .spb .unh 5 2. n_frames .brf is the number of main memory frames to be added. (Input) .spb .unh 5 3. code .brf is an error code. (Output) .inl 0 .spb 2 .ifi l2toc "hphcs_$del_main" Name: hphcs_$del_main .spb This entry is called to remove a region of main memory from use by Multics pages. .spb Usage .spb .all .inl 10 .unl 5 declare hphcs_$del_main entry (fixed bin(18), fixed bin(18), fixed bin(35)); .spb .unl 5 call hphcs_$del_main (first_frame, n_frames, code); .alb .inl 5 .spb .unh 5 1. first_frame .brf is as described above. (Input) .spb .unh 5 2. n_frames .brf is as described above. (Input) .spb .unh 5 3. code .brf is an error code. The following values are possible: .spb .inl +5 .unh 5 1 = not enough main memory would be left if this request were honored. .unh 5 2 = region to be removed contains abs wired pages. (Output) .inl 0 .spb 2 .ifi l2toc "hphcs_$reconfig_info" Name: hphcs_$reconfig_info .spb This entry returns the information found in scs$controller_data and scs$processor_data. It locks the reconfiguration data base and leaves it locked. If the data base was previously locked, it returns the process group ID of the process which set the lock. .spb Usage .spb .all .inl 10 .unl 5 declare hphcs_$reconfig_info entry (ptr, fixed bin(35)); .unl 5 declare 1 rci based (rci_ptr) aligned, .alb .fif 2 locker_group_id char (32), 2 controller_data (0: 7) like scs$controller_data, 2 processor_data (0: 7) like scs$processor_data; .spb .fin .unl 5 call hphcs_$reconfig_info (rci_ptr, code); .inl 5 .spb .unh 5 1. rci_ptr .brf is a pointer to the reconfiguration info structure described above. (Input) .spb .unh 5 2. code .brf is an error code. (Output) .inl 0 .spb 2 .ifi l2toc "hphcs_$rc_force_unlock" Name: hphcs_$rc_force_unlock .spb This entry is called only when the reconfiguration lock has been left locked by a system error or by a call to hphcs_$reconfig_info. It forcibly clears the reconfiguration lock. .spb Usage .spb .all .inl 10 .unl 5 declare hphcs_$rc_force_unlock entry; .spb .unl 5 call hphcs_$rc_force_unlock; .inl 0 .alb .ifi l1h "Error Codes" There are several general error codes which may be returned by any of the reconfiguration entries. These are summarized below: .spb .inl 10 .unh 5 11 = reconfiguration data base is locked. .unh 5 12 = device to be added is already online. .unl 5 13 = device to be added is not in the system configuration. .unl 5 14 = device to be removed is not online. .unl 5 15 = requested region of memory is not in the Multics configuration. .brp .inl 0 .fin  s6.rec.compin 10/22/84 1116.2r w 10/22/84 1115.5 100692 ..init_photo "AN71-01" .srv section 6 .ifi l0h "Processor Reconfiguration" This section describes the workings of the processor-adding and processor-deleting functions. Before this can be fully described, however, the mechanism of _i_d_l_e__p_r_o_c_e_s_s_e_s must be briefly explained. .ifi l1h "Idle Processes" There is one idle process for each processor on the system. In general, the idle process for a processor is run whenever that processor cannot find another process to run, either because no other process wants service or because all processes that want service are either running on other processors or are _w_a_i_t_i_n_g for some system event such as a page fault to be satisfied. A processor will never run another processor's idle process. .spb 2 An idle process is a limited Multics process. It has its own descriptor segment, its own APT entry, but no process stack. The idle process for a processor must be created before that processor is added to the system. (This is not quite true for the bootload CPU which must somehow be bootstrapped into the normal state. See S__y_s_t_e_m_I__n_i_t_i_a_l_i_z_a_t_i_o_n, Order No. AN70, for a complete description of this bootstrap mechanism.) Similarly, each processor on the system must have a processor data segment (prds) before it can be run. .spb 2 An APT entry for each configurable processor (i.e. each processor found in the configuration deck) is reserved during system initialization. When a processor is in use, its idle process APT entry is threaded into a list of idle APT entries. The idle process descriptor segments are apportioned from the single unpaged segment "idle_dsegs" during system initialization. The process data segments (pds) are apportioned from "idle_pdses" in a similar manner. A processor data segment (prds) is created when a processor is added and destroyed when a processor is removed. .ifi l1h "Adding a Processor" The program start_cpu is called to add a processor to the system. start_cpu is responsible for creating and initializing the idle process for a processor, managing the assignment of system controller interrupt masks, and starting up a processor. First, start_cpu creates the prds for the processor to be added and fills in certain variables in the idle process APT entry. The APT entry is threaded into the idle list at this time, but it is set to a state that will prevent attempts to use the processor. .spb 2 First, start_cpu ensures that the processor to be started has an interrupt mask assigned to it. If the bootload system controller is a 6000 SC, one interrupt mask must have been assigned to each configurable processor before the system was booted. If the bootload system controller is a 4MW SCU (which has only two interrupt masks) and there are more than two processors in the configuration, the new processor may not have an interrupt mask assigned to it. In this case, another processor must be "persuaded" to give up its interrupt mask and assign it to the new processor. (An SSCR-CFG instruction is issued to the bootload system controller to effect this change.) The mask is cleared and the system controller port to the processor is enabled. .spb 2 Now, the new processor is capable of being interrupted and can be started up. The contents of init_processor$new_dbr are set to the descriptor segment base register value for the new processor's idle process descriptor segment. The contents of init_processor$wait_flag are set to a value which indicates that the processor to be started has not yet responded to its interrupt. The interrupt vector is patched to direct the processor start interrupt to init_processor$first_steps, and the processor start interrupt cell is set via a SMIC instruction. The interrupt mask for the new processor is set to allow only the processor start interrupt. The new processor should immediately respond to that interrupt. (Note that a connect fault could be used to start a new processor, but it is not used for many reasons. One of these is that the interrupt vector location cannot be moved by changing processor switches.) .spb 2 After setting the interrupt cell, start_cpu loops for several milliseconds until init_processor$wait_flag changes. If the new processor started up successfully, the value of wait_flag will be zero. If it failed to respond to the interrupt, start_cpu will time out with the no response error code already in init_processor$wait_flag. If another error condition was detected, wait_flag will contain an error code indicating why the processor could not be added. This error code is returned to the caller of start_cpu. .spb 2 The program init_processor (see S__y_s_t_e_m_I__n_i_t_i_a_l_i_z_a_t_i_o_n, Order No. AN70) is invoked to start the idle processes of all processors on the system, including the bootload processor during system initialization. This program consists of two distinct sections: the initialization code to start a processor and the idle process loop for all processors. The initialization code, in turn, consists of two parts. The first part is entered when the processor start interrupt is received. It runs in absolute mode and checks that all processor switches are set correctly. If the first part of processor initialization is successfully completed, the processor's DBR is loaded and an indirect transfer is executed to place the processor in appending mode and enter the second part of processor initialization. .spb 2 The second part of the initialization code further fills in the idle process APT entry so that the processor can now be assigned to do useful work. It then issues a connect to itself to preempt the idle process and look for useful work for the processor. The wait_flag is cleared, indicating to start_cpu that the processor was successfully started. (The second part of processor initialization is called directly by start_cpu when initializing the idle process of the bootload processor.) .spb 2 The idle loop is essentially an uninhibited DIS instruction with a transfer back to the DIS. A processor which is idle will always be at the DIS instruction. If work exists for the processor, the idle process will be preempted by sending a connect to the processor. .spb 2 Many mechanisms are included in start_cpu and init_processor to allow recovery from operator and hardware errors when attempting to add a processor. Unexpected startup faults, trouble faults, and lockup faults (which sometimes occur for unexplained reasons when adding a processor) are directed to a special place in init_processor during the time that a processor is being added. When init_processor catches such an unexpected fault, it sets a special error code in wait_flag. An SCU instruction is _n_o_t placed in the fault vector for these faults since a processor may experience difficulties in executing an SCU at this time. .spb 2 All processor configuration switches are checked for correctness by init_processor. If one or more switches are incorrect, an appropriate error code is set, and information indicating which switches are in error is returned by start_cpu. If the processor is inadvertently left in GCOS or ABS mode, init_processor will detect the error and an appropriate error code will be returned. If the processor is left in STEP, it will not respond to the processor start interrupt. After several milliseconds, start_cpu will time out and return the no response error code initially placed in init_processor$wait_flag. The init_processor program also checks to make sure that the new processor can access each configured system controller. It does this by issuing a Read Calendar Clock (RCCL) instruction to each configured controller. If, for some reason, a controller cannot be accessed, init_processor intercepts the resultant op-not-complete fault and returns an appropriate error code. The PTW and the SDW associative memories must both be enabled in a processor to be added; init_processor checks to make sure that this is so. .spb 2 One error condition especially difficult to detect is the incorrect setting of the memory assignment switches on a processor. Such an error may cause the processor to believe that its fault and interrupt vectors are located in a system controller other than the bootload system controller. Recovery from such an error is accomplished by replacing the contents of the first two memory frames of each system controller with a special fault and interrupt vector image contained in the program fv_iv_template. Upon intercepting any fault or interrupt, fv_iv_template will direct the processor to read its switches and store them in a reserved place. It will then stop the processor at an inhibited DIS. If start_cpu times out, it will search the reserved place in each copy of fv_iv_template to see if processor switch data has been stored there. If data has been stored, start_cpu will return the error code indicating that a configuration switch error has occurred along with data indicating which switches are in error. .spb .inl 10 .unh 10 NOTE: If more than one system controller is incorrectly assigned as the bootload system controller on the configuration panel of a processor to be added, the recovery method described above will probably fail. This is one of the few error conditions that cannot be handled by the reconfiguration software. .inl 0 .spb 2 Since no operator intervention or interaction is normally required to add a processor to the system, it is possible to bootload a system with several processors in the configuration. Additional processors will automatically be started at the completion of system initialization. .ifi l1h "Removing a Processor" The program stop_cpu is called to remove a processor from the system. It first checks to see if the processor being removed is the BOS (or bootload) processor. If it is, a new BOS processor is assigned. If the bootload system controller is a 4MW SCU, the processor relinquishes its interrupt mask. If any other processors are currently running without an assigned interrupt mask, the freed interrupt mask is given to one such processor. Now the processor is ready to be stopped. The delete_cpu bit in scs$processor_data for the processor is set and a preempt connect is sent to the processor. .spb 2 When the dying processor receives the preemption, it enters special code in the traffic controller. The idle process APT entry is updated in order to prevent further use of the processor. The halted_cpu bit is turned on in scs$processor_data for the processor, and the processor is stopped at an inhibited DIS instruction. .spb 2 When stop_cpu detects the halted_cpu bit, it proceeds with destroying the processor's prds and removing its idle APT entry from the thread of idle APT entries. .spb 2 During system shutdown, stop_cpu is called automatically to remove all processors other than the BOS processor. It is therefore not necessary to manually remove processors before shutting down Multics. .brp .fin .inl 0  s7.rec.compin 10/22/84 1116.2r w 10/22/84 1115.5 63207 ..init_photo "AN71-01" .srv section 7 .ifi l0h "Memory Reconfiguration" This section describes the mechanisms used to dynamically reconfigure main memory (core or MOS memory). Two subsections describe system controller reconfiguration and another two describe main memory frame reconfiguration within a controller. .ifi l1h "Adding Main Memory" At system initialization time, the data bases scs$controller_data and the main memory map in the SST are initialized. These are initialized from the configuration deck (and active register values); since the main memory map cannot easily be grown, it is required that any system controllers that will ever be configured to the system for a given bootload must be specified in the configuration deck. This is done by using an ON or OFF field of the MEM configuration cards. All system controllers actually configured and to be used at bootload time are indicated as being ON. Other system controllers are OFF. .spb 2 When the main memory map is initially set up, only map entries for main memory frames which are in configured system controllers are threaded into the used list. Map entries for main memory frames in system controllers that are not yet configured are left alone and threaded into no list. To add a main memory frame to the system, all that need be done is to thread the map entry for the frame into the main memory used list. This is exactly what is done after an addmain request is given. .spb 2 A frame of main memory is added by calling freecore, a primitive in Multics page control. Before threading the map entry for a frame into the used list, freecore touches all words in the frame. It then notes if any parity errors occurred. A main memory frame containing one or more words with parity errors will not be added to the used list. .ifi l1h "Adding a System Controller" To add a system controller to the system, reconfig checks consistency of all arguments and calls add_scu to actually add the system controller. The program add_scu fills in the PTW for the page of the SCAS used to reference the system controller. It then forces the executing process to run on all processors and attempt to reference the system controller. If the controller is not properly configured at a processor configuration panel, or if a processor is not enabled at the system controller, a fault will occur. Any fault will be caught by add_scu and reflected back to the caller as an error. Note that no mechanism currently exists to check the configuration switches on the IOM and the bulk store. .spb 2 If the system controller can be successfully accessed by all processors, add_scu returns to reconfig which can then make calls to freecore to thread the main memory map entries for each main memory frame in the controller into the used list. If an attempt is made to add a system controller which is interlaced with a another controller on an adjacent active module port, both controllers will be added automatically. Two calls are made to add_scu before the main memory shared by the two controllers is added. .ifi l1h "Removing a System Controller" Two major problems are involved in removing a system controller from the system. First, a mechanism must be provided to remove all references to any pages in the system controller by processors. This mechanism is described in the following subsection. .spb 2 The second major problem in removing main memory, that of preventing other active modules from referencing the memory is solved before it even becomes a problem. This is accomplished via the abs_wiring technique, which requires that _a_n_y pages which are referenceable via nonprocessor active modules (e.g., the IOM) cannot reside in a deconfigurable system controller. In order to do this, certain system controllers are set up as "abs_usable" and hence nondeconfigurable. For most configurations, the bootload system controller alone is abs_usable, but the system dynamically chooses other controllers as necessary if there is not enough abs_wireable memory in the bootload system controller. .spb 2 Therefore, any program that uses a page for I/O (that is not permanently wired) must call a special program to have the page wired down. This program is "pc_contig". (See S__t_o_r_a_g_e_S__y_s_t_e_m, Order No. AN61, for a complete description of this mechanism.) Thus, the dynamic reconfiguration software need not be concerned about pages wired for I/O activity. .ifi l1h "Removing Main Memory" The problem in removing main memory mentioned above, that of preventing processors from referencing the memory, is not hard to solve since all processor references to the memory are made indirectly through PTWs over which the system software has control. (It is not possible to remove memory which contains permanently wired code or data.) It is thus necessary only to remove access in PTWs or to copy pages into main memory which is not being removed. This in fact is just what is done. There are three cases to consider: .spb .inl 10 .unh 5 1. Main memory frames that contain wired pages. .spb .unh 5 2. Main memory frames that contain pages that are not wired but are modified. .spb .unh 5 3. Other main memory frames. .spb 2 .inl 0 Pages which are temp-wired must remain in main memory but need not remain in the same frame of main memory. Such pages are copied from the region of memory being removed to a region of memory remaining. After the copy is complete, the PTW is changed to point to the new copy, and all processors are forced to clear their associative memories so that they will refetch the PTW with the new address (making all subsequent references to the new copy). If the page is modified while the copy is being performed, all processors are stopped (forced to loop lock via a connect fault), and the copy is made while no other processor can modify the data. The entire mechanism to move a wired page is implemented in the subroutine evict_page. .spb 2 Pages that are modified are simply written out to secondary storage and evicted when the I/O completes. This process continues until a page does not get modified while the I/O is going on, in which case the frame of memory can be claimed. .spb 2 Pages that are neither wired nor modified are evicted immediately (the PTW is set to fault) unless is I/O is in progress, in which case the I/O is waited for and the page is evicted on the next pass. .spb 2 The program responsible for performing all this work is pc_abs$remove_core. It loops through all frames to be removed until a pass is completed that leaves no frames unclaimed. Note that a request to remove a frame that is already removed is not considered to be an error. Such a condition might well occur when an operator makes a request to remove an entire controller after having removed several main memory frames in that controller. .ifi l1h "Automatic Memory Removal" (To be supplied.) .brp .fin .inl 0  s8.rec.compin 10/22/84 1116.2r w 10/22/84 1116.0 756 ..init_photo "AN71-01" .srv section 8 .ifi l0h "FILL ME IN CHRIS!" .brp .fin .inl 0  s9.rec.compin 10/22/84 1116.2r w 10/22/84 1116.0 7641 ..init_photo "AN71-01" .srv section 9 .ifi l0h "The Command Interface" The reconfiguration of main memory, processors, and bulk store is under operator control either from an "initializer" terminal or from a privileged logged-in user. The initializer commands are as follows: .spb .inl 5 .fif addcpu delcpu addmem delmem addmain delmain addpage delpage .fin .spb .inl 0 These are described fully in the M__u_l_t_i_c_s O__p_e_r_a_t_o_r'__s H__a_n_d_b_o_o_k, Order No. AM81. .spb 2 The normal user commands are as follows: .spb .inl 5 .fif addcpu delcpu addmem delmem addmain delmain addpag delpag .fin .inl 0 .spb The following special command is also provided: .spb .inl 5 reconfigure$force_unlock .inl 0 .spb 2 Note that there is no initializer command to unlock the reconfiguration lock. .brp .fin .inl 0 ----------------------------------------------------------- Historical Background This edition of the Multics software materials and documentation is provided and donated to Massachusetts Institute of Technology by Group BULL including BULL HN Information Systems Inc. as a contribution to computer science knowledge. This donation is made also to give evidence of the common contributions of Massachusetts Institute of Technology, Bell Laboratories, General Electric, Honeywell Information Systems Inc., Honeywell BULL Inc., Groupe BULL and BULL HN Information Systems Inc. to the development of this operating system. Multics development was initiated by Massachusetts Institute of Technology Project MAC (1963-1970), renamed the MIT Laboratory for Computer Science and Artificial Intelligence in the mid 1970s, under the leadership of Professor Fernando Jose Corbato. Users consider that Multics provided the best software architecture for managing computer hardware properly and for executing programs. Many subsequent operating systems incorporated Multics principles. Multics was distributed in 1975 to 2000 by Group Bull in Europe , and in the U.S. by Bull HN Information Systems Inc., as successor in interest by change in name only to Honeywell Bull Inc. and Honeywell Information Systems Inc. . ----------------------------------------------------------- Permission to use, copy, modify, and distribute these programs and their documentation for any purpose and without fee is hereby granted,provided that the below copyright notice and historical background appear in all copies and that both the copyright notice and historical background and this permission notice appear in supporting documentation, and that the names of MIT, HIS, BULL or BULL HN not be used in advertising or publicity pertaining to distribution of the programs without specific prior written permission. Copyright 1972 by Massachusetts Institute of Technology and Honeywell Information Systems Inc. Copyright 2006 by BULL HN Information Systems Inc. Copyright 2006 by Bull SAS All Rights Reserved