05/22/84 write_notify_test

Syntax:  write_notify_test {CPU_STR} {-control_args}


Function:  Test the ability of the DPS8M CPU and SCU interface to
         selectively clear CACHE when  another active unit writes
         into main memory. As an active function return the results
         of the test (see NOTE).

Arguments:
CPU_STR
     This is a  character string of cpus to  use for testing.  At
     least two cpus  are required, and one must  be a DPS8M.  The
     default is  to select all  the DPS8M cpus on  the system, if
     only one DPS8M cpu if found to be on_line then a L68 will be
     used as the  second processor.  If There is  only one cpu on
     system, or there are no DPS8M cpus the test will not run.


Control arguments:
-brief, -bf
     Displays the brief form of  errors and meters.  This control
     argument is the default.
-deactivation_count, -dc N
     This is number  (N) of times to deactivate  the data segment
     used.  This  deactivation is to  change the location  of the
     test page  in main memory.   The default is 1%  of the total
     on_line pages.
-loop_count, -lc N
     This is the number (N)  of times to loop before deactivating
     the segment.  The default is 10.
-long, -lg
     Displays the long form of errors and meters.
-meter
     Displays  the  memory  utilization  percentages.   If  -long
     argument has  been given then  the actual pages  and address
     lines are displayed.
-word_increment, -wi N
     This is the word increment to use for the test page.  N is a
     decimal  number  greater that  0  and less  that  1023.  The
     default is 52.


NOTE:  This command requires phcs_ and hphcs_ access.
       
       When invoked as an active function write_notify_test will return
       the results of the test. If no erroes are found, the return
       string is the word "passed". If the test detects errors then
       the first word of the return string is "failed" followed by the
       failing unit or units.
  example:
       failed CPU_A
       or
       failed CPU_A SCU_B


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Historical Background

This edition of the Multics software materials and documentation is provided and donated
to Massachusetts Institute of Technology by Group BULL including BULL HN Information Systems Inc. 
as a contribution to computer science knowledge.  
This donation is made also to give evidence of the common contributions of Massachusetts Institute of Technology,
Bell Laboratories, General Electric, Honeywell Information Systems Inc., Honeywell BULL Inc., Groupe BULL
and BULL HN Information Systems Inc. to the development of this operating system. 
Multics development was initiated by Massachusetts Institute of Technology Project MAC (1963-1970),
renamed the MIT Laboratory for Computer Science and Artificial Intelligence in the mid 1970s, under the leadership
of Professor Fernando Jose Corbato. Users consider that Multics provided the best software architecture 
for managing computer hardware properly and for executing programs. Many subsequent operating systems 
incorporated Multics principles.
Multics was distributed in 1975 to 2000 by Group Bull in Europe , and in the U.S. by Bull HN Information Systems Inc., 
as successor in interest by change in name only to Honeywell Bull Inc. and Honeywell Information Systems Inc. .

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Permission to use, copy, modify, and distribute these programs and their documentation for any purpose and without
fee is hereby granted,provided that the below copyright notice and historical background appear in all copies
and that both the copyright notice and historical background and this permission notice appear in supporting
documentation, and that the names of MIT, HIS, BULL or BULL HN not be used in advertising or publicity pertaining
to distribution of the programs without specific prior written permission.
    Copyright 1972 by Massachusetts Institute of Technology and Honeywell Information Systems Inc.
    Copyright 2006 by BULL HN Information Systems Inc.
    Copyright 2006 by Bull SAS
    All Rights Reserved