" " Begin include file get_cache.incl.alm " " Bernard Greenberg Feb. 1974 " " Last modified by Sherman D. Sprague 02/11/81 for DPS8 support. include cache_mode_reg " get_cache: "routine to fill up cache_dir and cache_contents "with contents of directory and cache. "One column is accessed. "Starting address is passed in A. ana ccolm1x4 insure good address eax5 0 x5 counts along cache contents sta cache_tempg save cache address absa fltscu get scuu adddress als 6 assume in 256 k stca cache_parity_pair,70 put in scu inst ldaq mem|64+2*9 save parity fault pair staq cache_save_parity_pair ldaq cache_parity_pair staq mem|64+2*9 set up our handler lda com|corearea low 12 bits are mod 64 free core als 6 normalize to real address adla clstcadd round up to double page ana cnegcsz and truncate adla cache_tempg add specified displacement epp xs1,mem|0,al xs1 is 4 " pr necessary because addr may be greater than "fixed bin (14) disp.possible. eax7 -4 x7 counts levels scpr cache_dump_mode_off-1,06 save old cache/luf reg (might be on) lda cache_dump_mode_off get old setting ora cmr.cache_to_reg_mode,dl put on special mode bit sta cache_dump_mode_on set for loading control reg get_cache_loop: ldaq xs1|0 get stuff which will be clobbered staq cache_tempg inhibit on "we must not take interrupts while we "mess around with possible Multics core. scpr xs1|0,06 get status register/directory entry lda xs1|1 get this status word sta cache_dir+4,7 store it in directory ldaq cache_tempg staq xs1|0 restore memory "following instruction "will put processor in a most anomalous state, "and _n_o_t_h_i_n_g must disturb us while in this state. lcpr cache_dump_mode_on,02 force all OU double loads from cache. ldaq xs1|0 get 2 lower words staq cache_contents,5 store them. ldaq xs1|2 get 2 upper words staq cache_contents+2,5 And store them. lcpr cache_dump_mode_off,02 Restore normalcy in processor. get_cache_ignore_parf: inhibit off eax5 4,5 Set for next 4 word entry. adwp xs1,cclvincr increment addr to next level eax7 1,7 tmi get_cache_loop Get more if needed. ldaq cache_save_parity_pair restore parity fault staq mem|64+2*9 tra 0,2 even " following words must be an even/odd pair cache_dump_mode_on: zero 0,cmr.cache_to_reg_mode+3 "cache mode reg to set "dump mode. 3 is lockup fault setting. cache_dump_mode_off: zero 0,3 "set dump mode off. even cache_dir: bss ,4 "Cache directory and status words, one "for each 4 words in cache_contents. cache_contents: bss ,16 "Cache contents, 4 words at a time. cache_tempg: oct 0,0 cache_fail_temp: oct 0,0 cache_save_parity_pair: oct 0,0 save for parity fault vector cache_parity_pair: scu *-* instr to store cu tra pgm|cache_parity_fault cache_parity_fault: lcpr cache_dump_mode_off,02 STOP THAT CRAZY BIT! scpr cache_fail_temp,01 get poss cache problem lda cache_fail_temp cana =o17,dl check cache bits tnz get_cache_ignore_parf forget it if so ldaq cache_save_parity_pair restore fv staq mem|64+9*2 lda cch_gt_nopinst pick up noop staq mem|64+6*2 set up drl to wantflt drl 0 simulate real handling cch_gt_nopinst: nop 0 " " End include file get_cache.incl.alm " " " " ----------------------------------------------------------- " " " " Historical Background " " This edition of the Multics software materials and documentation is provided and donated " to Massachusetts Institute of Technology by Group Bull including Bull HN Information Systems Inc. " as a contribution to computer science knowledge. " This donation is made also to give evidence of the common contributions of Massachusetts Institute of Technology, " Bell Laboratories, General Electric, Honeywell Information Systems Inc., Honeywell Bull Inc., Groupe Bull " and Bull HN Information Systems Inc. to the development of this operating system. " Multics development was initiated by Massachusetts Institute of Technology Project MAC (1963-1970), " renamed the MIT Laboratory for Computer Science and Artificial Intelligence in the mid 1970s, under the leadership " of Professor Fernando Jose Corbato. Users consider that Multics provided the best software architecture for " managing computer hardware properly and for executing programs. Many subsequent operating systems " incorporated Multics principles. " Multics was distributed in 1975 to 2000 by Group Bull in Europe , and in the U.S. by Bull HN Information Systems Inc., " as successor in interest by change in name only to Honeywell Bull Inc. and Honeywell Information Systems Inc. . " " ----------------------------------------------------------- " " Permission to use, copy, modify, and distribute these programs and their documentation for any purpose and without " fee is hereby granted,provided that the below copyright notice and historical background appear in all copies " and that both the copyright notice and historical background and this permission notice appear in supporting " documentation, and that the names of MIT, HIS, Bull or Bull HN not be used in advertising or publicity pertaining " to distribution of the programs without specific prior written permission. " Copyright 1972 by Massachusetts Institute of Technology and Honeywell Information Systems Inc. " Copyright 2006 by Bull HN Information Systems Inc. " Copyright 2006 by Bull SAS " All Rights Reserved " "