" " Begin include file .... getportinfo.incl.alm " " This routine initializes the coreblocks array in bos_common. " This array contains information about the memory attached to " each of the eight system ports. " " Each coreblock array word contains the following data: " Bits 0 - 17 Number of the first 64-word block on this port. " 18 - 35 Number of 64-word blocks on this port. " " NOTE: If there is no memory on this port then the corresponding word in " the coreblocks array will contain a ( -1 ). " Modified by RE Mullen to rscr for benefit of setup. " Modified 9/12/74 by Noel I. Morris to correct rsw instruction. " Modified 3/11/76 by Noel I. Morris to run with 4MW SCU. " Modified 5/12/77 by Noel I. Morris " Modified 9/18/80 by Sherman D. Sprague to run with DPSE cpu. " Modified 3/29/82 by Sherman D. Sprague to teach the L68 about 4meg ports and " to make him forget 96k... Remember, use a Group 10 patch plug for 4meg. " Modified 9/28/82 by J. Bongiovanni to save low order port in toehold getportinfo: stx2 gpir store x2 for return mlr (),(pr),fill(777) clear coreblock array to zero desc9a 0,0 desc9a com|coreblocks,8*4 tsx2 check_cpu_type get cpu type stq sw_store_2 save for later use eax6 size_code_table_dps8 set up DPS8 store size multiplier eax4 0,al save cpu type bits cmpx4 1,du check for DPS8 tze read_sw_1 skip rsw 4 DPS8 can't do it eax6 size_code_table set up L68 store size mltiplier rsw 4 get half/full info sta sw_store_4 might want the look at later ?? alr 13+2 position for examining half/full bits sta switches_4 and save for later read_sw_1: stx6 get_table store size table to use eax7 0 X7 used as port number index. rsw 1 Read config switches of 1st 4 ports. (A,B,C,D) sta sw_store_1 might want to look at later ?? set_word: llr 9 Shift switches for this port into low Q. sta save_switches Save switches for use later. canq =o040,dl Test Port Enable switch. tze get_next_port Bit off => port not enabled. " There is memory on this port. Test if this port has the low order memory. canq =o700,dl Test Address Assignment switches. tnz not_low_port Not = 0 => not low order memory. " This port is used for the low order memory. It will be called the " ( low_order_port ). Note, it isn't necessarily port 0. eaa 0,7 Port number in AU. als 18-3 Port address in AU. sta com|low_order_port Use this port as the low order port. not_low_port: eax5 0,ql Get switches for this port in X5. anx5 =o007,du We want memory size code. anq =o700,dl Just leave port assignment bits in Q. qls 18-6 Right justify port assignment bits in QU. orq =1,dl Put a 1 in QL. Used to compute memory size. mpy get_table,*5 Compute both base address and memory size. cmpx4 1,du Check for DPS8 tze full_mem must be DPS8 lda switches_4 half/full info in A cana 1,dl are we using half of mem? tze full_mem if not, skip following code lls 18 place base addr in AL qrl 1 divide size by 2 lrl 18 and restore base addr to Q full_mem: stq com|coreblocks,7 QU = base address - QL = memory size. get_next_port: eax7 1,7 make index 7 ref next port cmpx4 1,du Is this a DPS8 tnz L68 lda save_switches restore switches for next port cmpx7 4,du Is this the last DPS8 tmi set_word tra gpi_return L68: lda switches_4 rotate half/full info alr 2 for testing next port sta switches_4 .. lda save_switches Restore switches for next ports. cmpx7 4,du Must we read switches again? tnz more_ports If so, rsw 3 Read switches from ports E,F,G,H. sta sw_store_3 save rsw3 data untouched more_ports: cmpx7 8,du Have we processed all 8 ports? tnz set_word If not, loop. gpi_return: gpir: eax2 * set up for return tra 0,2 return " A temporary save area. save_switches: oct 0 Save A after read switches and shift. sw_store_1: oct 0 Here to store read switch info untouched sw_store_2: oct 0 Here to store read switch info untouched sw_store_3: oct 0 Here to store read switch info untouched sw_store_4: oct 0 Here to store read switch info untouched switches_4: oct 0 Save half/full switches here get_table: zero 0,0 " The following table is used to map memory size codes into memory size " for L68 and DPS cpu's size_code_table: vfd 36/(32*1024/64) vfd 36/(64*1024/64) vfd 36/(4096*1024/64) vfd 36/(128*1024/64) vfd 36/(512*1024/64) vfd 36/(1024*1024/64) vfd 36/(2048*1024/64) vfd 36/(256*1024/64) " The following table is used to map memory size codes into memory size " for DPSE cpu's size_code_table_dps8: vfd 36/(32*1024/64) vfd 36/(64*1024/64) vfd 36/(128*1024/64) vfd 36/(256*1024/64) vfd 36/(512*1024/64) vfd 36/(1024*1024/64) vfd 36/(2048*1024/64) vfd 36/(4096*1024/64) " End of include file .... getportinfo.incl.alm " " " ----------------------------------------------------------- " " " " Historical Background " " This edition of the Multics software materials and documentation is provided and donated " to Massachusetts Institute of Technology by Group Bull including Bull HN Information Systems Inc. " as a contribution to computer science knowledge. " This donation is made also to give evidence of the common contributions of Massachusetts Institute of Technology, " Bell Laboratories, General Electric, Honeywell Information Systems Inc., Honeywell Bull Inc., Groupe Bull " and Bull HN Information Systems Inc. to the development of this operating system. " Multics development was initiated by Massachusetts Institute of Technology Project MAC (1963-1970), " renamed the MIT Laboratory for Computer Science and Artificial Intelligence in the mid 1970s, under the leadership " of Professor Fernando Jose Corbato. Users consider that Multics provided the best software architecture for " managing computer hardware properly and for executing programs. Many subsequent operating systems " incorporated Multics principles. " Multics was distributed in 1975 to 2000 by Group Bull in Europe , and in the U.S. by Bull HN Information Systems Inc., " as successor in interest by change in name only to Honeywell Bull Inc. and Honeywell Information Systems Inc. . " " ----------------------------------------------------------- " " Permission to use, copy, modify, and distribute these programs and their documentation for any purpose and without " fee is hereby granted,provided that the below copyright notice and historical background appear in all copies " and that both the copyright notice and historical background and this permission notice appear in supporting " documentation, and that the names of MIT, HIS, Bull or Bull HN not be used in advertising or publicity pertaining " to distribution of the programs without specific prior written permission. " Copyright 1972 by Massachusetts Institute of Technology and Honeywell Information Systems Inc. " Copyright 2006 by Bull HN Information Systems Inc. " Copyright 2006 by Bull SAS " All Rights Reserved " "