" " Begin include file ...... intflt.incl.alm " This routine initializes the fault and interrupt vector and sets up the execute interrupt " Modified 3/15/76 by Noel I. Morris " Modified by Sherman D. Sprague 02/11/81 for DPS8 support. " Modified by Sherman D. Sprague 10/5/81 for change in AM store procedure. " Modified by J. Bongiovanni 1/7/82 to spl on faults and interrupts bool fvloc,100 absolute loc'n of fault vector bool ivloc,0 absolute loc'n of interrupt vector equ drl,6 derail fault # equ timer,4 timer runout fault # equ lockup,7 lockup fault # equ exec,15 execute fault # even hist_on: oct 61 inhibit on initint: eax7 0,2* address for xec fault stx7 exloc+1 mlr (),(),fill(0) set up to clear hist store area desc9a *,0 desc9a intflt_ouhist,128*4*4 mlr (),(),fill(0) set up to clear am stor area desc9a *,0 desc9a intflt_amptwptr,320*4 " Relocate to absolute all instructions with bit 29 ON. eax7 labsarea-1 do this many words ldq =o777677,dl mask in Q for clearing addr and bit 29 relop: lda absarea,7 instruction in A cana =o100,dl bit 29 ON? tze notrel if not, don't relocate stba *+1,60 set address and segment tag absa 0|0 ****** THIS INSTRUCTION GETS MODIFIED ****** als 6 absolute addr in AU ansq absarea,7 clear old addr and segment tag orsa absarea,7 insert absolute address notrel: eax7 -1,7 tpl relop eax7 64-2 set all fault pairs ldaq unexpair to unexpected fltloop: cmpx7 lockup*2,du except lockup tze skipflt cmpx7 timer*2,du and timer runout tze skipflt staq mem|fvloc,7 skipflt: eax7 -2,7 tpl fltloop ldaq lockfltpair now set lockup fault staq mem|fvloc+lockup*2 ignore them staq mem|fvloc+timer*2 also ignore timer runouts ldaq exintpair take exec faults staq mem|fvloc+exec*2 store into vector eax7 64-2 fill intrpt vectors ldaq intpair get pair initintl: staq mem|ivloc,7 store in first block eax7 -2,7 tpl initintl lcpr pgm|hist_on,04 turn on hist regs tra 1,2 return even exloc: its pgm,0 go to appending mode gotflt: its pgm,0 go to appending mode equ wantflt,gotflt+1 set if user wants control on fault absarea: "beginning here all addrs are changed to abs interentry: sreg pgm|intflt_regs here after execute fault lcpr pgm|hist_on,04 turn on history registers spl pgm|intflt_ptrlen and revive EIS box tra pgm|exloc,* unexpflt: spl pgm|intflt_ptrlen clear EIS box in case of mif szn pgm|wantflt if anybody wants unexpected fault tze pgm|*+3 go to it lcpr pgm|hist_on,04 but first, turn on history registers tra pgm|gotflt,* then go to appending mode sreg pgm|intflt_regs tsx2 pgm|check_cpu_type eax4 0,al save cpu type int_sam1: eax7 4 eax6 3 set up for a dps8 cmpx4 1,du were we right? tze pgm|int_sam2 yes ,now thats a first! eax6 0 so we were wrong its a l68 int_sam2: lda pgm|int_sam5-1,7 load instruction word to be executed eax5 0,6 set up counter int_sam3: eaq 0,5 but counter in q qls 4 multiply times 4 cmpx7 2,du is this the sdw regs ? tnz pgm|int_sam4 qls 1 it was so make it times 32 int_sam4: sta pgm|int_inst store instruction word to be XECed asq pgm|int_inst add in quadrant offset xec pgm|int_inst lets execute it eax5 -1,5 decrement counter tpl pgm|int_sam3 lets do it again eax7 -1,7 get another instruction tnz pgm|int_sam2 do it again " save the history registers ldq 2,du address field step eax6 nint_scpr-1 # of instructions intscpr2: eax7 16 16 instructions to store a history register cmpx4 1,du check cpu type tnz pgm|intl68 skip next instruction if l68 eax7 64 set up for dps8 intl68: lda pgm|int_scpr,6 pick up inst sta pgm|int_inst intscpr1: xec pgm|int_inst execute it asq pgm|int_inst incrment address field eax7 -1,7 decrement loop tnz pgm|intscpr1 not done eax6 -1,6 next ? tpl pgm|intscpr2 get next inst tra pgm|* now wait even lockfltpair: scu pgm|intflt_scuignore ignore lockup faults tra pgm|rstart_hist exintpair: scu pgm|intflt_scuignore tra pgm|interentry unexpair: scu pgm|scuinfo unexpected fault tra pgm|unexpflt intpair: scu pgm|intflt_scuignore int pair for int vector tra pgm|intset rstart_hist: "here to restart hist regs after ignored fault lcpr pgm|hist_on,04 rcu pgm|intflt_scuignore intset: sreg pgm|intflt_regs here from intrpt spl pgm|intflt_ptrlen clear EIS box lda pgm|intflt_scuignore+scu.fltint_num ana scu.fltint_num_mask,dl als 18-scu.fltint_num_shift right justify in upper sta pgm|intno ldq =o400000,du qrl 0,au position bit orsq pgm|intrpts1 lreg pgm|intflt_regs restore rcu pgm|intflt_scuignore and return int_sam5: ssdp pgm|intflt_amsdwptr ssdr pgm|intflt_amsdwregs sptp pgm|intflt_amptwptr sptr pgm|intflt_amptwregs int_scpr: scpr pgm|intflt_ouhist,40 scpr pgm|intflt_cuhist,20 scpr pgm|intflt_eishist,10 scpr pgm|intflt_aphist,00 equ nint_scpr,*-int_scpr equ labsarea,*-absarea end of abs area inhibit off int_inst: bss ,1 equ scu.fltint_num,1 bool scu.fltint_num_mask,76 equ scu.fltint_num_shift,1 intno: oct 0 intrpts1: oct 0 mod 16 intflt_amptwregs: bss ,64 mod 16 intflt_amptwptr: bss ,64 mod 16 intflt_amsdwregs: bss ,128 mod 16 intflt_amsdwptr: bss ,64 eight intflt_scu: bss ,8 intflt_scuignore: bss ,8 eight intflt_ouhist: bss ,128 intflt_cuhist: bss ,128 intflt_eishist: bss ,128 intflt_aphist: bss ,128 eight intflt_regs: bss ,8 intflt_ptrlen: bss ,8 intflt_mode: bss ,1 " End of include file ...... intflt.incl.alm " " " ----------------------------------------------------------- " " " " Historical Background " " This edition of the Multics software materials and documentation is provided and donated " to Massachusetts Institute of Technology by Group Bull including Bull HN Information Systems Inc. " as a contribution to computer science knowledge. " This donation is made also to give evidence of the common contributions of Massachusetts Institute of Technology, " Bell Laboratories, General Electric, Honeywell Information Systems Inc., Honeywell Bull Inc., Groupe Bull " and Bull HN Information Systems Inc. to the development of this operating system. " Multics development was initiated by Massachusetts Institute of Technology Project MAC (1963-1970), " renamed the MIT Laboratory for Computer Science and Artificial Intelligence in the mid 1970s, under the leadership " of Professor Fernando Jose Corbato. Users consider that Multics provided the best software architecture for " managing computer hardware properly and for executing programs. Many subsequent operating systems " incorporated Multics principles. " Multics was distributed in 1975 to 2000 by Group Bull in Europe , and in the U.S. by Bull HN Information Systems Inc., " as successor in interest by change in name only to Honeywell Bull Inc. and Honeywell Information Systems Inc. . " " ----------------------------------------------------------- " " Permission to use, copy, modify, and distribute these programs and their documentation for any purpose and without " fee is hereby granted,provided that the below copyright notice and historical background appear in all copies " and that both the copyright notice and historical background and this permission notice appear in supporting " documentation, and that the names of MIT, HIS, Bull or Bull HN not be used in advertising or publicity pertaining " to distribution of the programs without specific prior written permission. " Copyright 1972 by Massachusetts Institute of Technology and Honeywell Information Systems Inc. " Copyright 2006 by Bull HN Information Systems Inc. " Copyright 2006 by Bull SAS " All Rights Reserved " "