" *********************************************************** " * * " * Copyright, (C) Honeywell Information Systems Inc., 1982 * " * * " * Copyright (c) 1972 by Massachusetts Institute of * " * Technology and Honeywell Information Systems, Inc. * " * * " *********************************************************** " " " BOS ABS Command " " Bernard Greenberg, Mar. l974 " " Last modified 2/11/81 by Sherman D. Sprague for DPS8 include bos_sdw include bosequ include pt_equ include bos_common include bos_tv include apnd_equ include bos_ptw include sst include aste include cmp " " stx2 x2 save return address tsx2 initint initialize intflt package arg cycle depending on mode of invocation, "either exit of cycle on exec flt tsx2 init_io set up i/o for printing tsx2 ttyinit initialize opr console arg cycle req will be like exec flt tsx2 absresolve_init must be done before loading pring lda =h ptpkg set to load printing package eaq pt_org at its rightful address tsx2 ldcom load it tsx2 fatal die if error tsx2 initprint initiailize print package mlr (),() desc6a hdrln,(hdend-hdrln)*6 move in header desc6a pthdr,(hdend-hdrln)*6 tsx2 rdclock get date/time in header sta pthdr+(hdend-hdrln)+2 stq pthdr+(hdend-hdrln)+3 ldx2 x2 see if args given ldx2 mem|0,2 pick up parsed arg pointer lda mem|1,2 pick up possible first arg cmpa =-1 fence is no args tze setcycle enter cycle mode if no args ldx3 x2 "get address of source line ldq mem|0,3 "get pointer wd anq -1,dl get lower address mpy 6,dl convert to chars mlr (pr,ql),(),fill(020) desc6a mem|0,14*6 desc6a line,14*6 tsx2 scan rescan args eax0 0 set to move out command name fix_arg_loop: lda arg+1,0 sta arg,0 lda darg+1,0 sta darg,0 eax0 1,0 cmpa =-1 see if moved fence tnz fix_arg_loop no, move more args eax7 fthdlr we will take faults, could be cache error. stx7 wantflt,* start: lda arg inspect first arg cmpa =h dump see if full dump wanted tze dump tra if yes cmpa =h quit tze x2 cmpa =h cache tze cache cache compare and dump cmpa =h tape xed prtcmd arg tapeon cmpa =h prt xed prtcmd arg printon cmpa =h eof xed prtcmd arg wteof cmpa =-1 tze qm no args wrong szn arg test for a zero tze num this is legal num szn darg check for numeric tnz num num is ok qm: tsx2 erpt unrecognized command acc '^g' print ?? arg =h!!???? cycle: szn cyclesw see if single or multiple command mode tze x2 return if not in cycle mode tsx2 nextline get next line tra start setcycle: stc1 cyclesw tra cycle cyclesw: oct 0 x2: eax2 *-* restore index 2 lca 1,dl set fence for next-command protocol tra mem|1,2 hdrln: bci '1multics absolute core analysis ' hdend: even " s/r to test print control options prtcmd: tnz 2,ic tsx1 *+1 tsx2 0,1* tra cycle " fthdlr: scpr fault_temp,01 get fault reg- could be cache problem lcpr =3,02 turn off cache tsx2 erpt print out data acc 'unexp fault - fault reg = ^w' arg fault_temp tsx2 erpt print out scu data acc 'scu data :^w ^w ^w ^w' arg fltscu arg fltscu+1 arg fltscu+2 arg fltscu+3 tsx2 erpt acc '^w ^w ^w ^w' arg fltscu+4 arg fltscu+5 arg fltscu+6 arg fltscu+7 " " " Patch next instruction to NOP for debugging. " " halt: tra cycle tsx2 erpt acc 'doing a dis/tra *-1' dis tra *-1 fatal: eax2 -1,2 make x2 point to tsx2 fatal sxl2 temp_fatal save addr for printing tsx2 erpt print out message acc 'unexpected fatal error at ^o' arg temp_fatal tra halt temp_fatal: oct 0 " " " ABS nnnnnnn etc. " num: lda arg get arg tsx2 absresolve do our thing tra num_err out of core bounds tsx2 type print on opty zero line,14 might truncate to 14 chars tra cycle num_err: tsx2 erpt acc 'address not in core- ^o' arg arg tra cycle " " " " ABS DUMP " " use in conjuction with DUMP ABS if desired " dump: " First, must determine extent of core mlr (pr),() desc9a com|coreblocks,4*8 desc9a a_coreblocks,4*8 coresort: stz pass_mod assume no mod this pass eax0 0 corelp1: ldq a_coreblocks+1,0 get larger word, if good cmpq a_coreblocks,0 subtract hopefully smaller trc in_order good, in order lda a_coreblocks,0 get higher stq a_coreblocks,0 store lower sta a_coreblocks+1,0 store higher stc1 pass_mod in_order: eax0 1,0 cmpx0 7,du tmi corelp1 trail down array szn pass_mod see if now in order tnz coresort reorder if any switching done tsx2 headform skip to top ldx0 0,du index through coreblocks dumplp: lda a_coreblocks,0 pick up core word cmpa =-1 see if no core there tze end_dmplp ana -1,dl get number of pages arl 4 in 1024's eax1 0,al into index 1 lda a_coreblocks,0 arl 18 get starting address als 6 in words dlp: tsx2 absresolve do a page tra d_error sta dump_temp tsx2 print print result lda dump_temp ada page_size,dl eax1 -1,1 see if done tpnz dlp end_dmplp: eax0 1,0 cmpx0 8,du see if all blocks done tmi dumplp tra cycle a_coreblocks: bss ,8 array or coreblocks words, will be sorted pass_mod: dec 0 exchange sort switch dump_temp: oct 0 d_error: sta arg tra num_err " include cache_print include cache printing package " cache: tsx2 check_cpu_type cmpa =1,dl is it a dps8 ? tnz cl68 we have a L68 canq =o100000,dl check for cache tnz cdps8_8k we have cache tsx2 erpt acc 'there is no 8k cache on this cpu' tra cycle cdps8_8k: lda 511*4,dl init size variables for sta ccolm1x4 8k cache lda 8192-1,dl sta clstcadd lda -8192,dl sta cnegcsz lda 512*4,dl sta ccolx4 lda =o4000,du sta cclvincr tra ccont ccolm1x4: bss ,1 column -1 * 4 clstcadd: bss ,1 last cache address cnegcsz: bss ,1 comp. of cache size cclvincr: bss ,1 cache level incrementor ccolx4: bss ,1 column * 4 cl68: canq =o400,dl check for cache tnz cl68_2k we have cache tsx2 erpt acc 'there is no 2k cache on this cpu' tra cycle cl68_2k: lda 127*4,dl init size variables for sta ccolm1x4 2k cache lda 2048-1,dl sta clstcadd lda -2048,dl sta cnegcsz lda 128*4,dl sta ccolx4 lda =o1000,du sta cclvincr ccont: tsx2 print_cache_header get necessary hdr out lda 0,dl init cacheaddr clp: sta cacheaddr tsx2 print_cache_block print the normal cache block eax0 -4 count levels eax1 0 count contents clp2: lda cache_dir+4,0 look at ctl word cana cmr.level_full,du see if stuff there " " " " Change following instruction to " " tze clp2end " " to cause empty cache blocks not to be checked. " nop clp2end ignore no-fulls ana cmr.address_mask,du isolate addr arl cmr.address_shift ada cacheaddr sta cadr_temp tsx2 absresolve analyze contents tra cnocore notify printed output of no core tsx2 print print out analysis ldaq cache_contents,1 look at cache cmpaq contents see if looks like core tnz cnogo ldaq cache_contents+2,1 cmpaq contents+2 tze clp2end this is ok cnogo: tsx2 space clear out line lda =hdiffer ldq =hs- cor sta line print out core contents stq line+1 lda =he = " sta line+2 eax7 -4 count words eax6 contents print core, not cache eax5 line+3 count output clp3: lda =h " sta 0,5 store delim lda 0,6 get first word tsx2 octwd convert sta 1,5 store to line stq 2,5 eax5 3,5 move on along line eax6 1,6 move along contents eax7 1,7 move along count tmi clp3 tsx2 print print "different" line clp2end: eax1 4,1 move along cache contents eax0 1,0 move count tmi clp2 loop along blocks tsx2 space tsx2 print lda cacheaddr ada 4,dl go to next block address cmpa ccolx4 see if whole cache scanned tmi clp tra cycle done; cacheaddr: oct 0 cadr_temp: oct 0 temp for full cache address cnocore: tsx2 space blank buffer mlr (),() move in message desc6a ncomes,13 desc6a line,13 lda cadr_temp tsx2 octwd convert address to octal sta line+3 stq line+4 tsx2 print tra clp2end ncomes: bci 'no such core:' " include absresolve even fault_temp: bss ,2 patch_room: bss ,128 end " " " ----------------------------------------------------------- " " " " Historical Background " " This edition of the Multics software materials and documentation is provided and donated " to Massachusetts Institute of Technology by Group Bull including Bull HN Information Systems Inc. " as a contribution to computer science knowledge. " This donation is made also to give evidence of the common contributions of Massachusetts Institute of Technology, " Bell Laboratories, General Electric, Honeywell Information Systems Inc., Honeywell Bull Inc., Groupe Bull " and Bull HN Information Systems Inc. to the development of this operating system. " Multics development was initiated by Massachusetts Institute of Technology Project MAC (1963-1970), " renamed the MIT Laboratory for Computer Science and Artificial Intelligence in the mid 1970s, under the leadership " of Professor Fernando Jose Corbato. Users consider that Multics provided the best software architecture for " managing computer hardware properly and for executing programs. Many subsequent operating systems " incorporated Multics principles. " Multics was distributed in 1975 to 2000 by Group Bull in Europe , and in the U.S. by Bull HN Information Systems Inc., " as successor in interest by change in name only to Honeywell Bull Inc. and Honeywell Information Systems Inc. . " " ----------------------------------------------------------- " " Permission to use, copy, modify, and distribute these programs and their documentation for any purpose and without " fee is hereby granted,provided that the below copyright notice and historical background appear in all copies " and that both the copyright notice and historical background and this permission notice appear in supporting " documentation, and that the names of MIT, HIS, Bull or Bull HN not be used in advertising or publicity pertaining " to distribution of the programs without specific prior written permission. " Copyright 1972 by Massachusetts Institute of Technology and Honeywell Information Systems Inc. " Copyright 2006 by Bull HN Information Systems Inc. " Copyright 2006 by Bull SAS " All Rights Reserved " "