/* BEGIN INCLUDE FILE gtss_FMS_catalog.incl.pl1 */ /* Created: (Wardd Multics) 09/14/78 1813.7 mst Thu Change: Paul Benjamin 10/12/79 Further break down FS0_PBK_05 */ /** The structure FMS_catalog1 is from FMS PROGRAM LOGIC MANUAL DC26, Rev. 0, January 1974 Page 4-9 **/ dcl FMS_cat_ptr ptr init(null()); dcl 1 FMS_catalog aligned based(FMS_cat_ptr) , 3 FSnTYP_0 , 4 bits00_05 bit(06)unal , 4 bits06_10 bit(05)unal , 4 bits11_17 bit(07)unal , 4 bits18_35 bit(18)unal , 3 FSnNLL_1 , 4 bits00_17 bit(18)unal , 4 bits18_35 bit(18)unal , 3 FSnPLL_2 , 4 bits00_17 bit(18)unal , 4 bits18_35 bit(18)unal , 3 FSnPTP_3 , 4 bits00_17 bit(18)unal , 4 bits18_35 bit(18)unal , 3 FSnCBK_4 , 4 bits00_17 bit(18)unal , 4 bits18_35 bit(18)unal ; /** Page 4-10. **/ dcl 1 Type_0_Catalog aligned based(FMS_cat_ptr) , 3 FS0_TYP_00 bit(36) , 3 FS0_NLL_01 , 4 bits00_17 bit(18)unal , 4 bits18_35 bit(18)unal , 3 FS0_PLL_02 bit(36) , 3 FS0_PTP_03 , 4 bits00_17 fixed bin(17)unal , 4 bits18_35 bit(18)unal , 3 FS0_CBK_04 , 4 bits00_17 fixed bin(17)unal , 4 bits18_35 bit(18)unal , 3 FS0_PBK_05 , 4 bits00_17 bit(18)unal , 4 bits18_35 bit(18)unal , 3 FS0_CNM_06_07 bit(72) , 3 FS0_ORG_10_11 bit(72) , 3 FS0_PWD_12_13 bit(72) , 3 FS0_CDT_14 bit(36) , 3 FS0_MOD_15 bit(36) , 3 FS0_IND_16 bit(36) , 3 FS0_PER_17 , 4 bits00_11 bit(12)unal , 4 bits12_14 bit(03)unal , 4 bit15 bit(01)unal , 4 bit16 bit(01)unal , 4 bit17 bit(01)unal , 4 bits18_35 bit(18)unal , 3 FS0_OP1_20 bit(36) , 3 FS0_OP2_21 bit(36) , 3 FS0_VAR_22_76 (15) , 4 FS0_SNM_00_01 bit(72) , 4 FS0_SPT_02 , 5 bit00 bit(01)unal , 5 bit01 bit(01)unal , 5 bits02_17 bit(16)unal , 5 bits18_35 bit(18)unal , 3 checksum_77 bit(36) ; /* Condensed form of type 0 record. */ dcl 1 t0c aligned based(FMS_cat_ptr) , 2 fill (0:17)bit(36) , 2 name (15) , 3 bcd bit(72) , 3 more bit(36) ; /** Page 4-10. **/ dcl Type_1_ptr ptr init(null()); dcl 1 Type_1_Catalog aligned based(Type_1_ptr) , 3 FS1_TYP_00 bit(36) , 3 FS1_NLL_01 , 4 bits00_17 bit(18)unal , 4 bits18_35 bit(18)unal , 3 FS1_PLL_02 bit(36) , 3 FS1_PTP_03 , 4 bits00_17 fixed bin(17)unal , 4 bits18_35 bit(18)unal , 3 FS1_CBK_04 , 4 bits00_17 bit(18)unal , 4 bits18_35 bit(18)unal , 3 FS1_OPN_05 bit(36) , 3 FS1_VAR_06_76 (19) , 4 FS1_SNM_00_01 bit(72) , 4 FS1_SPT_02 , 5 bit00 bit(01)unal , 5 bit01 bit(01)unal , 5 bits02_17 bit(16)unal , 5 bits18_35 bit(18)unal , 3 checksum_77 bit(36) ; /* Condensed form of type 1 record. */ dcl 1 t1c aligned based(FMS_cat_ptr) , 2 fill (0:5)bit(36) , 2 name (19) like t0c.name ; /** Page 4-11. **/ dcl 1 Type_2_Catalog aligned based(FMS_cat_ptr) , 3 FS2_TYP_00 bit(36) , 3 FS2_NLL_01 bit(36) , 3 FS2_PLL_02 bit(36) , 3 FS2_PTP_03 bit(36) , 3 FS2_CBK_04 bit(36) , 3 FS2_PBK_05 , 4 bits00_17 bit(18)unal , 4 bits18_35 bit(18)unal , 3 FS2_FNM_06_07 bit(72) , 3 FS2_ORG_10_11 bit(72) , 3 FS2_PWD_12_13 bit(72) , 3 FS2_CDT_14 bit(36) , 3 FS2_MOD_15 bit(36) , 3 FS2_IND_16 bit(36) , 3 FS2_PER_17 , 4 bits00_11 bit(12)unal , 4 bits12_15 bit(04)unal , 4 bit16 bit(01)unal , 4 bit17 bit(01)unal , 4 bits18_35 bit(18)unal , 3 FS2_MTR_20_21 bit(72) , 3 FS2_FU1_22 , 4 bit00 bit(01)unal , 4 bit01 bit(01)unal , 4 bit02 bit(01)unal , 4 bit03 bit(01)unal , 4 bit04 bit(01)unal , 4 bit05 bit(01)unal , 4 bit06 bit(01)unal , 4 bit07 bit(01)unal , 4 bit08 bit(01)unal , 4 bit09 bit(01)unal , 4 bits10_11 bit(02)unal , 4 bits12_17 bit(06)unal , 4 bits18_35 bit(18)unal , 3 FS2_FUS_23 , 4 bits00_17 bit(18)unal , 4 bit18 bit(01)unal , 4 bit19 bit(01)unal , 4 bit20 bit(01)unal , 4 bit21 bit(01)unal , 4 bit22 bit(01)unal , 4 bit23 bit(01)unal , 4 bit24 bit(01)unal , 4 bit25 bit(01)unal , 4 bit26 bit(01)unal , 4 bit27 bit(01)unal , 4 bit28 bit(01)unal , 4 bit29 bit(01)unal , 4 bits30_35 bit(06)unal , 3 FS2_USI_24 , 4 bit00 bit(01)unal , 4 bits01_35 bit(35)unal , 3 FS2_FU2_25 , 4 bit00 bit(01)unal , 4 bit01 bit(01)unal , 4 bit02 bit(01)unal , 4 bit03 bit(01)unal , 4 bit04 bit(01)unal , 4 bit05 bit(01)unal , 4 bit06 bit(01)unal , 4 bit07 bit(01)unal , 4 bit08 bit(01)unal , 4 bit09 bit(01)unal , 4 bit10 bit(01)unal , 4 bit11 bit(01)unal , 4 bit12 bit(01)unal , 4 bit13 bit(01)unal , 4 bit14 bit(01)unal , 4 bit15 bit(01)unal , 4 bit16 bit(01)unal , 4 bit17 bit(01)unal , 4 bits18_35 bit(18)unal , 3 FS2_LCD_26 bit(36) , 3 FS2_LAD_27 bit(36) , 3 FS2_LST_30 , 4 bits00_05 bit(06)unal , 4 bits06_35 bit(30)unal , 3 FS2_ATB_31 bit(36) , 3 FS2_PDF_32 bit(36) , 3 FS2_STC_33 bit(36) , 3 FS2_BSY_34 bit(36) , 3 FS2_TBC_35 bit(36) , 3 FS2_OP2_7_36_43 (2:7)bit(36) , 3 FS2_VAR_44_75 , 4 Device_descriptor , 5 bits00_03 bit(04)unal /* 0101 */ , 5 bits04_05 bit(02)unal , 5 bits06_35 bit(30)unal , 4 Space_descriptor , 5 bit00 bit(01)unal , 5 bit01 bit(01)unal /* =0 => space desc. */ , 5 bit02 bit(01)unal , 5 bits03_17 bit(15)unal , 5 bits18_35 bit(18)unal , 4 zero (24)bit(36) , 3 zero_76 bit(36) , 3 checksum_77 bit(36) ; /** Page 4-13. **/ dcl Type_4_ptr ptr init(null()); dcl 1 Type_4_Catalog aligned based(Type_4_ptr) , 3 FS4_TYP_00 bit(36) , 3 FS4_NLL_01 bit(36) , 3 FS4_PLL_02 bit(36) , 3 FS4_PTP_03 bit(36) , 3 FS4_CBK_04 bit(36) , 3 FS4_OP1_2_05_06 bit(72) , 3 FS4_VAR_07_75 bit(1980) /* 1980 = 55 * 36bits @ */ , 3 zero bit(36) , 3 checksum_77 bit(36) ; /** Page 2-69 **/ dcl buffer_ptr ptr init(null()); dcl 1 callers_buffer aligned based(buffer_ptr) , 3 first25 (25)bit(36) /* Work area for ???. */ /** Next 35 words. FMS work area. **/ , 3 W00_FSCODE bit(036) , 3 W01_02_FSCALL bit(072) , 3 W03 bit(036) , 3 W04_06 bit(108) , 3 W07 bit(036) , 3 W10 bit(036) , 3 W11_12 bit(072) , 3 W13_FSSSLV bit(036) , 3 W14_15 bit(072) , 3 W16_FSFBSY bit(036) , 3 W17_FSRETP bit(036) , 3 W20 , 4 FSMME unal , 5 bits00_17 bit(18)unal , 4 FSARG unal , 5 bits18_35 bit(18)unal , 3 W21_FSCPOS , 4 bits00_17 bit(18)unal , 4 bits18_35 bit(18)unal , 3 W22_FSCCFP , 4 bits00_17 bit(18)unal , 4 bits18_35 bit(18)unal , 3 W23_FSPCFP , 4 bits00_17 bit(18)unal , 4 bits18_35 bit(18)unal , 3 W24 , 4 FSREGU unal , 5 bits00_17 bit(18)unal , 4 FSREGL unal , 5 bits18_35 bit(18)unal , 3 W25_FSCDEV , 4 bits00_15 bit(16)unal , 4 bit16 bit(01)unal , 4 bit17 bit(01)unal , 4 bits18_35 bit(18)unal , 3 W26_FSDDEV , 4 bits00_15 bit(16)unal , 4 bit16 bit(01)unal , 4 bit17 bit(01)unal , 4 bits18_35 bit(18)unal , 3 W27_FSENDT bit(036) , 3 W30_FSCPAT bit(036) , 3 W31_FSPERM bit(036) , 3 W32_FSDDCW bit(036) , 3 W33_FSDCWP bit(036) , 3 W34_FSDUPD bit(036) , 3 W35_FSAVBL bit(036) , 3 W36_FSTEMP bit(036) , 3 W37_FSCKSM bit(036) , 3 W40_FSIOS1 bit(036) , 3 W41_FSSRW1 bit(036) , 3 W42_FSSRW2 bit(036) , 3 W43_FSBFER bit(036) /* Starting location of buffer for catalog record(s). */ , 3 remainder_of_buffer (319)bit(36) ; /* END INCLUDE FILE gtss_FMS_catalog.incl.pl1 */ */ ----------------------------------------------------------- Historical Background This edition of the Multics software materials and documentation is provided and donated to Massachusetts Institute of Technology by Group Bull including Bull HN Information Systems Inc. as a contribution to computer science knowledge. This donation is made also to give evidence of the common contributions of Massachusetts Institute of Technology, Bell Laboratories, General Electric, Honeywell Information Systems Inc., Honeywell Bull Inc., Groupe Bull and Bull HN Information Systems Inc. to the development of this operating system. Multics development was initiated by Massachusetts Institute of Technology Project MAC (1963-1970), renamed the MIT Laboratory for Computer Science and Artificial Intelligence in the mid 1970s, under the leadership of Professor Fernando Jose Corbato. Users consider that Multics provided the best software architecture for managing computer hardware properly and for executing programs. Many subsequent operating systems incorporated Multics principles. Multics was distributed in 1975 to 2000 by Group Bull in Europe , and in the U.S. by Bull HN Information Systems Inc., as successor in interest by change in name only to Honeywell Bull Inc. and Honeywell Information Systems Inc. . ----------------------------------------------------------- Permission to use, copy, modify, and distribute these programs and their documentation for any purpose and without fee is hereby granted,provided that the below copyright notice and historical background appear in all copies and that both the copyright notice and historical background and this permission notice appear in supporting documentation, and that the names of MIT, HIS, Bull or Bull HN not be used in advertising or publicity pertaining to distribution of the programs without specific prior written permission. Copyright 1972 by Massachusetts Institute of Technology and Honeywell Information Systems Inc. Copyright 2006 by Bull HN Information Systems Inc. Copyright 2006 by Bull SAS All Rights Reserved */