/*     BEGIN INCLUDE FILE ... history_regs_dps8.incl.pl1
   *      ... created by R. L. Coppola 8/80. */
/*     Modified Sept, 1981 by Rich Coppola to reflect changes made in the CPU */

dcl (du_ouhrp, cuhrp, aphrp1, aphrp2, hr_data_ptr) ptr;
dcl  nregs fixed bin;				/* number of history registers saved (16/64) */


dcl 1 ext_hr based (hr_data_ptr),			/* History Register data */
    2 DU_OU (nregs),
      3 even bit (36),
      3 odd bit (36),
    2 CU (nregs),
      3 even bit (36),
      3 odd bit (36),
    2 AU2 (nregs),
      3 even bit (36),
      3 odd bit (36),
    2 AU1 (nregs),
      3 even bit (36),
      3 odd bit (36);



dcl  du_ou_offset fixed bin init (0),			/* offsets to hr data within the hr data block */
     cu_offset fixed bin init (32),
     au_offset2 fixed bin init (64),
     au_offset1 fixed bin init (96);


dcl 1 cuhra (nregs) like cuhr;			/* copy of HR data (corrected) */

dcl 1 cuhr (nregs) based (cuhrp) aligned,
   (2 pia bit (1),					/* preparing instruction address */
    2 poa bit (1),					/* preparing operand address */
    2 riw bit (1),					/* requesting indirect word */
    2 siw bit (1),					/* restoring indirect word */
    2 pot bit (1),					/* preparing operand tally */
    2 pon bit (1),					/* preparing operand address */
    2 raw bit (1),					/* requesting alter-rewrite word  (complemented) */
    2 saw bit (1),					/* restoring alter-rewrite word */
    2 rtrgo bit (1),				/* remember transfer go - condition met */
    2 xde bit (1),					/* XED from even location */
    2 xdo bit (1),					/* XED from odd location */
    2 ic bit (1),					/* even/odd inst. pair */
    2 rpts bit (1),					/* repeat operation */
    2 portf bit (1),				/* memory cycle to port  on previous cycle */
    2 internal bit (1),				/* memory cycle to cache or direct on previous cycle */
    2 pai bit (1),					/* prepare interrupt address */
    2 pfa bit (1),					/* prepare FLT address */
    2 master_mode bit (1),				/* in master mode */
    2 op_code bit (10),				/* op code of inst */
    2 inhib bit (1),				/* inhibit int bit */
    2 its_flag bit (1),				/* ar reg mod flag */
    2 tag bit (6),					/* tag field of instr */
    2 ca_value bit (24),				/* 24 bit address field of inst */
    2 pcmd bit (5),					/* processor command register */
    2 xint bit (1),					/* execute interrupt */
    2 ins_fetch bit (1),				/* inst fetch */
    2 cache_rd bit (1),				/* cache read cycle  this cycle */
    2 mem_rd bit (1),				/* memory read this cycle */
    2 mem_sto bit (1),				/* memory store this cycle */
    2 pib bit (1),					/* port interface busy */
    2 cache_flush bit (1)) unaligned;

dcl 1 du_ouhr (nregs) based (du_ouhrp) aligned,
   (2 fanld1 bit (1),				/* alpha-num load desc 1 (complemented) */
    2 fanld2 bit (1),				/* alpha-num load desc 2 (complemented) */
    2 fanstr bit (1),				/* alpha-num store  (complemented) */
    2 fldwrt1 bit (1),				/* load re-write reg 1 (complemented) */
    2 fldwrt2 bit (1),				/* load re-write reg 2 (complemented) */
    2 fnld1 bit (1),				/* numeric load desc 1 (complemented) */
    2 fnld2 bit (1),				/* numeric load desc 2 (complemented) */
    2 endseqf bit (1),				/*  end sequence flag */
    2 fdud bit (1),					/* decimal unit idle (complemented) */
    2 fgstr bit (1),				/* general store flag (complemented) */
    2 endseq bit (1),				/* end of sequence (complemented) */
    2 nine bit (1),					/* 9-bit char. operation */
    2 six bit (1),					/* 6-bit char. operation */
    2 four bit (1),					/* 4-bit char operation */
    2 du_bit bit (1),				/* Bit operation */
    2 du_word bit (1),				/* Word operation */
    2 ptr1 bit (1),					/* select ptr 1 */
    2 ptr2 bit (1),					/* select ptr 2 */
    2 ptr3 bit (1),					/* select ptr 3 */
    2 fpop bit (1),					/* prepare operand pointer */
    2 fgeac bit (1),				/* add cycle gate C (complemented) */
    2 fgeae bit (1),				/* add cycle gate E (complemented) */
    2 fgeaf bit (1),				/* add cycle gate F(complemented) */
    2 fgeah bit (1),				/* add cycle gate H (complemented) */
    2 fgldp1 bit (1),				/* load PTR #1  (complemented) */
    2 fsweq bit (1),				/* single word sequence flag (complemented) */
    2 fgch bit (1),					/* character cycle (complemented) */
    2 dfrst bit (1),				/* processing descriptor for first time  */
    2 exh bit (1),					/* exhaust */
    2 fgadd bit (1),				/* add cycle  (complemented) */
    2 intrptd bit (1),				/* interrupted */
    2 dcode,
      3 gldp2 bit (1),				/* ldp2 (complemented) */
      3 gemc bit (1),				/* exponent control */
      3 gbda bit (1),				/* bin to dec gate A */
      3 gsp5 bit (1),				/* shift timing gate */
      3 dcode_pad bit (1),
    2 ict bit (18),					/* Instruction counter */
    2 rs bit (9),					/* OU op-code register (RS0-8) */
    2 ir_reg,					/* the indicator reg */
      3 zero_ bit (1),
      3 sign_ bit (1),
      3 carry_ bit (1),
      3 ovfl_ bit (1),
      3 eovfl_ bit (1),
      3 eufl_ bit (1),
      3 oflm_ bit (1),
      3 hex_ bit (1),
    2 dtrgo bit (1)) unaligned;			/* transfer go */


dcl 1 apuhr1 (nregs) based (aphrp1) aligned,
   (2 esn bit (15),				/* effective segment number for this cycle */
						/* bits 11-14 contain the */
						/* SDWAM addr selected */
    2 piapgbsy bit (1),				/* ins fetch across a page bndry */
    2 piaoosb bit (1),				/* ins fetch OOSB */
    2 fdsptw bit (1),				/* fetch of dseg PTW */
    2 mdsptw bit (1),				/* mod of dseg PTW */
    2 fsdwp bit (1),				/* fetch paged SDW */
    2 fptw bit (1),					/* fetch PTW */
    2 fptw2 bit (1),				/* fetch PTW + 1 */
    2 mptw bit (1),					/* modify PTW */
    2 fanp bit (1),					/* fetch final add from non-paged seg */
    2 fap bit (1),					/* fetch final addr paged */
    2 mtchsdw bit (1),				/* SDW match in AM */
    2 sdwmf bit (1),				/* SDWAM match occurred and used */
    2 bsy bit (2),					/* data source for ESN */
						/* 00 = from ppr.psr */
						/* 01 = from prn.tsr */
						/* 10 = from tpr.snr */
						/* 11 = from tpr.ca */
    2 ptwmf bit (1),				/* PTW match in AM */
    2 mtchptw bit (1),				/* PTWAM match occurred */
    2 ptwaddr bit (4),				/* addr sel for PTWAM (tpr.ca)4,7 */
    2 flt bit (1),					/* ACV or DF flt caused by this cycle */
    2 finadd bit (24),				/* absolute address of this cycle */
    2 trr bit (3),					/* value of tpr.trr for this cycle */
    2 sdwerr bit (1),				/* multi-mtch or parity err in SDWAM */
    2 sdwlvl bit (2),				/* SDWAM level selected */
    2 cache_used bit (1),				/* CPU used cache for this cycle */
    2 ptwerr bit (1),				/* multi-match or parity err in PTWAM */
    2 ptwlvl bit (2),				/* PTWAM level selected */
    2 flthld bit (1),				/* an ACV or DF flt is waiting to be processed */
    2 apu_pad2 bit (1))unaligned;

dcl 1 apuhr2 (nregs) based (aphrp2) aligned,
    (2 CA bit (18),					/* tpr.ca */
    2 opcode bit (10),				/* opcode from cur instr */
    2 inhibit_bit bit (1),				/* interrupt inhib bit */
    2 pr_flag bit (1),				/* PR mod flag */
    2 TAG bit (6),					/* mod. tag field */
    2 pad1 bit (36))unaligned;


/* END INCLUDE FILE ... history_regs_dpse.incl.pl1 */


*/
                                          -----------------------------------------------------------


Historical Background

This edition of the Multics software materials and documentation is provided and donated
to Massachusetts Institute of Technology by Group Bull including Bull HN Information Systems Inc. 
as a contribution to computer science knowledge.  
This donation is made also to give evidence of the common contributions of Massachusetts Institute of Technology,
Bell Laboratories, General Electric, Honeywell Information Systems Inc., Honeywell Bull Inc., Groupe Bull
and Bull HN Information Systems Inc. to the development of this operating system. 
Multics development was initiated by Massachusetts Institute of Technology Project MAC (1963-1970),
renamed the MIT Laboratory for Computer Science and Artificial Intelligence in the mid 1970s, under the leadership
of Professor Fernando Jose Corbato. Users consider that Multics provided the best software architecture for 
managing computer hardware properly and for executing programs. Many subsequent operating systems 
incorporated Multics principles.
Multics was distributed in 1975 to 2000 by Group Bull in Europe , and in the U.S. by Bull HN Information Systems Inc., 
as successor in interest by change in name only to Honeywell Bull Inc. and Honeywell Information Systems Inc. .

                                          -----------------------------------------------------------

Permission to use, copy, modify, and distribute these programs and their documentation for any purpose and without
fee is hereby granted,provided that the below copyright notice and historical background appear in all copies
and that both the copyright notice and historical background and this permission notice appear in supporting
documentation, and that the names of MIT, HIS, Bull or Bull HN not be used in advertising or publicity pertaining
to distribution of the programs without specific prior written permission.
    Copyright 1972 by Massachusetts Institute of Technology and Honeywell Information Systems Inc.
    Copyright 2006 by Bull HN Information Systems Inc.
    Copyright 2006 by Bull SAS
    All Rights Reserved

*/